CN108110008B - Semiconductor element and manufacturing method thereof and manufacturing method of memory - Google Patents
Semiconductor element and manufacturing method thereof and manufacturing method of memory Download PDFInfo
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- CN108110008B CN108110008B CN201611054276.3A CN201611054276A CN108110008B CN 108110008 B CN108110008 B CN 108110008B CN 201611054276 A CN201611054276 A CN 201611054276A CN 108110008 B CN108110008 B CN 108110008B
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- trench
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- isolation material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Abstract
Disclosure of the inventionA semiconductor device and a method of manufacturing the same and a method of manufacturing a memory are provided. The method for manufacturing a semiconductor element includes: forming a first channel and a second channel in the substrate and the material layer on the substrate, wherein the width of the first channel is smaller than that of the second channel; forming a covering material layer and filling the first and second channels with the flowable isolation material; removing part of the flowable isolation material in the second trench to a thickness between the flowable isolation material on the sidewalls of the second trench
To
To (c) to (d); a non-flowable insulation material is formed on the flowable insulation material.
Description
Technical Field
The invention relates to a semiconductor element and a manufacturing method thereof and a manufacturing method of a memory.
Background
In a conventional semiconductor process, an isolation structure is usually formed in a substrate to define an active region and a peripheral region. For the process of the nonvolatile memory, a memory cell area is defined between the isolation structures occupying a large layout area, and the isolation structures occupying a small layout area also exist in the memory cell area. As the size of the devices continues to shrink, isolation materials are filled into trenches formed in the substrate during the formation of the isolation structures to prevent voids in the formed isolation structures. Various techniques for isolation structures are currently being developed to improve device performance.
Disclosure of Invention
The invention provides a method for manufacturing a semiconductor element, which can avoid the damage to the side wall and the bottom of a channel when an isolation structure is formed and can avoid the problem of dislocation caused by stress generated by the isolation structure.
The invention provides a semiconductor element formed by the manufacturing method.
The invention provides a method for manufacturing a memory, which can manufacture a memory with better reliability.
The method for manufacturing a semiconductor element of the present invention includes the steps of: on the substrateForming a material layer; forming a first channel and a second channel in the material layer and the substrate, wherein the width of the first channel is smaller than that of the second channel; forming a flowable isolation material to cover the material layer and fill the first channel and the second channel; removing a portion of the flowable isolation material in the second trench such that the flowable isolation material on sidewalls of the second trench has a thickness between
To
To (c) to (d); forming a non-flowable barrier material on the flowable barrier material.
In an embodiment of the method for manufacturing a semiconductor device of the present invention, a thickness of the flowable isolation material on the bottom of the second trench is greater than that of the flowable isolation material
In an embodiment of the method for manufacturing a semiconductor device of the present invention, after the forming of the first trench and the second trench and before the forming of the flowable isolation material, a buffer layer is formed on the substrate and the material layer.
In an embodiment of the method for manufacturing a semiconductor device of the present invention, the method further includes performing a curing process on the flowable isolation material.
In an embodiment of the method for manufacturing a semiconductor device of the present invention, a distance between the top surface of the flowable isolation material located on the bottom of the second trench and the top surface of the substrate is, for example, 1/3 which is greater than a distance between the top surface of the substrate and the bottom of the second trench.
The semiconductor element comprises a material layer, a first isolation material layer and a second isolation material layer. A material layer disposed on the substrate, wherein the material layer and the substrate have a first channel and a second channelAnd the width of the first channel is smaller than that of the second channel. The first isolation material layer is configured in the first trench and on the side wall and the bottom of the second trench. A second isolation material layer is disposed on the first isolation material layer in the second trench. In addition, the thickness of the first isolation material layer on the side wall of the second trench is between
To
In the meantime.
In an embodiment of the semiconductor device of the invention, a thickness of the portion of the first isolation material layer on the bottom of the second trench is greater than
In an embodiment of the semiconductor device of the present invention, a distance between the top surface of the first isolation material layer on the bottom of the second trench and the top surface of the substrate is greater than 1/3 of a distance between the top surface of the substrate and the bottom of the second trench.
The manufacturing method of the memory comprises the following steps: sequentially forming a gate dielectric material layer and a gate material layer on the substrate; forming a plurality of first channels and a plurality of second channels in the substrate, the gate dielectric material layer and the gate material layer, and defining a gate dielectric layer and a floating gate on the substrate, wherein the width of the first channels is smaller than that of the second channels; filling a flowable isolation material in the first trench and the second trench; removing a portion of the flowable isolation material in the second trench such that the flowable isolation material on sidewalls of the second trench has a thickness between
To
To (c) to (d); forming a non-flowable isolation material on the flowable isolation material in the second channel; removing a portion of the flowable isolation material in the first channel; forming an inter-gate dielectric layer on the floating gate; and forming a control gate on the inter-gate dielectric layer.
In an embodiment of the method for manufacturing a memory device of the present invention, a distance between the top surface of the flowable isolation material on the bottom of the second trench and the top surface of the substrate is greater than 1/3 of a distance between the top surface of the substrate and the bottom of the second trench.
Based on the above, in the present invention, after filling the larger trench with the flowable isolation material, a portion of the flowable isolation material in the trench is removed and then the subsequent processes are performed. Therefore, the stress can be effectively released to solve the dislocation problem caused by the isolation material, thereby improving the reliability of the device.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a manufacturing process of a nonvolatile memory according to an embodiment of the invention.
[ notation ] to show
100: substrate
102: layer of gate dielectric material
102 a: gate dielectric layer
104: grid material layer
104 a: floating gate
106: first channel
108: second channel
110: buffer layer
112: flowable barrier material
114: patterned mask layer
116. 118: isolation structure
120: inter-gate dielectric layer
122: control grid
D1, D2: distance between two adjacent plates
T1, T2: thickness of
Detailed Description
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a manufacturing process of a nonvolatile memory according to an embodiment of the invention.
First, referring to fig. 1A, a material layer is formed on a substrate 100. The substrate 100 is, for example, a silicon substrate. In the present embodiment, the material layers include a gate dielectric material layer 102 and a gate material layer 104 sequentially formed on the substrate 100. In other embodiments, if the semiconductor device to be formed is not a nonvolatile memory, the material layer may be other types of layers according to actual requirements. In the present embodiment, the gate dielectric material layer 102 is, for example, an oxide layer, and the gate material layer 104 is, for example, a polysilicon layer or a metal layer. In an embodiment of the non-volatile memory, the layer of gate dielectric material 102 acts as a tunneling dielectric layer in the memory region. Electrons can pass through the tunneling dielectric layer and be stored in the floating gate. In the logic device region, the gate dielectric material layer 102 serves as a gate dielectric layer of a Field Effect Transistor (FET). In some embodiments, a hard mask layer (not shown) is formed on the gate material layer 104. The hard mask layer may comprise a composition of oxygen or nitrogen.
Then, referring to fig. 1B, a plurality of first trenches 106 and a plurality of second trenches 108 are formed in the substrate 100, the gate dielectric material layer 102 and the gate material layer 104, wherein the width of the first trenches 106 is smaller than the width of the second trenches 108. In fig. 1B, only two first channels 106 and two second channels 108 are illustrated for clarity, but the number of the first channels 106 and the second channels 108 is not limited thereto. In the present embodiment, the second trench 108 surrounds the first trench 106, and the first trench 106 and the second trench 108 define the substrate 100 with a memory cell region having the first trench 106 and a peripheral region having the second trench 108. The first channel 106 and the second channel 108 are formed by, for example, patterning the gate material layer 104, the gate dielectric material layer 102, and the substrate 100. In addition, after the patterning process, the gate material layer 104 and the gate dielectric material layer 102 are respectively defined as a floating gate 104a and a gate dielectric layer 102 a.
Referring to fig. 1C, a buffer layer 110 is selectively formed on the substrate 100. in the present embodiment, the buffer layer 110 is conformally formed on the substrate 100 to cover the floating gate 104a, the gate dielectric layer 102a and the substrate 100. the buffer layer 110 is, for example, an oxide layer, and is formed by, for example, performing an atomic layer deposition (a L D) process or a High Temperature Oxidation (HTO) process, and the buffer layer 110 has a thickness, for example, between the thicknesses of the buffer layer 110 and the substrate 100
To
In the meantime. Then, a fluid isolation material 112 is formed on the substrate 100 to cover the floating gate 104a and fill the first channel 106 and the second channel 108. The flowable isolation material 112 is, for example, an oxide material, which is formed on the substrate 100 by spin coating, for example. The flowable isolation material 112 may include a silicate or Methylsilsesquioxane (MSQ). Since the flowable isolation material 112 has a higher flowability than a material formed by a conventional deposition process, it can be effectively filled into the first trench 106 and the second trench 108 without voids after filling the first trench 106 having a smaller width due to poor flowability. Thereafter, the flow separation material 112 may be subjected to a semi-curing treatment. The semi-curing treatment is performed at a temperature of 200 to 300 ℃ for 10 to 30 minutes under water vapor or oxygen, for example.
In particular, in the present embodiment, since the buffer layer 110 is formed before the flowable isolation material 112 is formed, the problem of the degradation of the device reliability caused by the flowable isolation material 112 entering the floating gate 104a, the gate dielectric layer 102a or the substrate 100 during the process can be avoided.
In addition, when the flowable isolation material 112 is subjected to a semi-curing process, the flowable isolation material 112 in the wider second channel 108 generates a larger stress, which may cause dislocation between the surrounding substrate 100 and the floating gate 104 a. Thus, in the following step, a portion of the flowable isolation material 112 in the second channel 108 is removed to relieve the stress.
Then, referring to fig. 1D, a patterned mask layer 114 is formed on the semi-cured flowable isolation material 112. The patterned masking layer 114 exposes portions of the flowable isolation material 112 over the second trenches 108, such as exposing the flowable isolation material 112 over central portions of the second trenches 108. The patterned mask layer 114 is, for example, a patterned photoresist layer. Next, an anisotropic etching process is performed to remove a portion of the exposed flowable isolation material 112 by using the patterned mask layer as an etching mask. In detail, after removing a portion of the exposed flowable isolation material 112, the flowable isolation material 112 remaining in the second trench 108 is required to satisfy the following conditions: the thickness T1 of the flowable isolation material 112 on the sidewalls of the second trench 108 is between
To
The thickness T1 of the flowable isolation material 112 on the sidewalls of the second trench 108 is substantially uniform; the distance D1 between the top surface of the flowable isolation material 112 on the bottom of the second channel 108 and the top surface of the substrate 100 is greater than 1/3 of the distance D2 between the top surface of the substrate 100 and the bottom of the second channel 108. Furthermore, in the present embodiment, the thickness T2 of the flowable isolation material 112 on the bottom of the second trench 108 is, for example, greater than
When the thickness T1 exceeds
The purpose of releasing the stress cannot be effectively achieved. When the thickness T1 is less than
In this case, the substrate 100, the gate dielectric layer 102a and the floating gate 104a at the sidewall of the second trench 108 may be damaged in the etching process, and the dopant may be lost if the substrate 100 or the floating gate 104a has dopants. In addition, in the case where the distance D1 is not greater than 1/3 of the distance D2, the flowable isolation material 112 remains in the second trench 108 too much, and therefore, the stress release cannot be effectively achieved. However, the thickness T2 preferably needs to be greater than
So as to prevent the substrate 100 under the second trench 108 from being damaged during the etching process. In other words, when the thickness T1, the thickness T2 and the distance D1 are within the above ranges, the purpose of releasing stress can be effectively achieved, the substrate 100, the gate dielectric layer 102a and the floating gate 104a can be prevented from being damaged in the etching process, and the dopant loss in the substrate 100 or the floating gate 104a can be prevented, thereby improving the reliability of the subsequently formed device.
Next, referring to fig. 1E, after removing a portion of the flowable isolation material 112 in the second trench 108, the patterned mask layer 114 is removed. The flowable isolation material 112 is then subjected to a curing process. The curing treatment is, for example, a multistage curing treatment: the method is carried out at a temperature of 300 ℃ to 500 ℃ for 10 minutes to 30 minutes under water vapor or oxygen, then at a temperature of 500 ℃ to 800 ℃ for 10 minutes to 30 minutes under water vapor or oxygen, and then at a temperature of 800 ℃ to 1100 ℃ for 30 minutes to 60 minutes under nitrogen.
Then, a non-flowable isolation material is formed on the solidified flowable isolation material 112 in the second trench 108, and the non-flowable isolation material fills the second trench 108. The non-flowable isolation material is, for example, a high density plasma oxide material or an oxide material formed by enhanced high aspect ratio (eHARP) process. Then, a planarization process (e.g., a chemical mechanical polishing process) is performed to remove the non-flowable isolation material, the cured flowable isolation material 112 and the buffer layer 110 outside the second trench 108 until the floating gate 104a is exposed. As such, the isolation structure 116 (i.e., the solidified flowable isolation material 112 remaining in the second trench 108) and the isolation structure 118 located on the isolation structure 116 (i.e., the non-flowable isolation material remaining in the second trench 108) are formed in the second trench 108.
Then, referring to fig. 1F, a portion of the isolation structure 116 and a portion of the buffer layer 110 in the first channel 106 are removed to expose at least a portion of the sidewall of the floating gate 104a around the first channel 106. An inter-gate dielectric layer 120 is then formed on the top surface and sidewalls of the floating gate 104 a. The inter-gate dielectric layer 120 is formed, for example, by performing a chemical vapor deposition process to conformally form a multi-layer structure on the top surface and sidewalls of the floating gate 104 a. The inter-gate dielectric layer 120 may include two oxide layers and a nitride layer therebetween. Thereafter, a control gate 122 is formed on the intergate dielectric layer 120. The control gate 122 is made of polysilicon, for example, and is formed by a chemical vapor deposition process. The removed isolation structure 116 and the buffer layer 110 in the first channel 106 may increase the contact area between the floating gate 104a and the control gate 122. Therefore, the coupling ratio (coupling ratio) between the floating gate 104a and the control gate 122 can be increased, so that the device can have better performance.
In this embodiment, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the formation of a nonvolatile memory as an example. However, the semiconductor element of the present invention is not limited to the nonvolatile memory. In the above embodiments, the material layers are replaced according to actual requirements, and the steps described with reference to fig. 1A to 1E can be used to form other types of semiconductor devices. For example, when the material layer is a polysilicon layer, the isolation structure and the mos transistor located on the active region of the substrate defined by the isolation structure can be formed according to the steps described in fig. 1A to fig. 1E and by using appropriate processes.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the disclosed embodiments, but rather, may be embodied in many different forms and varied within the spirit and scope of the appended claims.
Claims (10)
1. A method for manufacturing a semiconductor device includes:
forming a material layer on a substrate;
forming a first channel and a second channel in the material layer and the substrate, wherein the width of the first channel is smaller than that of the second channel;
forming a flowable isolation material to cover the material layer and fill the first channel and the second channel;
removing a portion of the flowable isolation material in the second trench such that the flowable isolation material on sidewalls of the second trench has a thickness between
To
To (c) to (d); and
forming a non-flowable barrier material on the flowable barrier material.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the flowable isolation material on a bottom of the second trench is larger than that of the flowable isolation material
3. The method of claim 1, further comprising forming a buffer layer on the substrate and the material layer after forming the first trench and the second trench and before forming the flowable isolation material.
4. The method as claimed in claim 1, further comprising curing the flowable isolation material.
5. The method of claim 1, wherein a distance between a top surface of the flowable isolation material on the bottom of the second channel and a top surface of the substrate is greater than 1/3 of a distance between the top surface of the substrate and the bottom of the second channel.
6. A semiconductor component, comprising:
a material layer disposed on a substrate, wherein the material layer and the substrate have a first channel and a second channel, and a width of the first channel is smaller than a width of the second channel;
a first isolation material layer disposed in the first trench and on sidewalls and a bottom of the second trench; and
a second isolation material layer disposed on the first isolation material layer in the second trench, wherein the first isolation material layer on the sidewall of the second trench has a thickness between
To
In the meantime.
7. The semiconductor element of claim 6, wherein a thickness of a portion of the first isolation material layer on a bottom of the second trench is greater than a thickness of a portion of the first isolation material layer on a bottom of the second trench
8. The semiconductor component of claim 6 wherein a distance between a top surface of the first layer of isolation material on the bottom of the second channel and a top surface of the substrate is greater than 1/3 of a distance between the top surface of the substrate and the bottom of the second channel.
9. A method of manufacturing a memory, comprising:
sequentially forming a gate dielectric material layer and a gate material layer on the substrate;
forming a plurality of first channels and a plurality of second channels in the substrate, the gate dielectric material layer and the gate material layer, and defining a gate dielectric layer and a floating gate on the substrate, wherein the width of the first channels is smaller than that of the second channels;
filling a fluid isolation material in the first trench and the second trench;
removing a portion of the flowable isolation material in the second trench such that the flowable isolation material on sidewalls of the second trench has a thickness between
To
To (c) to (d);
forming a non-flowable isolation material on the flowable isolation material in the second channel;
removing a portion of the flowable isolation material in the first channel;
forming an inter-gate dielectric layer on the floating gate; and
and forming a control grid on the inter-grid dielectric layer.
10. The method of claim 9, wherein a distance between a top surface of the flowable isolation material on the bottom of the second channel and a top surface of the substrate is greater than 1/3 of a distance between the top surface of the substrate and the bottom of the second channel.
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| CN201611054276.3A CN108110008B (en) | 2016-11-25 | 2016-11-25 | Semiconductor element and manufacturing method thereof and manufacturing method of memory |
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| CN201611054276.3A CN108110008B (en) | 2016-11-25 | 2016-11-25 | Semiconductor element and manufacturing method thereof and manufacturing method of memory |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329253B1 (en) * | 1999-11-05 | 2001-12-11 | Chartered Semiconductor Manufacturing Ltd. | Thick oxide MOS device used in ESD protection circuit |
| CN103474353A (en) * | 2012-06-08 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Fin and STI structure manufacturing method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4621414A (en) * | 1985-03-04 | 1986-11-11 | Advanced Micro Devices, Inc. | Method of making an isolation slot for integrated circuit structure |
| JPH11186379A (en) * | 1997-12-19 | 1999-07-09 | Sony Corp | Manufacture of semiconductor device |
| JP3691963B2 (en) * | 1998-05-28 | 2005-09-07 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP2003031650A (en) * | 2001-07-13 | 2003-01-31 | Toshiba Corp | Method for manufacturing semiconductor device |
| US6500712B1 (en) * | 2002-06-17 | 2002-12-31 | Mosel Vitelic, Inc. | Fabrication of dielectric in trenches formed in a semiconductor substrate for a nonvolatile memory |
| KR20060001196A (en) * | 2004-06-30 | 2006-01-06 | 주식회사 하이닉스반도체 | Method for formong isolation film of semiconductor device |
| KR100816749B1 (en) * | 2006-07-12 | 2008-03-27 | 삼성전자주식회사 | Device Isolation Layer, Nonvolatile Memory Device Having The Device Isolation Layer, and Methods Of Forming The Device Isolation Layer and The Semiconductor Device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329253B1 (en) * | 1999-11-05 | 2001-12-11 | Chartered Semiconductor Manufacturing Ltd. | Thick oxide MOS device used in ESD protection circuit |
| CN103474353A (en) * | 2012-06-08 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Fin and STI structure manufacturing method |
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