JPH11186379A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device having superior characteristics and high reliability, even when mixed with wide and narrow regions which are spaced by element isolating trenches. SOLUTION: This manufacturing method comprises the steps of etching a wiring layer 14, a gate insulation film 13 and a semiconductor substrate 11 to form element isolating trenches 15, depositing an insulation film 16 by biased ECR-CVD method, and etching back to retain this film 16 in the trenches 15 so as to make the wiring layer 14 thicker than the deposited insulation film 16. As a result, the surface of the insulation film 16 filling up the narrow-spaced trenches 15 can be made higher than that of the substrate 11 even after completely removing the insulation film 16 on the wiring layer 14 between the wide- spaced trenched 15 themselves.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an insulating film is buried in a groove of a semiconductor substrate to insulate and isolate elements from each other.

[0002]

2. Description of the Related Art As an element isolation method in a semiconductor device, insulation isolation using an oxide film formed by a selective oxidation (LOCOS) method has been widely used. However, since the selective oxidation method causes a large dimensional conversion difference due to bird's beak, it has become difficult to apply the selective oxidation method to the manufacture of a semiconductor device whose integration is advanced. For this reason, as a device isolation method with a small dimensional conversion difference, a method of forming a groove in a semiconductor substrate and insulatingly separating elements with an insulating film filling the groove has been considered.

In order to fill the groove with an insulating film, an insulating film is deposited on the semiconductor substrate on which the groove has been formed. However, if a narrow groove and a wide groove are mixed, the deposited insulating film is formed. However, these steps cannot be filled with an insulating film having a flat surface, and a complicated process such as chemical mechanical polishing is required. Therefore, a method has been considered in which a selective oxidation method is applied to an element isolation region having a large width and little hindrance due to a dimensional conversion difference, and a trench isolation method is applied only to an element isolation region having a small width.

In the semiconductor device manufactured by this method, the distance between the element isolation grooves in a region where the selective oxidation method is not applied is narrow, but the element isolation grooves on both sides of the element isolation region where the selective oxidation method is applied. Since the gaps between the trenches for isolation are wide, a region where the gap between the trenches for element isolation is narrow and a wide region are mixed.

FIG. 5 shows a NAND flash EEPROM using both the trench isolation method and the selective oxidation method.
1 shows a conventional example of a method for manufacturing M. In this conventional example, as shown in FIG. 5A, a region to be a wide element isolation region in the semiconductor substrate 11, for example, a region to be an element isolation region in a peripheral circuit portion is selectively oxidized. An oxide film 12 is formed. Then, a gate insulating film 13 is formed on a surface of the semiconductor substrate 11 in a region surrounded by the oxide film 12, for example, a region to be a memory cell portion.

Next, as shown in FIG. 5B, a wiring layer 14 for forming a floating gate is deposited on the oxide film 12 and the gate insulating film 13. Then, using a resist (not shown) of a groove pattern to be formed as a mask, FIG.
As shown in FIG. 1C, the wiring layer 14, the gate insulating film 13, and the semiconductor substrate 11 are continuously etched to form a groove 15 in the semiconductor substrate 11. In order to facilitate the embedding of the insulating film in the groove 15, the groove 15 is slightly tapered so that the side surface of the groove 15 is inclined.

Next, as shown in FIG.
An insulating film 16 thicker than the wiring layer 14 is deposited by a conformal CVD method such as a method, and the trench 15 is filled with the insulating film 16. Then, as shown in FIG. 5E, the entire surface of the insulating film 16 is etched back to remove the insulating film 16 on the wiring layer 14 and leave the insulating film 16 in the groove 15. Thereafter, substantially the same steps as those of the first embodiment of the present invention to be described later are executed to complete the flash EEPROM.

FIG. 6 shows a method considered to manufacture a NAND flash EEPROM by using both the trench isolation method and the selective oxidation method, which is different from the conventional example shown in FIG. Another method is shown. Even in this alternative method, as shown in FIGS. 6A to 6C, until the groove 15 is formed, substantially the same steps as those in the conventional example shown in FIG. 5 are executed.

In this alternative method, thereafter, as shown in FIG. 6D, an insulating film 16 thicker than the wiring layer 14 is deposited by a bias ECR-CVD method or the like, and the groove 15 is formed in the insulating film 16.
Fill with. Then, as shown in FIG.
The process after the etch back of the entire surface of FIG.
The steps substantially the same as those of the conventional example shown in FIG.

[0010]

By the way, low pressure CVD
In a conformal CVD method such as the CVD method, as shown in FIG. 5D, the insulating film 16 deposited on the wiring layer 14 between the grooves 15 having a small gap is also used for forming the insulating film 16 between the grooves 15 having a large gap. The thickness of the insulating film 16 deposited on the wiring layer 14 on the oxide film 12 formed by the selective oxidation method is substantially the same.

For this reason, the wiring layer 1
In order to completely remove the insulating film 16 thicker than 4, as shown in FIG. 5E, even if a certain degree of over-etching is performed at the time of etching back the insulating film 16, the insulating film 16 filling the groove 15 is not removed. The surface can be higher than the surface of the semiconductor substrate 11.

As a result, even if an insulating film or the like for capacitive coupling between the floating gate and the control gate is subsequently formed, the trench 15
Concentration of the electric field at the corner of the element formation region in contact with the opening can be suppressed. Therefore, in the conventional example shown in FIG. 5, a highly reliable semiconductor device can be manufactured.

However, in a conformal CVD method such as a low pressure CVD method, the insulating film 16 is deposited on the bottom face and the side face of the groove 15 at substantially the same speed.
5 is filled at substantially the same speed from both the bottom and side surfaces.
For this reason, a long void (not shown) in the direction perpendicular to the surface of the semiconductor substrate 11 is likely to be formed in a portion where the insulating films 16 deposited on the side surfaces of the groove 15 contact each other at the center of the groove 15.

When voids are formed in the insulating film 16, the insulating film 16 in the voids is easily removed by the subsequent etching, and the withstand voltage of the insulating film 16 is lowered. For this reason, in the conventional example shown in FIG.
6, it was difficult to fill the groove 15, and it was difficult to manufacture a semiconductor device having excellent characteristics.

On the other hand, in the bias ECR-CVD method, the deposition of the film and the etching of the deposited film proceed simultaneously. However, as shown in FIG. 4A, the deposition depends on the angle of the deposition surface with respect to the surface of the semiconductor substrate. Both the rate and the etching rate are different, and as a result, as shown in FIG. 4B, the actual deposition rate is also different depending on the angle.

That is, a film having a thickness as deposited remains on a surface parallel to the surface of the semiconductor substrate, whereas a film which is not parallel to the surface of the semiconductor substrate has a thickness smaller than that of the deposited film. Only a thin film remains. Therefore, in particular, in the tapered groove 15 as shown in FIG.
The insulating film 16 fills the groove 15 from the bottom faster than the side.

Therefore, the insulating film 1 deposited on the side surface of the groove 15
It is difficult for a state in which the 6 contact each other at the center of the groove 15, and a long void perpendicular to the surface of the semiconductor substrate 11 is hardly formed in the insulating film 16 in the groove 15. Therefore, according to the method shown in FIG. 6, the trench 15 can be filled with the insulating film 16 having excellent quality, and a semiconductor device having excellent characteristics can be manufactured.

However, C filling the groove 15 from the bottom surface
In the VD method, as shown in FIG.
While only the insulating film 16 thinner than the deposited thickness remains on the wiring layer 14 between
An insulating film 16 having a thickness as deposited remains on the wiring layer 14 on the oxide film 12 formed by selective oxidation between the five layers.

For this reason, as shown in FIG.
If the insulating film 16 is etched back only so that the surface of the insulating film 16 filling the layer 5 is higher than the surface of the semiconductor substrate 11, the insulating film 16 is thicker than the wiring layer 14 on the wiring layer 14 on the oxide film 12. The deposited insulating film 16 remains without being etched.

Conversely, when the insulating film 16 is etched back from the wiring layer 14 on the oxide film 12 until the insulating film 16 thicker than the wiring layer 14 is completely removed, the surface of the insulating film 16 filling the groove 15 is formed. Is lower than the surface of the semiconductor substrate 11. Therefore, it is difficult to manufacture a highly reliable semiconductor device by the method shown in FIG.

That is, in both the conventional example shown in FIG. 5 and the method shown in FIG. 6, the characteristics are excellent and the reliability is excellent even if a narrow area and a wide area are separated from each other. It is difficult to manufacture a semiconductor device having high reliability.
Therefore, the invention of the present application provides a method capable of manufacturing a semiconductor device having excellent characteristics and high reliability even in a case where a narrow region and a wide region of an element isolation groove are mixed. It is intended to be.

[0022]

In a method of manufacturing a semiconductor device according to the present invention, a wiring layer, a first insulating film, and a semiconductor substrate are etched into a pattern of a groove isolation region to form a semiconductor substrate with an element isolation element. Since the groove is formed, the groove for element isolation can be formed in a self-alignment manner with at least a part of the wiring.

Also, a second for filling the trench for element isolation is provided.
When the insulating film is deposited, the method of filling the groove from the bottom faster than from the side is adopted. Therefore, even if the groove has a high aspect ratio, the second insulating films deposited on the side of the groove are located at the center of the groove. A contact portion is not easily formed, and a void is not easily formed in the second insulating film in the groove, so that the element isolation groove can be filled with a high-quality insulating film.

On the other hand, in the method of filling the trench from the bottom surface faster than from the side surface, the second insulating film is relatively thinly deposited on the wiring layer between the closely spaced trenches. ,
A second insulating film is relatively thickly deposited on the wiring layer between the widely spaced trenches. For this reason, if a narrow region and a wide region of the isolation trench are mixed, the thickness of the second insulating film on the wiring layer becomes uneven.

However, since the groove is formed by etching the wiring layer and the semiconductor substrate in the same pattern, the depth of the groove is substantially deep by the thickness of the wiring layer, and the thickness for depositing the second insulating film. A wiring layer is formed thicker than that. For this reason,
There is a mixture of narrow and wide areas between the isolation trenches, and etch back until the relatively thick insulating film is completely removed from the wiring layer between the widely spaced grooves. However, the surface of the insulating film that fills the narrow gaps can be higher than the surface of the semiconductor substrate.

In the method of manufacturing a semiconductor device according to the second aspect, the second insulating film and the groove to be deposited by the method of filling the groove from the bottom faster than from the side are filled at the same speed from the bottom and the side. Since the trench for element isolation is filled with both the third insulating film deposited by the method and the entire surface of the groove only with the third insulating film deposited by the method of filling the groove from the bottom surface and the side surface at the same speed. As compared with the case where the trench is buried, voids are less likely to be formed in the second and third insulating films in the trench, and the trench for element isolation can be filled with a high quality insulating film.

In the method of filling the trenches at the same speed from the bottom surface and the side surfaces, the third insulating film deposited on the wiring layer between the closely spaced trenches also has a large gap between the widely spaced trenches. The third insulating films deposited on the wiring layer also have substantially the same thickness. For this reason, even if a narrow region and a wide region of the trench for element isolation are mixed, the thickness of the third insulating film on the wiring layer is nearly uniform, and the gap between the narrow trenches is small. The difference in the thickness of the insulating film between the wiring layer and the wiring layer between the widely-spaced grooves is caused only by the second insulating film.

In order to completely remove the insulating film from the wiring layer between the widely spaced trenches, the wiring layer is formed thicker than the second insulating film is deposited. The second insulating film may be thinner than the case where the groove is filled only with the film. Accordingly, the selectable range of the thickness of the wiring layer is wide, and the selectable range of the etch-back amount for completely removing the insulating film from above the wiring layer between the widely-spaced grooves is also wide. The surface of the insulating film filling the narrow groove can be easily made higher than the surface of the semiconductor substrate.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A NAND flash EEPROM using both a trench isolation method and a selective oxidation method will be described below.
The first and second embodiments of the invention of the present application applied to the manufacturing method will be described with reference to FIGS. 1 and 2
1 shows a first embodiment. In the first embodiment, as shown in FIG. 1A, an oxide film 12 is formed in a region of a semiconductor substrate 11 to be a wide element isolation region by a selective oxidation method. Enclosed semiconductor substrate 11
The gate insulating film 13 is formed on the surface of the substrate.

Next, as shown in FIG. 1B, a polycrystalline silicon layer as a wiring layer 14 for forming a floating gate is deposited on the oxide film 12 and the gate insulating film 13 by a CVD method. . The thickness of the wiring layer 14 depends on the thickness of the groove 15 to be formed later.
Is thicker than the insulating film 16 deposited to fill the gap.

Next, using a resist (not shown) of a groove pattern to be formed as a mask, as shown in FIG.
The wiring layer 14, the gate insulating film 13, and the semiconductor substrate 11 are continuously dry-etched to a depth of 300 to 500 nm.
A groove 15 having a width of about 250 nm is formed in the semiconductor substrate 11. In order to facilitate the embedding of the insulating film 16 in the groove 15, the groove 15 is slightly tapered and the side surface of the groove 15 is inclined.

Further, in order to remove a damaged portion formed on the inner surface of the groove 15 by dry etching, a thickness of 10 to 30
An oxide film (not shown) of about nm is formed on the inner surface of the groove 15 by thermal oxidation. However, in order to reduce the leak current at the source / drain junction formed later, it is preferable to form an oxide film as thick as possible on the inner surface of the groove 15.

Next, as shown in FIG.
An insulating film 16 is deposited by CR-CVD, and the groove 15 is filled with the insulating film 16. In the bias ECR-CVD method, as described above, only the insulating film 16 having a smaller thickness than the deposited thickness remains on the wiring layer 14 between the grooves 15 having a small gap, whereas An insulating film 16 of the thickness as deposited remains between the layers 15, that is, on the wiring layer 14 on the oxide film 12 formed by the selective oxidation method.

In the bias ECR-CVD method, as described above, the insulating film 16 fills the groove 15 from the bottom surface at a higher speed than the speed of filling from the side surface. The thickness of 16 does not necessarily depend on the width of groove 15.

However, since the insulating film 16 grows to some extent also from the side surface of the groove 15, the narrow groove 15 is filled with the insulating film 16 grown from the side surface. Therefore, a groove 15 having a depth of about 300 to 500 nm and a width of about 250 nm is used.
May be deposited by depositing an insulating film 16 having a thickness of about 300 to 400 nm.

Next, as shown in FIG.
Is etched back to form an insulating film 16 on the wiring layer 14.
And the insulating film 16 is left in the groove 15. As described above, since the wiring layer 14 is thicker than the insulating film 16, there is always an etchback amount satisfying the following relationship. Insulating film 16
Thickness <etchback amount <thickness of wiring layer 14

Therefore, in order to completely remove the insulating film 16 from the wiring layer 14, even if a certain degree of over-etching is performed at the time of etching back the insulating film 16, FIG.
As shown in (e), the surface of the insulating film 16 filling the groove 15 can be higher than the surface of the semiconductor substrate 11.

Next, as shown in FIG. 2, an insulating film 17 for capacitive coupling between the floating gate and the control gate is formed on the entire surface, and a connection hole 18 reaching the wiring layer 14 of the select transistor.
Is formed on the insulating film 17. Then, a silicide layer as a wiring layer 21 for forming a control gate is
The wiring layer 21, the insulating film 17, and the wiring layer 14 are successively etched using a resist (not shown) of a control gate pattern as a mask.

Thereafter, impurities are ion-implanted using the wiring layer 21, the insulating film 16, the oxide film 12 and the like as a mask, thereby forming the source / drain 22 on the semiconductor substrate 11. And
After forming an interlayer insulating film 23 covering the wiring layer 21 and the source / drain 22 and flattening the surface of the interlayer insulating film 23,
A connection hole 24 reaching one source / drain 22 of the select transistor is formed in the interlayer insulating film 23 and the gate insulating film 13.

Thereafter, the connection hole 24 is filled with a plug 25,
The bit line 26 connected to the plug 25 is formed of a metal wiring layer. Then, the bit line 26 and the like are covered with the passivation film 27 to complete the flash EEPROM 33 having the selection transistor 31 and the storage transistor 32.

In this flash EEPROM 33, since the wiring layer 14 is thick, as is clear from FIG.
The insulating film 17 is formed not only on the upper surface but also on the side surfaces of the wiring layer 14. For this reason, the insulating film 1 with respect to the sum of the coupling capacitance of the gate insulating film 13 and the coupling capacitance of the insulating film 17
7, the ratio of the coupling capacitance is high, and the write / erase characteristics are excellent.

FIG. 3 shows a second embodiment. Also in the second embodiment, as shown in FIGS. 3A to 3C, steps similar to those of the first embodiment shown in FIGS. . In the second embodiment, thereafter, as shown in FIG.
An insulating film 34 having a thickness of 200 to 300 nm is deposited by a CVD method, and the insulating film 34 is buried halfway of the groove 15. Note that the wiring layer 14 is formed thicker than the insulating film 34.

Next, as shown in FIG.
200-400 thickness by conformal CVD such as CVD
An insulating film 35 of nm is deposited. At this time, since the insulating film 34 has already buried a part of the groove 15, the remaining part of the groove 15 can be buried with the insulating film 35 while suppressing generation of voids even if the groove 15 is deep.

Next, as shown in FIG.
5 and 34 are etched back to remove the insulating films 35 and 34 on the wiring layer 14 and to form the insulating film 3 in the grooves 15.
Leave 5, 34. Since the wiring layer 14 is thicker than the insulating film 34 as described above, there is always an etchback amount that satisfies the following relationship.

The thickness of the insulating film 34 + the thickness of the insulating film 35 <the amount of etchback <the thickness of the wiring layer 14 + the thickness of the insulating film 35 When this relationship is modified, the following relationship is obtained. Thickness of insulating film 34 <etchback amount−thickness of insulating film 35 <wiring layer 14
Thickness

For this reason, the insulating film 35,
Even if a certain degree of over-etching is performed at the time of etching back the insulating films 35 and 34 to completely remove the insulating film 34, the insulating film 3 filling the groove 15 as shown in FIG.
The surfaces of 5 and 34 can be made higher than the surface of the semiconductor substrate 11.

Moreover, in the first embodiment shown in FIGS. 1 and 2, the entire groove 15 is filled with the insulating film 16, but in the second embodiment, the insulating film 34 is filled only halfway through the groove 15. The film 34 may be thinner than the insulating film 16. Therefore, from the above relationship, the selectable range of the thickness of the wiring layer 14 is wide, and the selectable range of the etchback amount is also wide. Thereafter, although not shown, substantially the same steps as those of FIG. 2 in the above-described first embodiment are executed to complete the flash EEPROM.

In the first and second embodiments, the present invention is applied to a method of manufacturing a NAND flash EEPROM using both the trench isolation method and the selective oxidation method. Even if the method is not used, a semiconductor device in which a narrow region and a wide region are mixed in an element forming region itself, so that a narrow region and a wide region of an interval between element isolation grooves are mixed. The invention of the present application can also be applied to the manufacturing method of (1).

Also, a NAND flash EEPROM is used.
Not only M but also NOR type flash EEPROM,
The invention of the present application can be applied to a nonvolatile semiconductor memory device other than the flash EEPROM and a method of manufacturing a semiconductor device other than the nonvolatile semiconductor memory device.

[0050]

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, a trench for element isolation can be formed in a self-alignment manner with at least a part of a wiring, thereby manufacturing a semiconductor device with a high degree of integration. can do. Further, since the trench for element isolation can be filled with a high quality insulating film, a semiconductor device having excellent characteristics can be manufactured.

In addition, a narrow region and a wide region of the isolation trench are mixed, and the relatively thick insulating film is completely removed from the wiring layer between the widely spaced trenches. Even when the etch back is performed, the surface of the insulating film that fills the narrow grooves can be made higher than the surface of the semiconductor substrate, so that the concentration of the electric field at the corners of the element formation region is suppressed, and high reliability is achieved. A semiconductor device can be manufactured.

In the method of manufacturing a semiconductor device according to the second aspect, since the trench for element isolation can be filled with an insulating film having excellent quality, a semiconductor device having excellent characteristics can be manufactured. Further, even if a narrow region and a wide region of the element isolation grooves are mixed, the surface of the insulating film filling the narrow grooves can be easily made higher than the surface of the semiconductor substrate. The concentration of the electric field at the corners of the element formation region is suppressed, and a highly reliable semiconductor device can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a side sectional view sequentially showing a first embodiment of the present invention.

FIGS. 2A and 2B show the semiconductor device manufactured in the first embodiment, wherein FIG. 2A is a side sectional view taken along a line AA in FIG. 2C, and FIG. 2B is a line BB in FIG. (C) is a plan view at a position along the line.

FIG. 3 is a side sectional view sequentially showing a second embodiment of the present invention.

FIG. 4 is a graph showing a deposition rate and an etching rate in a bias ECR-CVD method.

FIG. 5 is a side sectional view sequentially showing one conventional example of the invention of the present application.

FIG. 6 is a side sectional view sequentially showing another method different from one conventional example.

[Explanation of symbols]

11 semiconductor substrate (semiconductor substrate), 13 gate insulating film (first insulating film), 14 wiring layer, 15 groove, 16 insulating film (second insulating film), 33 flash EEPROM
(Semiconductor device), 34 ... insulating film (second insulating film), 35
... Insulating film (third insulating film)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 H01L 29/78 371 29/792 // H01L 21/316

Claims (2)

[Claims] A step of sequentially forming a first insulating film and a wiring layer on a semiconductor substrate; and etching the wiring layer, the first insulating film and the semiconductor substrate into a pattern of a trench isolation region. Forming a trench for element isolation in the semiconductor substrate by depositing a second insulating film in the trench and on the wiring layer by a method of filling the trench from the bottom faster than from the side surface, Filling the groove with the second insulating film; and etching back the second insulating film to remove the second insulating film on the wiring layer and to place the second insulating film in the groove. A method of manufacturing a semiconductor device, comprising: a step of leaving the wiring layer thicker than a thickness on which the second insulating film is deposited. 2. The method according to claim 1, further comprising: depositing the second insulating film in the groove and on the wiring layer by a method of filling the groove from the bottom surface faster than from the side surface, and forming the second insulating film halfway through the groove. Filling a third insulating film on the second insulating film by a method of filling the groove from the bottom and side surfaces at the same speed, and resting the groove with the third insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: filling the wiring layer so as to be thicker than a thickness on which the second insulating film is deposited.