CN108092730B - A kind of sequential control method suitable for more equipment - Google Patents
A kind of sequential control method suitable for more equipment Download PDFInfo
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- CN108092730B CN108092730B CN201711439304.8A CN201711439304A CN108092730B CN 108092730 B CN108092730 B CN 108092730B CN 201711439304 A CN201711439304 A CN 201711439304A CN 108092730 B CN108092730 B CN 108092730B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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Abstract
The present invention provides a kind of sequential control method suitable for more equipment, this method is based on host computer, timing control unit and external equipment, and the timing control unit includes network module, single-chip microcontroller, FPGA and external interface；The purpose of the present invention is to provide a kind of methods of simple, easy-operating independent sequence logic control, for realizing the accurate control of the operations such as the switching on and shutting down to distinct device, and has fixed point caching, the quickly functions such as accurate switching, realize the transmission modes such as network UDP unicast, UDP multicast transmission.
Description
Technical field
The present invention relates to a kind of methods of the operations such as timing controlled, switching on and shutting down between distinct device accurately controlled.It is suitable
For plurality of devices, node or specific timing node complete corresponding operation in different times.
Background technique
With the fast development of intelligent control, intelligent control technology has arrived more and more applications.Especially some
In the case that plurality of devices controls operation simultaneously, the timing that need to just control between distinct device is completed in strict accordance with timing node
Other control operations such as switching on and shutting down between distinct device.Traditional equipment, which seldom has, realizes position control and control time point
The functions such as caching, cumbersome, complicated, technology transplant is more difficult.
Summary of the invention
The purpose of the present invention is to provide a kind of methods of simple, easy-operating independent sequence logic control, for realizing
The accurate control of the operations such as the switching on and shutting down to distinct device, and have fixed point caching, quickly the functions such as accurate switching, are realized
The transmission modes such as network UDP unicast, UDP multicast transmission.
The object of the present invention is achieved like this:
Sequence controller main control unit completes the core design function of sequence controller by the way of single-chip microcontroller+FPGA combination
Can, wherein single-chip microcontroller undertakes operation flow and data protocol parsing, conversion, FPGA are responsible for extension and the letter of peripheral data interface
The control of number timing.
Sequence controller, which is connect by transmission modes such as network UDP unicast, UDP multicasts with host computer, completes control information
Obtain, work information reports task, the work such as hardware interface conversion and the conversion of communication protocol of data information can be completed, and
Have the characteristics that the operation moment such as time maintenance, facility switching machine caching and timing controlled.This method is based on host computer, and (application is soft
Part), timing control unit and external equipment, the timing control unit includes network module, single-chip microcontroller, FPGA and to external
Mouthful；The following steps are included:
(1) host computer is sent by network connection to the network module of timing control unit synchronous with outer welding system and accurate
To the fiducial time of second；
(2) single-chip microcontroller of timing control unit reads the fiducial time in network module and makes a decision parsing, after parsing
Time maintenance module of the fiducial time setting to FPGA, the 1pps triggering update that time maintenance module is provided by outer welding system
Local zone time, and send local zone time to the time cache module of FPGA；
(3) operational motion of host computer sending device and it is accurate to net of the actuation time to timing control unit of Millisecond
Network module；
(4) single-chip microcontroller of timing control unit reads the operational motion in network module and actuation time and makes a decision solution
The actuation time of extraction, is set the time cache module of FPGA by analysis；
(5) local zone time of time maintenance module input and the actuation time of caching are compared in time cache module,
Interrupting information is generated after two temporal informations are completely the same is sent to single-chip microcontroller；
(6) after single-chip microcontroller detects interrupting information, according to operational motion framing, frame letter is sent by the serial port module of FPGA
It ceases to relevant external equipment；Wherein, the corresponding external equipment of a serial port module；
(7) serial port module of FPGA obtains the work information that corresponding external equipment reports, and is sent to single-chip microcontroller, monolithic
Machine parsing work information content and the state for judging equipment will be transmitted to after work information content again framing by network connection
Host computer.
Wherein, step (2) the following steps are included:
(201) time maintenance module and a time cache module are designed in the FPGA of timing control unit；
(202) single-chip microcontroller of timing control unit reads the data cached in network module, and the host computer that will acquire is set
The fiducial time parsing set simultaneously is arranged after correct judgment into the time maintenance module of FPGA；
(203) time maintenance module of FPGA divides to obtain the clock of 1000pps by the clock of local 10MHz, according to
Fiducial time generates local millisecond clock；
(204) 1pps that the time maintenance module of FPGA is provided by outer welding system resets local millisecond clock, comes
Local zone time is updated, and sends local zone time to the time cache module of FPGA.
Wherein, step (7) the following steps are included:
(701) the receipts module of each serial port module receives the information of corresponding external equipment respectively and is stored in data buffer storage
In space；If data buffer storage has data information in space, externally exports high level data flag bit and otherwise externally export low
Level data flag bit；
(702) single-chip microcontroller reads the Data Labels position of current serial port module inside FPGA module；
(703) single-chip microcontroller judges whether the Data Labels position of current serial port module is high level, if so, being transferred to (704)
Otherwise, serial port module is transferred to (702) as current serial port module all the way by under；
(704) single-chip microcontroller reads the number cached in the data buffer storage space of current serial port module according to the length of data information
It is believed that breath；
(705) single-chip microcontroller judges whether the verification of data information is correct, if it is, executing (706)；It otherwise, will be next
Road serial port module is transferred to (702) as current serial port module；
(706) work information of extract equipment after single-chip microcontroller parses the data of reading；And the work information of equipment is pressed
According to network module is sent to after frame format recombination, the work information after framing again is transferred to host computer by network module；
(707) serial port module is transferred to (702) as current serial port module all the way by under, in per serial port module all the way
Reading data complete.
The present invention having the beneficial effect that compared with prior art
(1) sequence controller that the present invention designs is built using the transmission modes such as network UDP unicast, UDP multicast and host computer
Vertical correspondence can be good at completing the data interaction with upper computer software, can greatly improve data management policies and be
System stability.
(2) the timing control unit external connection relationship that the present invention designs is simple, operation convenient for safeguarding.
(3) timing control unit that the present invention designs can be realized local zone time maintenance, timing controlled and time caching.
Time-controlled accuracy can reach Millisecond, accurately and rapidly complete very much switching, help to improve system performance index and steady
It is qualitative.
Detailed description of the invention
Fig. 1 is general frame figure of the invention.
Fig. 2 is time maintenance flow chart of the invention.
Fig. 3 is timing controlled workflow of the invention.
Fig. 4 is business information transmission flow of the invention.
Specific embodiment
The present invention will be further described with attached drawing combined with specific embodiments below:
Fig. 1 is the timing unit general frame figure that the present invention designs.
1. the design core is using host computer (application software), timing control unit and external equipment；Timing control unit
Including network module, single-chip microcontroller, FPGA and external interface；FPGA includes time maintenance module, time cache module and serial ports mould
Block；
2. single-chip microcontroller: mainly completing data frame analyzing, treatment process；
3.FPGA:FPGA is responsible for the extension of peripheral data interface and the control of signal sequence.
4. network module: using W5100 chip, connect with AVR single chip by SPI interface, interrupt data receiver；
The module mainly completes equipment and host computer application software udp data transmission mode.
5. external interface: the serial ports provided with the external RS422 level of multichannel, all the way external 1pps signal input interface.
External interface carries out information exchange for timing control unit and external equipment；
Fig. 2 is the local zone time maintenance process figure that the present invention designs:
Time maintenance module counts on the basis of receiving the fiducial time of host computer setting according to millisecond and outer welding system
Synchronous 1pps updates local time information, realizes the maintenance of local time information.
Fig. 3 is the work flow diagram that the present invention designs:
(1) host computer is sent by network connection to the network module of timing control unit synchronous with outer welding system and accurate
To the fiducial time of second；Command content is stored in local cache module by network module, and generates interrupt signal to main control unit
Single-chip microcontroller；
(2) single-chip microcontroller of timing control unit, which receives, reads fiducial time in network module after interrupt signal according to frame
Agreement calculates verification, makes a decision parsing after verification is correct, and the time maintenance module to FPGA is arranged in the fiducial time after parsing,
The 1pps triggering that time maintenance module is provided by outer welding system updates local zone time, and by local zone time be sent to FPGA when
Between cache module；
(3) operational motion of host computer sending device and it is accurate to net of the actuation time to timing control unit of Millisecond
Network module；
(4) single-chip microcontroller of timing control unit reads the operational motion in network module and actuation time and makes a decision solution
The actuation time of extraction, is set the time cache module of FPGA by analysis；
(5) local zone time of time maintenance module input and the actuation time of caching are compared in time cache module,
Interrupting information is generated after two temporal informations are completely the same is sent to single-chip microcontroller；
(6) after single-chip microcontroller detects interrupting information, according to operational motion framing, pass through the hair module of the serial port module of FPGA
Frame information is sent to relevant external equipment；Wherein, the corresponding external equipment of a serial port module；
(7) the receipts module of the serial port module of FPGA obtains the work information that corresponding external equipment reports, and is sent to list
Piece machine, single-chip microcontroller parsing work information content and the state for judging equipment, will pass through network after work information content again framing
Connection is transmitted to host computer.
Wherein, step (2) the following steps are included:
(201) time maintenance module and a time cache module are designed in the FPGA of timing control unit；
(202) single-chip microcontroller of timing control unit reads the data cached in network module, and the host computer that will acquire is set
The fiducial time parsing set simultaneously is arranged after correct judgment into the time maintenance module of FPGA；
(203) time maintenance module of FPGA divides to obtain the clock of 1000pps by the clock of local 10MHz, according to
Fiducial time generates local millisecond clock；
(204) 1pps that the time maintenance module of FPGA is provided by outer welding system resets local millisecond clock, comes
Local zone time is updated, and sends local zone time to the time cache module of FPGA.
Wherein, step (7) the following steps are included:
(701) the receipts module of each serial port module receives the information of corresponding external equipment respectively and is stored in data buffer storage
In space；If data buffer storage has data information in space, externally exports high level data flag bit and otherwise externally export low
Level data flag bit；
(702) single-chip microcontroller reads the Data Labels position of current serial port module inside FPGA module；
(703) single-chip microcontroller judges whether the Data Labels position of current serial port module is high level, if so, being transferred to (704)
Otherwise, serial port module is transferred to (702) as current serial port module all the way by under；
(704) single-chip microcontroller reads the data information received and cached in module data spatial cache according to the length of data information；
(705) single-chip microcontroller judges whether the verification of data information is correct, if it is, executing (706)；It otherwise, will be next
Road serial port module is transferred to (702) as current serial port module；
(706) work information of extract equipment after single-chip microcontroller parses the data of reading；And the work information of equipment is pressed
According to network module is sent to after frame format recombination, the work information after framing again is transferred to host computer by network module；
(707) serial port module is transferred to (702) as current serial port module all the way by under, in per serial port module all the way
Reading data complete.
Fig. 4 is the business process map that the present invention designs:
Host computer controls external equipment according to user demand, and sequence controller receives process instruction, and according to timing requirements
Control external equipment；External equipment is per second to report primary equipment state to sequence controller；Sequence controller analyzes the instruction content
And it is sent to upper computer software after reassembled frame content, so that user is real-time monitored the working condition of external equipment.
Claims (3)
1. a kind of sequential control method suitable for more equipment, this method is based on host computer, timing control unit and external equipment,
The timing control unit includes network module, single-chip microcontroller, FPGA and external interface；Characterized by comprising the following steps:
(1) host computer sends synchronous with outer welding system and is accurate to the second by network connection to the network module of timing control unit
Fiducial time；
(2) single-chip microcontroller of timing control unit reads the fiducial time in network module and makes a decision parsing, by the base after parsing
The time maintenance module of FPGA is arrived in setting between punctual, and the 1pps triggering that time maintenance module is provided by outer welding system updates local
Time, and send local zone time to the time cache module of FPGA；
(3) operational motion of host computer sending device and it is accurate to network mould of the actuation time to timing control unit of Millisecond
Block；
(4) single-chip microcontroller of timing control unit reads the operational motion in network module and actuation time and makes a decision parsing, general
The actuation time of extraction sets the time cache module of FPGA；
(5) time cache module compares the actuation time of local zone time and caching that time maintenance module inputs, at two
Between information it is completely the same after generate interrupting information be sent to single-chip microcontroller；
(6) after single-chip microcontroller detects interrupting information, according to operational motion framing, by the serial port module of FPGA send frame information to
Relevant external equipment；Wherein, the corresponding external equipment of a serial port module；
(7) serial port module of FPGA obtains the work information that corresponding external equipment reports, and is sent to single-chip microcontroller, single-chip microcontroller solution
Analysis work information content and the state for judging equipment, it is upper by being transmitted to after work information content again framing by network connection
Machine.
2. a kind of sequential control method suitable for more equipment according to claim 1, which is characterized in that (2) step includes
Following steps:
(201) time maintenance module and a time cache module are designed in the FPGA of timing control unit；
(202) single-chip microcontroller of timing control unit reads the data cached in network module, the host computer setting that will acquire
It is arranged after fiducial time parsing and correct judgment into the time maintenance module of FPGA；
(203) time maintenance module of FPGA divides to obtain the clock of 1000pps by the clock of local 10MHz, according to benchmark
Time generates local millisecond clock；
(204) 1pps that the time maintenance module of FPGA is provided by outer welding system resets local millisecond clock, Lai Gengxin
Local zone time, and send local zone time to the time cache module of FPGA.
3. a kind of sequential control method suitable for more equipment according to claim 1, which is characterized in that step (7) packet
Include following steps:
(701) the receipts module of each serial port module receives the information of corresponding external equipment respectively and is stored in data buffer storage space
It is interior；If data buffer storage has data information in space, externally exports high level data flag bit and otherwise externally export low level
Data Labels position；
(702) single-chip microcontroller reads the Data Labels position of current serial port module inside FPGA；
(703) single-chip microcontroller judges whether the Data Labels position of current serial port module is high level, if so, it is transferred to (704) otherwise,
Serial port module is transferred to (702) as current serial port module all the way by under；
(704) single-chip microcontroller reads the data letter cached in the data buffer storage space of current serial port module according to the length of data information
Breath；
(705) single-chip microcontroller judges whether the verification of data information is correct, if it is, executing (706)；Otherwise, it is gone here and there all the way by under
Mouth mold block is transferred to (702) as current serial port module；
(706) work information of extract equipment after single-chip microcontroller parses the data of reading；And by the work information of equipment according to frame
It is sent to network module after format recombination, the work information after framing again is transferred to host computer by network module；
(707) serial port module is transferred to (702) as current serial port module all the way by under, until per the number in serial port module all the way
It is completed according to reading.
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| CN201711439304.8A CN108092730B (en) | 2017-12-27 | 2017-12-27 | A kind of sequential control method suitable for more equipment |
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|---|---|---|---|
| CN201711439304.8A CN108092730B (en) | 2017-12-27 | 2017-12-27 | A kind of sequential control method suitable for more equipment |
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| CN102075318B (en) * | 2010-12-28 | 2013-07-17 | 重庆邮电大学 | FPGA-based multi-channel data packet monitoring and timestamp capture system and method |
| CN102868515B (en) * | 2012-09-27 | 2015-04-29 | 烽火通信科技股份有限公司 | System time synchronization device and method in packet transport network |
| CN106773635A (en) * | 2016-12-27 | 2017-05-31 | 天津七六四通信导航技术有限公司 | A kind of time service precision detecting system and implementation method |
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