CN108092730A - A kind of sequential control method suitable for more equipment - Google Patents
A kind of sequential control method suitable for more equipment Download PDFInfo
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- CN108092730A CN108092730A CN201711439304.8A CN201711439304A CN108092730A CN 108092730 A CN108092730 A CN 108092730A CN 201711439304 A CN201711439304 A CN 201711439304A CN 108092730 A CN108092730 A CN 108092730A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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Abstract
The present invention provides a kind of sequential control method suitable for more equipment, this method is based on host computer, timing control unit and external equipment, and the timing control unit includes network module, microcontroller, FPGA and external interface；It is an object of the invention to provide a kind of methods of simple, easy-operating independent sequence logic control, for realizing the accurate control of the operations such as the switching on and shutting down to distinct device, and possesses fixed point caching, the functions such as quick accurate switching, realize the transmission modes such as network UDP unicasts, UDP multicast transmissions.
Description
Technical field
The present invention relates to a kind of methods accurately controlled of the operations such as timing controlled, the switching on and shutting down between distinct device.It is suitable
For plurality of devices, node or specific timing node complete corresponding operation in different times.
Background technology
With the fast development of intelligent control, intelligent control technology has arrived more and more applications.Especially at some
Plurality of devices in the case of control operation, need to just control the sequential between distinct device to be completed in strict accordance with timing node simultaneously
Other control operations such as switching on and shutting down between distinct device.Traditional equipment, which seldom possesses, realizes position control and control time point
The functions such as caching, cumbersome, complicated, technology transplant is more difficult.
The content of the invention
It is an object of the invention to provide a kind of method of simple, easy-operating independent sequence logic control, for realizing
The accurate control of the operations such as the switching on and shutting down to distinct device, and possess fixed point caching, the functions such as quick accurate switching are realized
The transmission modes such as network UDP unicasts, UDP multicast transmissions.
The object of the present invention is achieved like this：
Time schedule controller main control unit completes the core design work(of time schedule controller by the way of microcontroller+FPGA combinations
Can, wherein microcontroller undertakes operation flow and data protocol parsing, conversion, FPGA are responsible for extension and the letter of peripheral data interface
The control of number sequential.
Time schedule controller is connected by transmission modes such as network UDP unicasts, UDP multicasts with host computer completes control information
Obtain, work information reports task, the work such as hardware interface conversion and the conversion of communication protocol of data message can be completed, and
There is the operation moment such as time maintenance, facility switching machine caching and timing controlled.This method is based on host computer, and (application is soft
Part), timing control unit and external equipment, the timing control unit includes network module, microcontroller, FPGA and to external
Mouthful；Comprise the following steps：
(1) host computer is sent and external system synchronization and accurate by network connection to the network module of timing control unit
To the fiducial time of second；
(2) microcontroller of timing control unit reads the fiducial time in network module and makes a decision parsing, after parsing
Fiducial time time maintenance module to FPGA is set, the 1pps that time maintenance module is provided by outer welding system triggers update
Local zone time, and local zone time is sent to the time cache module of FPGA；
(3) operational motion of host computer sending device and it is accurate to net of the actuation time to timing control unit of Millisecond
Network module；
(4) microcontroller of timing control unit reads the operational motion in network module and actuation time and makes a decision solution
The actuation time of extraction is put the time cache module of FPGA by analysis；
(5) local zone time of time maintenance module input is compared with the actuation time cached in time cache module,
Interrupting information is generated after two temporal informations are completely the same and is sent to microcontroller；
(6) after microcontroller detects interrupting information, according to operational motion framing, frame is sent by the serial port module of FPGA and is believed
It ceases to relevant external equipment；Wherein, a serial port module corresponds to an external equipment；
(7) serial port module of FPGA obtains the work information that corresponding external equipment reports, and is sent to microcontroller, monolithic
Machine parses work information content and judges the state of equipment, will be transmitted to after work information content again framing by network connection
Host computer.
Wherein, (2) step comprises the following steps：
(201) time maintenance module and a time cache module are designed in the FPGA of timing control unit；
(202) microcontroller of timing control unit reads the data cached in network module, and the host computer got is set
The fiducial time parsing put simultaneously is set after correct judgment into the time maintenance module of FPGA；
(203) time maintenance module of FPGA divides to obtain the clock of 1000pps by the clock of local 10MHz, according to
Fiducial time generates local millisecond clock；
(204) time maintenance module of FPGA resets local millisecond clock by the 1pps that outer welding system provides, and comes
Local zone time is updated, and local zone time is sent to the time cache module of FPGA.
Wherein, step (7) comprises the following steps：
(701) the receipts module of each serial port module receives the information of corresponding external equipment and is stored in data buffer storage respectively
In space；If data buffer storage has data message in space, high level data flag bit is externally exported, otherwise, is externally exported low
Level data flag bit；
(702) microcontroller reads the Data Labels position of current serial port module inside FPGA module；
(703) microcontroller judges whether the Data Labels position of current serial port module is high level, if so, being transferred to (704)
Otherwise, serial port module as current serial port module, is transferred to (702) all the way by under；
(704) microcontroller reads the number cached in the data buffer storage space of current serial port module according to the length of data message
It is believed that breath；
(705) microcontroller judges whether the verification of data message is correct, if it is, performing (706)；It otherwise, will be next
Road serial port module is transferred to (702) as current serial port module；
(706) work information of extraction equipment after microcontroller parses the data of reading；And the work information of equipment is pressed
Network module is sent to after being recombinated according to frame format, the work information after framing again is transferred to host computer by network module；
(707) serial port module as current serial port module, is transferred to (702), in per serial port module all the way all the way by under
Digital independent complete.
The present invention having the beneficial effect that compared with prior art：
(1) time schedule controller that the present invention designs is built using the transmission modes such as network UDP unicasts, UDP multicasts and host computer
Vertical correspondence can be good at completing the data interaction with upper computer software, can greatly improve data management policies and be
System stability.
(2) the timing control unit external connection relation that the present invention designs is simple, convenient for attended operation.
(3) timing control unit that the present invention designs can realize that local zone time is safeguarded, timing controlled and time cache.
Time-controlled accuracy can reach Millisecond, accurately and rapidly complete very much switching, help to improve system performance index and steady
It is qualitative.
Description of the drawings
Fig. 1 is the general frame figure of the present invention.
Fig. 2 is the time maintenance flow chart of the present invention.
Fig. 3 is the timing controlled workflow of the present invention.
Fig. 4 is the business information transfer process of the present invention.
Specific embodiment
With reference to specific embodiments and the drawings, the present invention will be further described：
Fig. 1 is the timing unit general frame figure that the present invention designs.
1. the design core uses host computer (application software), timing control unit and external equipment；Timing control unit
Including network module, microcontroller, FPGA and external interface；FPGA includes time maintenance module, time cache module and serial ports mould
Block；
2. microcontroller：It is main to complete data frame analyzing, processing procedure；
3.FPGA：FPGA is responsible for the extension of peripheral data interface and the control of signal sequence.
4. network module：Using W5100 chips, it is connected with AVR single chip by SPI interface, interrupt data receiver；
The module mainly completes equipment and host computer application software udp data transmission mode.
5. external interface：There is provided the serial ports of the external RS422 level of multichannel, external 1pps signal input interfaces all the way.
External interface carries out information exchange for timing control unit and external equipment；
Fig. 2 is the local zone time maintenance process figure that the present invention designs:
Time maintenance module is counted on the basis of the fiducial time of host computer setting is received according to millisecond and outer welding system
Synchronous 1pps updates local time information, realizes the maintenance of local time information.
Fig. 3 is the work flow diagram that the present invention designs:
(1) host computer is sent and external system synchronization and accurate by network connection to the network module of timing control unit
To the fiducial time of second；Command content is stored in local cache module by network module, and generates interrupt signal to main control unit
Microcontroller；
(2) microcontroller of timing control unit, which receives, reads fiducial time in network module after interrupt signal according to frame
Agreement calculates verification, and parsing is made a decision after verification is correct, and the fiducial time after parsing is set the time maintenance module to FPGA,
The 1pps triggering update local zone times that time maintenance module is provided by outer welding system, and by local zone time be sent to FPGA when
Between cache module；
(3) operational motion of host computer sending device and it is accurate to net of the actuation time to timing control unit of Millisecond
Network module；
(4) microcontroller of timing control unit reads the operational motion in network module and actuation time and makes a decision solution
The actuation time of extraction is put the time cache module of FPGA by analysis；
(5) local zone time of time maintenance module input is compared with the actuation time cached in time cache module,
Interrupting information is generated after two temporal informations are completely the same and is sent to microcontroller；
(6) after microcontroller detects interrupting information, according to operational motion framing, the hair module of the serial port module of FPGA is passed through
Frame information is sent to relevant external equipment；Wherein, a serial port module corresponds to an external equipment；
(7) the receipts module of the serial port module of FPGA obtains the work information that corresponding external equipment reports, and is sent to list
Piece machine, microcontroller parsing work information content simultaneously judge the state of equipment, will pass through network after work information content again framing
Connection is transmitted to host computer.
Wherein, (2) step comprises the following steps：
(201) time maintenance module and a time cache module are designed in the FPGA of timing control unit；
(202) microcontroller of timing control unit reads the data cached in network module, and the host computer got is set
The fiducial time parsing put simultaneously is set after correct judgment into the time maintenance module of FPGA；
(203) time maintenance module of FPGA divides to obtain the clock of 1000pps by the clock of local 10MHz, according to
Fiducial time generates local millisecond clock；
(204) time maintenance module of FPGA resets local millisecond clock by the 1pps that outer welding system provides, and comes
Local zone time is updated, and local zone time is sent to the time cache module of FPGA.
Wherein, step (7) comprises the following steps：
(701) the receipts module of each serial port module receives the information of corresponding external equipment and is stored in data buffer storage respectively
In space；If data buffer storage has data message in space, high level data flag bit is externally exported, otherwise, is externally exported low
Level data flag bit；
(702) microcontroller reads the Data Labels position of current serial port module inside FPGA module；
(703) microcontroller judges whether the Data Labels position of current serial port module is high level, if so, being transferred to (704)
Otherwise, serial port module as current serial port module, is transferred to (702) all the way by under；
(704) microcontroller reads the data message received and cached in module data spatial cache according to the length of data message；
(705) microcontroller judges whether the verification of data message is correct, if it is, performing (706)；It otherwise, will be next
Road serial port module is transferred to (702) as current serial port module；
(706) work information of extraction equipment after microcontroller parses the data of reading；And the work information of equipment is pressed
Network module is sent to after being recombinated according to frame format, the work information after framing again is transferred to host computer by network module；
(707) serial port module as current serial port module, is transferred to (702), in per serial port module all the way all the way by under
Digital independent complete.
Fig. 4 is the business process map that the present invention designs:
Host computer controls external equipment according to user demand, and time schedule controller receives process instruction, and according to timing requirements
Control external equipment；External equipment is per second to report primary equipment state to time schedule controller；Time schedule controller analysis instruction content
And upper computer software is sent to after reassembled frame content, user is made to real-time monitor the working condition of external equipment.
Claims (3)
1. a kind of sequential control method suitable for more equipment, this method is based on host computer, timing control unit and external equipment,
The timing control unit includes network module, microcontroller, FPGA and external interface；It is characterised in that it includes following steps：
(1) host computer to the network module transmission of timing control unit and external system synchronization and is accurate to the second by network connection
Fiducial time；
(2) microcontroller of timing control unit reads the fiducial time in network module and makes a decision parsing, by the base after parsing
Time maintenance module to FPGA is set between punctual, and the 1pps triggering updates that time maintenance module is provided by outer welding system are local
Time, and local zone time is sent to the time cache module of FPGA；
(3) operational motion of host computer sending device and it is accurate to network mould of the actuation time to timing control unit of Millisecond
Block；
(4) microcontroller of timing control unit reads the operational motion in network module and actuation time and makes a decision parsing, general
The actuation time of extraction puts the time cache module of FPGA；
(5) time cache module compares the actuation time of the local zone time that time maintenance module inputs and caching, at two
Between information it is completely the same after generate interrupting information be sent to microcontroller；
(6) after microcontroller detects interrupting information, according to operational motion framing, by the serial port module of FPGA send frame information to
Relevant external equipment；Wherein, a serial port module corresponds to an external equipment；
(7) serial port module of FPGA obtains the work information that corresponding external equipment reports, and is sent to microcontroller, microcontroller solution
Analysis work information content simultaneously judges the state of equipment, upper by being transmitted to after work information content again framing by network connection
Machine.
2. a kind of sequential control method suitable for more equipment according to claim 1, which is characterized in that (2) step includes
Following steps：
(201) time maintenance module and a time cache module are designed in the FPGA of timing control unit；
(202) microcontroller of timing control unit reads the data cached in network module, and the host computer got is set
It is set after fiducial time parsing and correct judgment into the time maintenance module of FPGA；
(203) time maintenance module of FPGA divides to obtain the clock of 1000pps by the clock of local 10MHz, according to benchmark
Time generates local millisecond clock；
(204) time maintenance module of FPGA resets local millisecond clock by the 1pps that outer welding system provides, to update
Local zone time, and local zone time is sent to the time cache module of FPGA.
3. a kind of sequential control method suitable for more equipment according to claim 1, which is characterized in that step (7) is wrapped
Include following steps：
(701) the receipts module of each serial port module receives the information of corresponding external equipment and is stored in data buffer storage space respectively
It is interior；If data buffer storage has data message in space, high level data flag bit is externally exported, otherwise, externally exports low level
Data Labels position；
(702) microcontroller reads the Data Labels position of current serial port module inside FPGA；
(703) microcontroller judges whether the Data Labels position of current serial port module is high level, if so, it is transferred to (704) otherwise,
Serial port module as current serial port module, is transferred to (702) all the way by under；
(704) microcontroller reads the data cached in the data buffer storage space of current serial port module according to the length of data message and believes
Breath；
(705) microcontroller judges whether the verification of data message is correct, if it is, performing (706)；Otherwise, gone here and there all the way by under
Mouth mold block is transferred to (702) as current serial port module；
(706) work information of extraction equipment after microcontroller parses the data of reading；And by the work information of equipment according to frame
Network module is sent to after form restructuring, the work information after framing again is transferred to host computer by network module；
(707) serial port module as current serial port module, is transferred to (702), until per the number in serial port module all the way all the way by under
It is completed according to reading.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711439304.8A CN108092730B (en) | 2017-12-27 | 2017-12-27 | A kind of sequential control method suitable for more equipment |
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|---|---|---|---|
| CN201711439304.8A CN108092730B (en) | 2017-12-27 | 2017-12-27 | A kind of sequential control method suitable for more equipment |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075318A (en) * | 2010-12-28 | 2011-05-25 | 重庆邮电大学 | FPGA-based multi-channel data packet monitoring and timestamp capture system and method |
| CN102428451A (en) * | 2009-04-08 | 2012-04-25 | 谷歌公司 | Command and interrupt grouping for a data storage device |
| CN102868515A (en) * | 2012-09-27 | 2013-01-09 | 烽火通信科技股份有限公司 | System time synchronization device and method in packet transport network |
| CN106773635A (en) * | 2016-12-27 | 2017-05-31 | 天津七六四通信导航技术有限公司 | A kind of time service precision detecting system and implementation method |
-
2017
- 2017-12-27 CN CN201711439304.8A patent/CN108092730B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102428451A (en) * | 2009-04-08 | 2012-04-25 | 谷歌公司 | Command and interrupt grouping for a data storage device |
| CN102075318A (en) * | 2010-12-28 | 2011-05-25 | 重庆邮电大学 | FPGA-based multi-channel data packet monitoring and timestamp capture system and method |
| CN102868515A (en) * | 2012-09-27 | 2013-01-09 | 烽火通信科技股份有限公司 | System time synchronization device and method in packet transport network |
| CN106773635A (en) * | 2016-12-27 | 2017-05-31 | 天津七六四通信导航技术有限公司 | A kind of time service precision detecting system and implementation method |
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