CN108091701A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN108091701A CN108091701A CN201711061804.2A CN201711061804A CN108091701A CN 108091701 A CN108091701 A CN 108091701A CN 201711061804 A CN201711061804 A CN 201711061804A CN 108091701 A CN108091701 A CN 108091701A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 376
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 61
- 229920005591 polysilicon Polymers 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 9
- 238000011084 recovery Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 9
- 239000012535 impurity Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 239000000969 carrier Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 230000002035 prolonged effect Effects 0.000 description 5
- 239000000203 mixture Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- Power Engineering (AREA)
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Abstract
The invention discloses semiconductor devices and its manufacturing method, wherein the semiconductor devices includes：The first semiconductor region has the first conduction type；At least one second semiconductor regions, it is arranged in the first semiconductor region, and the surface of second semiconductor regions is flushed with the surface of the first semiconductor region, and second semiconductor regions have second conduction type opposite with first conduction type；Wherein, at least one sunk area is formed in the surface of second semiconductor regions, the sunk area is the semi-conducting material with first conduction type.The semiconductor devices that the embodiment of the present invention is provided can shorten the length in lateral resistance area while surface temperature is reduced, so as to reduce the size of semiconductor devices.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
Semiconductor devices, particularly power semiconductor devices, need to have the capability to handle high voltages, large currents. Fig. 1A and fig. 1B respectively illustrate a vertical cross-sectional view of a conventional semiconductor device under forward bias and reverse bias, in which 100 is an N-type substrate, 200 is a P-type doped region, 300 is a first electrode, 400 is an insulating layer, and 500 is a second electrode. In the lateral position, the portion of the first electrode 300 in contact with the P-type doped region 200 is referred to as an active region; the edge of the first electrode 300 contacting the P-type doped region 200 to the side edge of the P-type doped region 200 is referred to as a lateral resistance region, which may be equivalent to a resistance R; the portion outside the active region and the lateral resistance region is called a termination region.
As shown in fig. 1A, when a positive voltage is applied to the first electrode 300 and a negative voltage is applied to the second electrode 500 (i.e., when the positive electrode is turned on), the majority holes in the P-type doped region 200 flow to the N-type doped region 100 through the edge of the P-type doped region 200, and excess holes (i.e., excess carriers) are formed in the N-type doped region 100. Due to the higher doping concentration and the lower resistance of the surface of the P-type doped region 200, holes at the side edge of the P-type doped region 200 (the side edge is shown by the thick line in fig. 1A and 1B, and the dashed arrow indicates the path of the holes) will gather at the surface and flow into the N-type doped region 100 (also referred to as lateral hole injection).
As shown in fig. 1B, when the first electrode 300 is applied with a negative voltage and the second electrode 500 is applied with a positive voltage (i.e. during reverse recovery), the excess holes in the N-type doped region 100 flow into the P-type doped region 200 and are further extracted by the first electrode 300. Also, due to the higher doping concentration and the lower resistance of the surface of the P-type doped region 200, holes near the side edge of the P-type doped region 200 will accumulate on the surface and flow into the P-type doped region 200. Because the voltage difference of the electrodes is higher during reverse recovery, the carrier aggregation effect is more prominent during reverse recovery, so that the surface temperature of the P-type doped region 200 is higher than that of other regions; and the more excess carriers are instantaneously extracted, the higher the temperature.
When conducting forward, if the length of the lateral resistance region is short, even zero (i.e. there is no lateral resistance region), then the voltage drop from the first electrode 300 to the side edge is small due to the high surface doping concentration and the small resistance of the P-type doped region 100, so that the PN junction bias voltage is large, and more holes will flow into the N-type doped region 100 through the side edge; the longer transverse resistance region can increase the voltage drop from the first electrode 300 to the side edge, reduce the bias voltage of the PN junction at the side edge, and reduce the number of holes instantaneously flowing into the N-type doped region 100 through the side edge, thereby reducing the lateral injection of carriers.
In the reverse recovery, the lateral resistance region corresponds to a hole current flowing from the right end to the left end of the resistor R shown in fig. 1B, so that the voltage at the right end is higher than that at the left end, i.e. the lateral resistance region forms a self-bias effect, specifically, since the first electrode 300 is a negative voltage and the second electrode 500 is a positive voltage, the voltage difference between the side edge and the second electrode 500 is smaller than that between the first electrode 300 and the second electrode 500. Thus, the provision of the lateral resistance region enables the reverse bias of the PN junction at the low side edge to be reduced and the electric field strength at the low side edge to be reduced, so that the number of holes instantaneously extracted in the reverse direction is reduced, thereby reducing the temperature of the surface during reverse recovery. The longer the length of the lateral resistive region, the stronger the self-biasing effect, the smaller the number of holes instantaneously extracted in reverse, and the lower the temperature of the surface during reverse recovery.
Therefore, in order to solve the temperature of the surface of the P-type doped region 200, the lateral length of the lateral resistive region is usually made longer in the prior art, so as to reduce the number of holes instantly flowing into the N-type doped region 100 through the side edge, reduce the number of holes instantly extracted in reverse direction, and reduce the electric field strength of the PN junction at the side edge. However, the longer the length of the lateral resistance region, the larger the size of the semiconductor device as a whole. For example, with existing high voltage diodes for 3.3kV, the width of the lateral resistive region reaches hundreds or even hundreds of microns.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, so as to solve the problem that the conventional semiconductor device has a large size for reducing the surface temperature of the device.
A first aspect of the present invention provides a semiconductor device comprising: a first semiconductor region having a first conductivity type; at least one second semiconductor region disposed on the first semiconductor region and having a surface flush with a surface of the first semiconductor region, the second semiconductor region having a second conductivity type opposite the first conductivity type; wherein,
at least one recessed region is formed in the surface of the second semiconductor region, the recessed region being of semiconductor material having the first conductivity type.
Optionally, the semiconductor device further comprises: a first electrode provided on the surface of the second semiconductor region, the first electrode being in contact with the second semiconductor region on a side of the recessed region remote from where the second semiconductor region is in contact with the first semiconductor region; and a second electrode disposed on the other surface of the first semiconductor region.
Optionally, the first electrode is not in contact with a surface of the recessed region.
Optionally, the semiconductor device further comprises: a first insulating layer disposed on the surfaces of the first and second semiconductor regions; a doped polysilicon layer disposed on the first insulating layer; and the second insulating layer is arranged on the doped polycrystalline silicon layer, an opening is formed in the second insulating layer, and the first electrode is in contact with the doped polycrystalline silicon layer above the second semiconductor region through the opening.
Optionally, the semiconductor device further comprises: at least one third semiconductor region disposed on the first semiconductor region and having a surface that is flush with the surface of the first semiconductor region, the third semiconductor region having a second conductivity type.
Optionally, a contact electrode disposed on the second insulating layer, the contact electrode contacting the third semiconductor region through an opening passing through the first insulating layer, the doped polysilicon layer and the second insulating layer.
Optionally, the semiconductor device further comprises: at least one fourth semiconductor region disposed on the first semiconductor region and having a surface flush with the surface of the first semiconductor region, the fourth semiconductor region having the first conductivity type, and the doped polysilicon layer contacting the fourth semiconductor region through an opening in the first insulating layer.
Optionally, the semiconductor device is a power semiconductor device.
A second aspect of the present invention provides a method of manufacturing a semiconductor device, including: providing a first semiconductor region having a first conductivity type; forming at least one second semiconductor region on the first semiconductor region, a surface of the second semiconductor region being flush with a surface of the first semiconductor region, and the second semiconductor region having a second conductivity type opposite to the first conductivity type; forming at least one recessed region in the surface of the second semiconductor region, the recessed region being of semiconductor material of the first conductivity type.
Optionally, the method further comprises: providing a first electrode on the surface of the second semiconductor region, the first electrode contacting the second semiconductor region on a side of the recessed region remote from where the second semiconductor region contacts the first semiconductor region; a second electrode is disposed on the other surface of the first semiconductor region.
Optionally, the step of providing a first electrode on the surface of the second semiconductor region comprises: forming an insulating layer on the surfaces of the first and second semiconductor regions; forming an opening on the insulating layer, wherein the opening does not expose the surface of the recessed region; the first electrode is disposed at the opening.
Optionally, before the step of disposing the first electrode on the surface of the second semiconductor region, the method further includes: forming a first insulating layer on the surfaces of the first and second semiconductor regions; forming a doped polysilicon layer on the first insulating layer; forming a second insulating layer on the doped polysilicon layer; forming an opening on the second insulating layer above the second semiconductor region, the first electrode being in contact with the doped polysilicon layer through the opening.
Optionally, the method further comprises: forming at least one third semiconductor region on the first semiconductor region, a surface of the third semiconductor region being flush with the surface of the first semiconductor region, the third semiconductor region having a second conductivity type.
Optionally, the method further comprises: forming an opening through the second insulating layer, the doped polysilicon layer and the first insulating layer above the third semiconductor region; forming a contact electrode on the second insulating layer, the contact electrode contacting the third semiconductor region through an opening passing through the first insulating layer, the doped polysilicon layer, and the second insulating layer.
Optionally, the method further comprises: forming at least one fourth semiconductor region on the first semiconductor region, a surface of the fourth semiconductor region being flush with the surface of the first semiconductor region, the fourth semiconductor region having a first conductivity type; forming an opening on the first insulating layer above the fourth semiconductor region, the doped polysilicon layer contacting the fourth semiconductor region through the opening on the first insulating layer.
The semiconductor device and the manufacturing method thereof provided by the embodiment of the invention are characterized in that the second semiconductor region with the second conductivity type is arranged on the first semiconductor region with the first conductivity type, and the concave region with the first conductivity type is arranged in the second semiconductor region, so that when PN junctions of the first semiconductor region and the second semiconductor region are positively biased, multi-photon holes gathered on the surface in the second semiconductor region can bypass the edge of the concave region and flow into the first semiconductor region to form surplus holes (namely surplus carriers), the path of the holes is prolonged in the transverse resistance region with the same length, the voltage drop of the transverse resistance region is increased, the bias voltage of the PN junctions is reduced, and the number of the holes instantly rushing into the first semiconductor region through the side edge of the second semiconductor region is reduced; when the PN junction of the first semiconductor region and the second semiconductor region is subjected to higher reverse bias, the excess holes in the first semiconductor region are gathered on the surface and flow into the second semiconductor region, and when the excess holes are further extracted by the electrode, the edges of the concave regions are also bypassed in the second semiconductor region, so that the paths of the holes are prolonged in the transverse resistance regions with the same length, the self-bias effect of the transverse resistance regions is enhanced, the number of the holes which are instantaneously extracted reversely through the side edges is reduced, the electric field intensity at the positions and the corresponding hole concentration effect are reduced, and the temperature of the surface in the reverse recovery (namely when the PN junction is subjected to reverse bias) process is reduced. It can be seen that the semiconductor device described above can reduce the surface temperature while shortening the length of the lateral resistance region, thereby reducing the size of the semiconductor device.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:
FIG. 1A shows a schematic longitudinal cross-sectional view of a prior art diode under forward bias;
FIG. 1B shows a schematic longitudinal cross-sectional view of a prior art diode under reverse bias;
FIG. 2 illustrates a schematic longitudinal cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention;
FIG. 3A illustrates a schematic longitudinal cross-sectional view of yet another semiconductor device in accordance with an embodiment of the present invention;
FIG. 3B illustrates a schematic longitudinal cross-sectional view of yet another semiconductor device in accordance with an embodiment of the present invention;
FIG. 4A illustrates a schematic longitudinal cross-sectional view of yet another semiconductor device in accordance with an embodiment of the present invention;
FIG. 4B illustrates a schematic longitudinal cross-sectional view of yet another semiconductor device in accordance with an embodiment of the present invention;
FIG. 5 shows a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the invention;
FIGS. 6A-6F are schematic diagrams illustrating steps in a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 7 shows a flow chart of another method of manufacturing a semiconductor device according to the present invention;
fig. 8A to 8F are schematic diagrams showing respective steps in the method of manufacturing a semiconductor device according to the embodiment of the present invention.
Detailed Description
In order to make the objects, advantages and preparation methods of the present invention clearer, the following detailed description of embodiments of the present invention will be made with reference to the accompanying drawings, wherein some structures in the drawings directly show preferred structural materials, and obviously, the described embodiments are some, but not all embodiments of the present invention. It is to be noted that the embodiments described with reference to the drawings are exemplary, and the structural materials shown in the embodiments are also exemplary and are intended to illustrate the present invention, but not to be construed as limiting the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the first conductivity type in the present application may be N-type, and the second conductivity type is P-type; or the first conductivity type is P-type, and the second conductivity type is N-type.
Example one
Fig. 2 shows a schematic longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present invention, as shown in fig. 2, the semiconductor device comprises a first semiconductor region 1, at least one second semiconductor region 2 and at least one recess region 6, wherein the first semiconductor region 1 has a first conductivity type, the second semiconductor region 2 has a second conductivity type opposite to the first conductivity type, a surface of the second semiconductor region 2 is flush with a surface of the first semiconductor region 1, the surface of the second semiconductor region 2 has at least one recess region 6 formed therein, and the recess region 6 is a semiconductor material having the first conductivity type. Although only one recessed area 6 is shown in fig. 2, it will be understood by those skilled in the art that more recessed areas 6 are possible. The semiconductor device of the embodiment of the invention is particularly suitable for power semiconductor devices such as diodes. Hereinafter, embodiments of the present invention will be described in detail by taking the first semiconductor type as an N-type and the second semiconductor type as a P-type as examples.
As shown in fig. 2, when a voltage is applied between the first semiconductor region 1 and the second semiconductor region 2, for example, when a forward bias is applied, holes in the second semiconductor region 2 flow into the first semiconductor region 1 through the edge of the second semiconductor region 2, and excess holes (i.e., excess carriers) are formed in the first semiconductor region 1. Since the holes in the second semiconductor region 2 concentrate on the surface and flow to the first semiconductor region 1, the holes need to bypass the edge of the recess region 6, so that the path of the holes is extended in the lateral resistance region of the same length, the voltage drop of the lateral resistance region is increased, the PN junction bias is reduced, and the number of holes flowing into the first semiconductor region 1 through the lateral edge of the second semiconductor region 2 (the lateral edge is the position shown by the thick line in fig. 2, and the dashed line shows the hole path) is reduced.
On the other hand, the lateral resistance region shown in fig. 1A corresponds to R, and the lateral resistance region shown in fig. 2 corresponds to R1+ R2+ R3, where R1 corresponds to the resistance of the left edge of the recess region 6, R2 corresponds to the resistance of the bottom edge of the recess region 6, and R3 corresponds to the resistance of the right edge of the recess region 6. Due to the deeper depth of the recess region 6, when the surface doping concentration of the second semiconductor region 2 is higher, the resistance R2 is larger than the resistance R (the higher the doping concentration, the smaller the resistance), the presence of the resistances R1, R3 further increases the resistance of the lateral resistance region, so that the PN junction bias is further reduced, and the number of holes momentarily rushing into the first semiconductor region 1 through the side edges of the second semiconductor region 2 is further reduced.
When a high reverse bias is applied between the first semiconductor region 1 and the second semiconductor region 2, excess holes of the first semiconductor region flow into the second semiconductor region 2. When holes near the side edge of the second semiconductor region 2 are gathered on the surface and flow into the second semiconductor region 2, the edges of the concave regions 6 also need to be bypassed, so that the paths of the holes are prolonged in the lateral resistance regions with the same length, the self-bias effect of the lateral resistance regions is enhanced, the electric field intensity at the positions and the corresponding hole concentration effect are reduced, the number of the holes which are instantaneously and reversely extracted through the side edge is reduced, and the temperature of the surface during the reverse recovery (namely, when the PN junction is reversely biased) is reduced.
It should be added that the recess region 6 may be located completely within the lateral resistance region (as shown in fig. 2).
In the semiconductor device, the second semiconductor region with the second conductivity type is arranged on the first semiconductor region with the first conductivity type, and the concave region with the first conductivity type is arranged in the second semiconductor region, so that when PN junctions of the first semiconductor region and the second semiconductor region are forward biased, multi-electron holes gathered on the surface in the second semiconductor region bypass the edge of the concave region and flow into the first semiconductor region to form surplus holes (namely surplus carriers), the path of the holes is prolonged in the transverse resistance region with the same length, the voltage drop of the transverse resistance region is increased, the PN junction bias voltage is reduced, and the number of holes instantly rushing into the first semiconductor region through the side edge of the second semiconductor region is reduced; when the PN junction of the first semiconductor region and the second semiconductor region is subjected to higher reverse bias, the excess holes in the first semiconductor region are gathered on the surface and flow into the second semiconductor region, and when the excess holes are further extracted by the electrode, the edges of the concave regions are also bypassed in the second semiconductor region, so that the paths of the holes are prolonged in the transverse resistance regions with the same length, the self-bias effect of the transverse resistance regions is enhanced, the electric field intensity at the positions and the corresponding hole concentration effect are reduced, the number of the holes which are instantaneously extracted in a reverse direction through the side edges is reduced, and the temperature of the surface in the process of reverse recovery (namely, when the PN junction is subjected to reverse bias) is reduced. It can be seen that the semiconductor device can reduce the surface temperature and shorten the length of the lateral resistance region (simulation results show that the width of the lateral resistance region can be reduced to 50-70% of the existing width, such as 55%, 60%, 65%, 70%), thereby reducing the size of the semiconductor device. For example, in a 3.3kV fast recovery diode, the width of the lateral resistance region in the prior art is as high as 120 μm or more, but the lateral resistance region of the semiconductor device provided by the embodiment of the present invention only needs 30 μm, so that the additional area of the semiconductor device can be reduced, the area of the active region can be increased, and the utilization rate of the semiconductor device can be improved.
The semiconductor device in this embodiment may further include a first electrode 3 and a second electrode 5. As shown in fig. 2, the first electrode 3 is disposed on the surface of the second semiconductor region 2, and the first electrode 3 is in contact with the second semiconductor region 2 on the side of the recess region 6 away from the side of the second semiconductor region 2 in contact with the first semiconductor region 1, that is, the recess region 6 is located between the first electrode 3 and the side edge of the second semiconductor region 2 (the side edge is the position indicated by the thick line in the figure). The first electrode 3 is not in contact with the surface of the recess region 6. In fig. 2, the second electrode 5 is provided on the other surface of the first semiconductor region 1, but the present invention is not limited thereto, and in practice, the second electrode 5 may be provided on the surface of the first semiconductor region 1 on the same side as the first electrode 3; alternatively, as shown in fig. 2, it may be provided on a surface (i.e., a lower surface) opposite to the above-mentioned "surface" (upper surface in the drawing); or may be provided on a side surface, which is not limited herein.
Alternatively, in FIG. 2, the width of the recess region 6 is 35-55 μm, the depth is 2-6 μm, and the doping concentration is 1.2e 18. The distance between the right edge of the recess region 6 and the right edge of the second semiconductor region 2 is 10-25 μm, and the distance between the left edge of the recess region 6 and the first electrode 3 is 30-40 μm. The first semiconductor region 1 has a width of 100-120 μm, a depth of 10-15 μm, and a surface doping concentration of 1e17-5e 17. The substrate 1 has an internal doping concentration of 1.5e13-5e13 and a thickness of 200-250 μm.
As an optional implementation of this embodiment, the semiconductor device further includes a first insulating layer 41, a doped polysilicon layer 8, and a second insulating layer 42.
A first insulating layer 41 is provided on the surfaces of the first and second semiconductor regions 1 and 2. A doped polysilicon layer 8 is disposed on the first insulating layer 41. A second insulating layer 42 is provided on the doped polysilicon layer 8, the second insulating layer 42 having an opening provided therein, the first electrode 3 being in contact with the doped polysilicon layer 8 over the second semiconductor region 2 through the opening.
As shown in fig. 3A, in the lateral resistance region above the second semiconductor region 2, a first insulating layer 41, a doped polysilicon layer 8, and a second insulating layer 42 are sequentially provided, and an opening is provided on the second insulating layer. The first electrode 3 extends to cover the second insulating layer 42 over the lateral resistive region and contacts the doped polysilicon layer 8 through an opening in the second insulating layer. The doped polysilicon 8 of the lateral resistive region is provided separately, i.e. not in contact with other parts of the doped polysilicon layer.
The doped polysilicon can be used as a field plate to improve the voltage which can be endured by the semiconductor device.
Example two
The difference from the first embodiment is that the semiconductor device in this embodiment further comprises at least one third semiconductor region 7. As shown in fig. 3A, the third semiconductor region 7 is disposed on the first semiconductor region 1, and the surface of the third semiconductor region 7 is flush with the surface of the first semiconductor region 1, the third semiconductor region 7 having the second conductivity type, i.e., P-type. Above the third semiconductor region 7, a first insulating layer 41, a doped polysilicon layer 8 and a second insulating layer 42 are sequentially disposed.
The third semiconductor region 7 can be used as a field limiting ring to improve the withstand voltage of the semiconductor device. The doped polysilicon layer above the third semiconductor region is independently arranged (i.e. is not in contact with other parts of the doped polysilicon layer) and is used as a floating field plate, so that the withstand voltage of the semiconductor device can be further improved. Simulation results show that the width of the lateral resistance region of the semiconductor device with the floating field plate in the present embodiment can be reduced to 50-70% of the prior art, for example, 55%, 60%, 65%, 70%, and the withstand voltage can reach about 3.3kV, under the condition that the same lateral resistance value (i.e., the resistance value of the lateral resistance region) as the prior art is obtained.
Further, the semiconductor device may further include a contact electrode 13. As shown in fig. 3B, the contact electrode 13 is disposed on the second insulating layer 42, and the contact electrode 13 is in contact with the third semiconductor region 7 through an opening that penetrates the first insulating layer 41, the doped polysilicon layer 8, and the second insulating layer 42. The contact electrode 13 electrically connects the third semiconductor region 7 with the doped polysilicon layer 8 above the third semiconductor region to form a contact field plate, which can further improve the withstand voltage of the semiconductor device in the reverse recovery process. For example, simulation results show that the withstand voltage of the semiconductor device with the contact field plate can reach about 4.5 kV.
EXAMPLE III
The difference from the first and second embodiments is that the semiconductor device in this embodiment further comprises at least one fourth semiconductor region 9. As shown in fig. 4A and 4B, the fourth semiconductor region 9 is disposed on the first semiconductor region 1, and a surface of the fourth semiconductor region 9 is flush with a surface of the first semiconductor region 1, the fourth semiconductor region 9 having the first conductivity type, i.e., N-type. A first insulating layer 41, a doped polysilicon layer 8 and a second insulating layer 42 are sequentially disposed above the fourth semiconductor region 9, and the doped polysilicon layer 8 is in contact with the fourth semiconductor region 9 through an opening on the first insulating layer 41.
The fourth semiconductor region may act as a stop ring and the separately provided doped polysilicon 8 in contact with the stop ring (i.e. not in contact with other parts of the doped polysilicon layer) may act as a field plate.
It should be noted that in the first, second, and third embodiments, most of the first semiconductor region 1 is the lightly doped region 11, and the portion in contact with the second electrode 5 is the heavily doped region 12, so as to form a good ohmic contact with the second electrode 5. The second semiconductor region 2 may be heavily doped; or, it is heavily doped only where it contacts the first electrode 3, thereby forming a good ohmic contact with the first electrode 3. The third semiconductor region 7 may be heavily doped; alternatively, when the contact electrode 13 is provided, it is heavily doped only at a place in contact with the contact electrode 13, thereby forming a good ohmic contact with the contact electrode 13.
Example four
Fig. 5 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, which can be used to manufacture the semiconductor device described in the first embodiment or the second embodiment, or any alternative implementation manner thereof. As shown in fig. 5, the method includes the steps of:
s101: a first semiconductor region having a first conductivity type is provided.
S102: at least one second semiconductor region is formed on the first semiconductor region, a surface of the second semiconductor region being flush with a surface of the first semiconductor region, and the second semiconductor region having a second conductivity type opposite to the first conductivity type.
As shown in fig. 6A, 1 is a first semiconductor region of N-type, and 2 is a second semiconductor region 2. The second semiconductor region 2 may be formed by implanting impurity ions into the flat surface of the first semiconductor region 1 by a process such as ion implantation or thermal diffusion, thereby forming the second semiconductor region 2.
S103: at least one recessed region is formed in a surface of the second semiconductor region, the recessed region being of a semiconductor material of the first conductivity type.
As shown in fig. 6B, 6 is a recessed region. The method of forming the recess region 6 may be to implant impurity ions into the flat surface of the second semiconductor region 2 by a process such as ion implantation or thermal diffusion, thereby forming the recess region 6.
S104: a first electrode is provided on a surface of the second semiconductor region, the first electrode contacting the second semiconductor region on a side of the recessed region away from the second semiconductor region where the first semiconductor region contacts.
As shown in fig. 6C, the side edges of the first electrode 3 and the second semiconductor region 2 are located on both sides of the recess region 6, respectively.
Step S104 may be to first form an insulating layer 4 on the surfaces of the first semiconductor region 1 and the second semiconductor region 2, as shown in fig. 6D; then, an opening is formed in the insulating layer 4, and the opening does not expose the surface of the recess region 6, as shown in fig. 6E; finally, the first electrode 3 is disposed at the opening, as shown in fig. 6F.
S105: a second electrode is provided on the other surface of the first semiconductor region.
For example, the second electrode 5 may be provided on the other surface opposite to the surface of the first semiconductor 1, or the second electrode 5 may be provided on the side surface, which is not limited in the present application.
In the method for manufacturing a semiconductor device, the second semiconductor region having the second conductivity type is formed on the first semiconductor region having the first conductivity type, and the recess region having the first conductivity type is formed in the second semiconductor region, so that the surface temperature can be reduced and the length of the lateral resistance region can be shortened, thereby reducing the size of the semiconductor device.
EXAMPLE five
Fig. 7 is a flow chart showing a method for manufacturing a semiconductor device according to another embodiment of the present invention, which can be used to manufacture the semiconductor device described in any of the first to third embodiments or any alternative embodiment thereof. As shown in fig. 7, the method includes the steps of:
s201: a first semiconductor region having a first conductivity type is provided.
S202: at least one second semiconductor region and at least one third semiconductor region are formed on the first semiconductor region. The surface of the second semiconductor region is flush with the surface of the first semiconductor region, and the second semiconductor region has a second conductivity type opposite to the first conductivity type. The surface of the third semiconductor region is flush with the surface of the first semiconductor region, the third semiconductor region having the second conductivity type. The second semiconductor region and the third semiconductor region may be formed simultaneously or separately, and preferably are formed simultaneously.
As shown in fig. 8A, the first semiconductor region may include a lightly doped region 11 and a heavily doped region 12. The heavily doped region 12 may be formed by doping impurity ions to a surface on which the second electrode is disposed on the N-type lightly doped semiconductor through ion implantation, thermal diffusion, or the like. The step of forming the heavily doped region 12 is only required to precede the step of "disposing the second electrode 5".
As shown in fig. 8A, 2 is the second semiconductor region, 7 is the third semiconductor region, and the third semiconductor region is of P-type conductivity. The second semiconductor region 2 and the third semiconductor region 7 may be formed by implanting impurity ions into the flat surface of the first semiconductor region 1 by ion implantation or thermal diffusion.
S203: at least one recessed region and at least one fourth semiconductor region are formed in the surface of the second semiconductor region, the recessed region being of a semiconductor material of the first conductivity type. A surface of the fourth semiconductor region is flush with a surface of the first semiconductor region, the fourth semiconductor region having the first conductivity type. The fourth semiconductor region and the recess region may be formed simultaneously or separately, and preferably are formed simultaneously.
As shown in fig. 8B, 6 is a recess region, and 9 is a fourth semiconductor region. The fourth semiconductor region is N-type conductive. The method of forming the recess region 6 and the fourth semiconductor region 9 may be to implant impurity ions into the flat surface of the first semiconductor region 1 by a process such as ion implantation or thermal diffusion.
S204: a first insulating layer is formed on surfaces of the first and second semiconductor regions, and a first opening is formed on the first insulating layer over the fourth semiconductor region.
As shown in fig. 8C, 41 is a first insulating layer.
It should be noted that, as an alternative to steps S202 to S204, an opening may be formed in the first insulating layer, the opening serves as an ion implantation window, ions are implanted into the first semiconductor region through the window by using an ion implantation method to form a recess region, a third semiconductor region, or a fourth semiconductor region, and a thinner insulating layer may be formed at the bottom of the opening before the doped polysilicon layer is formed, that is, the first insulating layer shown in fig. 8C is formed. If the recess region, the third semiconductor region and the fourth semiconductor region are formed first, and then the first insulating layer 41 is formed, the surface of the first insulating layer may be flush.
S205: a doped polysilicon layer is formed on the first insulating layer.
As shown in fig. 8C, 8 is a doped polysilicon layer. Since the first insulating layer 41 above the fourth semiconductor region 9 is formed with a first opening, the doped polysilicon layer 8 is in contact with the fourth semiconductor region through the first opening on the first insulating layer. The doped polysilicon layer has a first conductivity type.
S206: and forming openings on the doped polycrystalline silicon layer, so that the doped polycrystalline silicon layer above the second semiconductor region, the doped polycrystalline silicon layer above the third semiconductor region and the doped polycrystalline silicon layer above the fourth semiconductor region are disconnected in pairs, and the doped polycrystalline silicon layers above the adjacent third semiconductor regions are disconnected in pairs.
It should be added that the fourth semiconductor region 9 may be formed simultaneously with the recess region 6; or may be formed simultaneously with the doped polysilicon layer. Specifically, the doped polysilicon layer 8 is formed first, and then semiconductor impurities (e.g., phosphorus ions) having the first conductivity type are implanted into the surface of the doped polysilicon layer. Since the first insulating layer is provided with an opening, the doped polysilicon at this opening is in contact with the first semiconductor region 1, so that semiconductor impurities can be implanted into the first semiconductor region 1 through the doped polysilicon there to form a fourth semiconductor region.
S207: a second insulating layer is formed on the doped polysilicon layer.
As shown in fig. 8C, 42 is a second insulating layer.
S208: a second opening is formed in the second insulating layer over the second semiconductor region.
S209: and forming a third opening on the first insulating layer, the doped polycrystalline silicon layer and the second insulating layer, wherein the surface of the recessed region is not exposed by the third opening.
This step is followed as shown in fig. 8D.
S210: a first electrode is disposed on a surface of the second semiconductor region, the first electrode being in contact with the doped polysilicon layer through the second opening.
As shown in fig. 8E, the first electrode 3 extends onto the second insulating layer and contacts the doped polysilicon layer through the second opening in the second insulating layer 42. The first electrode 3 is in contact with the second semiconductor region 2 at a side of the recessed region 6 remote from where the second semiconductor region 2 is in contact with the first semiconductor region 1. That is, the side edges of the first electrode 3 and the second semiconductor region 2 are located at two sides of the recess region 6, respectively.
S211: a second electrode is provided on the other surface of the first semiconductor region.
Please refer to step S205 of the fifth embodiment.
Through the above steps, a passivation layer is formed on the surfaces of the second insulating layer 42 and the first electrode 3, so that the semiconductor device shown in fig. 4A can be formed.
As an alternative implementation of this embodiment, after step S210, the semiconductor device shown in fig. 4B may also be formed by the following steps.
S212: and forming an opening penetrating through the second insulating layer, the doped polycrystalline silicon layer and the first insulating layer above the third semiconductor region.
S213: a contact electrode is formed on the second insulating layer, and the contact electrode contacts the third semiconductor region through an opening penetrating the first insulating layer, the doped polysilicon layer, and the second insulating layer.
As shown in fig. 8F, 13 is a contact electrode. And 43 is a passivation layer.
Although the present invention has been described in detail with respect to the exemplary embodiments and the advantages thereof, those skilled in the art will appreciate that various changes, substitutions and alterations can be made to the embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while maintaining the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (15)
1. A semiconductor device, comprising:
a first semiconductor region having a first conductivity type;
at least one second semiconductor region disposed on the first semiconductor region and having a surface flush with a surface of the first semiconductor region, the second semiconductor region having a second conductivity type opposite the first conductivity type; wherein,
at least one recessed region is formed in the surface of the second semiconductor region, the recessed region being of semiconductor material having the first conductivity type.
2. The semiconductor device according to claim 1, further comprising:
a first electrode provided on the surface of the second semiconductor region, the first electrode being in contact with the second semiconductor region on a side of the recessed region remote from where the second semiconductor region is in contact with the first semiconductor region;
and a second electrode disposed on the other surface of the first semiconductor region.
3. The semiconductor device according to claim 2, wherein the first electrode is not in contact with a surface of the recess region.
4. The semiconductor device according to claim 2, further comprising:
a first insulating layer disposed on the surfaces of the first and second semiconductor regions;
a doped polysilicon layer disposed on the first insulating layer;
and the second insulating layer is arranged on the doped polycrystalline silicon layer, an opening is formed in the second insulating layer, and the first electrode is in contact with the doped polycrystalline silicon layer above the second semiconductor region through the opening.
5. The semiconductor device according to claim 4, further comprising:
at least one third semiconductor region disposed on the first semiconductor region and having a surface that is flush with the surface of the first semiconductor region, the third semiconductor region having a second conductivity type.
6. The semiconductor device according to claim 5, further comprising:
a contact electrode disposed on the second insulating layer, the contact electrode contacting the third semiconductor region through an opening passing through the first insulating layer, the doped polysilicon layer, and the second insulating layer.
7. The semiconductor device according to claim 4, further comprising:
at least one fourth semiconductor region disposed on the first semiconductor region and having a surface flush with the surface of the first semiconductor region, the fourth semiconductor region having the first conductivity type, and the doped polysilicon layer contacting the fourth semiconductor region through an opening in the first insulating layer.
8. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is a power semiconductor device.
9. A method of manufacturing a semiconductor device, comprising:
providing a first semiconductor region having a first conductivity type;
forming at least one second semiconductor region on the first semiconductor region, a surface of the second semiconductor region being flush with a surface of the first semiconductor region, and the second semiconductor region having a second conductivity type opposite to the first conductivity type;
forming at least one recessed region in the surface of the second semiconductor region, the recessed region being of semiconductor material of the first conductivity type.
10. The method for manufacturing a semiconductor device according to claim 9, further comprising:
providing a first electrode on the surface of the second semiconductor region, the first electrode contacting the second semiconductor region on a side of the recessed region remote from where the second semiconductor region contacts the first semiconductor region;
a second electrode is disposed on the other surface of the first semiconductor region.
11. The method according to claim 10, wherein the step of providing a first electrode over the surface of the second semiconductor region comprises:
forming an insulating layer on the surfaces of the first and second semiconductor regions;
forming an opening on the insulating layer, wherein the opening does not expose the surface of the recessed region;
the first electrode is disposed at the opening.
12. The method according to claim 11, wherein before the step of providing the first electrode on the surface of the second semiconductor region, further comprising:
forming a first insulating layer on the surfaces of the first and second semiconductor regions;
forming a doped polysilicon layer on the first insulating layer;
forming a second insulating layer on the doped polysilicon layer;
forming an opening on the second insulating layer above the second semiconductor region, the first electrode being in contact with the doped polysilicon layer through the opening.
13. The method for manufacturing a semiconductor device according to claim 12, further comprising:
forming at least one third semiconductor region on the first semiconductor region, a surface of the third semiconductor region being flush with the surface of the first semiconductor region, the third semiconductor region having a second conductivity type.
14. The method for manufacturing a semiconductor device according to claim 13, further comprising:
forming an opening through the second insulating layer, the doped polysilicon layer and the first insulating layer above the third semiconductor region;
forming a contact electrode on the second insulating layer, the contact electrode contacting the third semiconductor region through an opening passing through the first insulating layer, the doped polysilicon layer, and the second insulating layer.
15. The method for manufacturing a semiconductor device according to claim 12, further comprising:
forming at least one fourth semiconductor region on the first semiconductor region, a surface of the fourth semiconductor region being flush with the surface of the first semiconductor region, the fourth semiconductor region having a first conductivity type;
forming an opening on the first insulating layer above the fourth semiconductor region, the doped polysilicon layer contacting the fourth semiconductor region through the opening on the first insulating layer.
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|---|---|---|---|---|
| CN118431301A (en) * | 2024-03-29 | 2024-08-02 | 海信家电集团股份有限公司 | Diode module and method for manufacturing diode module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150859A (en) * | 1998-11-18 | 2000-05-30 | Meidensha Corp | Diode |
| US20130214394A1 (en) * | 2012-02-22 | 2013-08-22 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
| CN105304696A (en) * | 2015-10-29 | 2016-02-03 | 深圳深爱半导体股份有限公司 | Variation of lateral doping (VLD) junction termination structure for semiconductor devices and manufacturing method thereof |
| CN106252420A (en) * | 2016-07-27 | 2016-12-21 | 电子科技大学 | Three ends carry vertical-type constant current device and the manufacture method thereof of safeguard function |
-
2017
- 2017-11-02 CN CN201711061804.2A patent/CN108091701A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150859A (en) * | 1998-11-18 | 2000-05-30 | Meidensha Corp | Diode |
| US20130214394A1 (en) * | 2012-02-22 | 2013-08-22 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
| CN105304696A (en) * | 2015-10-29 | 2016-02-03 | 深圳深爱半导体股份有限公司 | Variation of lateral doping (VLD) junction termination structure for semiconductor devices and manufacturing method thereof |
| CN106252420A (en) * | 2016-07-27 | 2016-12-21 | 电子科技大学 | Three ends carry vertical-type constant current device and the manufacture method thereof of safeguard function |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118431301A (en) * | 2024-03-29 | 2024-08-02 | 海信家电集团股份有限公司 | Diode module and method for manufacturing diode module |
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