CN108063165A - Diode and its manufacturing method - Google Patents
Diode and its manufacturing method Download PDFInfo
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- CN108063165A CN108063165A CN201711061906.4A CN201711061906A CN108063165A CN 108063165 A CN108063165 A CN 108063165A CN 201711061906 A CN201711061906 A CN 201711061906A CN 108063165 A CN108063165 A CN 108063165A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 302
- 239000011810 insulating material Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 61
- 229920005591 polysilicon Polymers 0.000 claims description 52
- 230000005611 electricity Effects 0.000 claims description 10
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- 238000009413 insulation Methods 0.000 claims description 3
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- 238000011084 recovery Methods 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 210000000746 body region Anatomy 0.000 description 6
- 238000000605 extraction Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
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- 230000000994 depressogenic effect Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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Abstract
The invention discloses diode and its manufacturing method, wherein the diode includes：The first semiconductor region has the first conduction type；At least one second semiconductor regions, it is arranged in the first semiconductor region, and the surface of second semiconductor regions is flushed with the surface of the first semiconductor region, and second semiconductor regions have second conduction type opposite with first conduction type；Wherein, at least one sunk area is formed in the surface of second semiconductor regions, the sunk area is insulating materials.The diode that the embodiment of the present invention is provided can shorten the length in lateral resistance area while surface temperature is reduced, so as to reduce the size of diode.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to diode and its manufacturing method.
Background technology
It is necessary to have processing high voltage, the abilities of high current for diode, particularly high-voltage diode.Figure 1A and Figure 1B points
Not using diode to be illustrated Longitudinal cross section schematic of the existing diode when bearing forward bias and reverse biased, wherein
100 be N-type substrate, and 200 be P-doped zone, and 300 be first electrode, and 400 be insulating layer, and 500 be second electrode.In horizontal position
It puts, first electrode 300 is known as active area with the part that P-doped zone 200 contacts；First electrode 300 and P-doped zone 200
The lateral edges of the edge of contact to P-doped zone 200 are known as lateral resistance area, and lateral resistance area can be equivalent to resistance R；It is active
Part outside area and lateral resistance area is known as termination environment.
As shown in Figure 1A, when first electrode 300 plus positive voltage, second electrode 500 plus negative voltage (during forward conduction),
The how sub- hole of P-doped zone 200 flows to N-doped zone 100 by the edge of P-doped zone 200, in 100 shape of N-doped zone
Into excess holes (i.e. excess carriers).Since the doping concentration on 200 surface of P-doped zone is higher, resistance is smaller, p-type doping
The hole of 200 lateral edges of area (lateral edges are position shown in thick line in Figure 1A and Figure 1B, and dotted arrow show hole path)
The surface can be collected in and flow into N-doped zone 100 (lateral hole injection also referred to as occurs).
As shown in Figure 1B, when first electrode 300 plus negative voltage, second electrode 500 plus positive voltage (during Reverse recovery),
The excess holes of N-doped zone 100 flows into P-doped zone 200, is further extracted by first electrode 300.Also due to p-type
The doping concentration on 200 surface of doped region is higher, resistance is smaller, and the hole of 200 near side edges of P-doped zone can be collected in the table
Surface current enters P-doped zone 200.The voltage difference of electrode is higher during due to Reverse recovery, and carrier during Reverse recovery gathers
Effect is more prominent so that the surface temperature of P-doped zone 200 is higher than other regions；And the superfluous current-carrying that moment is extracted
Son is more, and temperature is higher.
During forward conduction, if the length in lateral resistance area is shorter, not even zero (not having lateral resistance area), then due to P
100 surface dopant concentration of type doped region is higher, resistance is smaller, and the pressure drop for causing first electrode 300 to lateral edges is smaller so that PN
Junction bias is larger, has and pours in N-doped zone 100 by lateral edges compared with multi-hole；Longer lateral resistance area enables to
The pressure drop of one electrode 300 to lateral edges increases, and PN junction bias reduces at lateral edges, and moment pours in N-doped zone by lateral edges
100 number of cavities is reduced, so as to reduce the lateral injection of carrier.
During Reverse recovery, the right end that lateral resistance area is equivalent to resistance R of the hole current shown in Figure 1B flows to left end,
So that the voltage of right end forms self-biasing effect higher than left end namely lateral resistance area, specifically, since first electrode 300 is
Negative voltage, second electrode 500 are positive voltage, then lateral edges and the voltage difference of second electrode 500 are less than first electrode 300 and second
The voltage difference of electrode 500.Set lateral resistance region that can reduce the reverse biased of PN junction at lateral edges and reduce side as a result,
The electric field strength of edge so that the number of cavities that moment is reversed extraction is reduced, so as to reduce the table in reversely restoring process
The temperature in face.The length in lateral resistance area is longer, and self-biasing effect is stronger, and the number of cavities that moment is reversed extraction is fewer, instead
Into recovery process, the temperature on the surface is lower.
Therefore, to solve the temperature on the surface of P-doped zone 200, in the prior art usually by the horizontal stroke in lateral resistance area
It is made longer to length, moment pours in the number of cavities of N-doped zone 100 by lateral edges, reduction moment is reversed to reduce
The electric field strength of PN junction at the number of cavities and lateral edges of extraction.However, the length in lateral resistance area is longer, diode is whole
Size it is bigger.For example, the high-voltage diode for being currently used for 3.3kV, the width in lateral resistance area reaches up to a hundred or even number
Hundred microns.
The content of the invention
In view of this, an embodiment of the present invention provides a kind of diode and its manufacturing method, using solve existing diode as
Reduce device surface temperature and larger-size problem.
First aspect present invention provides a kind of diode, including：The first semiconductor region has the first conductive-type
Type；At least one second semiconductor regions, are arranged in the first semiconductor region, and second semiconductor regions
Surface is flushed with the surface of the first semiconductor region, and second semiconductor regions have and the first conduction type phase
The second anti-conduction type；Wherein, at least one sunk area, institute are formed in the surface of second semiconductor regions
It is with insulating materials to state sunk area.
Optionally, the diode further includes：First insulating layer is arranged on the first semiconductor region and described second
On the surface of semiconductor regions；The sunk area is integrally formed with first insulating layer.
Optionally, the diode further includes：First electrode is arranged on the surface of second semiconductor regions
On, the first electrode connects in the sunk area away from second semiconductor regions with the first semiconductor region
Tactile one side is contacted with second semiconductor regions；Second electrode is arranged on another surface of the first semiconductor region
On.
Optionally, the first electrode does not contact or the table with the sunk area with the surface of the sunk area
Face tap is touched.
Optionally, the diode further includes：Doped polysilicon layer is arranged on first insulating layer；Second insulation
Layer, is arranged on the doped polysilicon layer, opening is provided in the second insulating layer, the first electrode is opened by described
Mouth is contacted with the doped polysilicon layer above second semiconductor regions.
Optionally, the diode further includes：At least one the third semiconductor region is arranged on first semiconductor region
On domain, and the surface of the third semiconductor region is flushed with the surface of the first semiconductor region, and the described 3rd
Semiconductor regions have the second conduction type.
Optionally, the diode further includes：Electrode is contacted, is arranged in the second insulating layer, the contact electrode
Pass through the opening for penetrating through first insulating layer, the doped polysilicon layer and the second insulating layer and the 3rd semiconductor
Region contacts.
Optionally, the diode further includes：At least one the fourth semiconductor region is arranged on first semiconductor region
On domain, and the surface of described the fourth semiconductor region is flushed with the surface of the first semiconductor region, and the described 4th
Semiconductor regions have the first conduction type, and the doped polysilicon layer passes through the opening on first insulating layer and institute
State the fourth semiconductor region contact.
Optionally, the diode is high-voltage fast recovery.
Second aspect of the present invention provides a kind of manufacturing method of diode, including：It provides with the first conduction type
The first semiconductor region；Form at least one second semiconductor regions in the first semiconductor region, described the second half lead
The surface of body region is flushed with the surface of the first semiconductor region, and second semiconductor regions have and described the
The second opposite conduction type of one conduction type；At least one recess is formed in the surface of second semiconductor regions
Region, the sunk area are insulating materials.
Optionally, it is described to form at least one sunk area in the surface of second semiconductor regions, it is described
The step of sunk area is insulating materials includes：In the first semiconductor region and the table of second semiconductor regions
Groove is formed on face；The first insulation is formed on the surface of the first semiconductor region and second semiconductor regions
Layer, while first insulating layer fills the groove and forms the sunk area.
Optionally, the method further includes：First electrode is set on the surface of second semiconductor regions, institute
State what first electrode was in contact in separate second semiconductor regions of the sunk area with the first semiconductor region
One side is contacted with second semiconductor regions；Second electrode is set on another surface of the first semiconductor region.
Optionally, include in described the step of first electrode is being set on the surface of second semiconductor regions：
Opening, the be open surface for not exposing the sunk area or the opening exposing are formed on first insulating layer
The part surface of the sunk area；In the opening, the first electrode is set.
Optionally, further included described before the step of opening sets the first electrode：Described first
Doped polysilicon layer is formed on insulating layer；Second insulating layer is formed on the doped polysilicon layer；In second semiconductor
Opening is formed in the second insulating layer of overlying regions, the first electrode passes through the opening and the doped polysilicon layer
Contact.
Optionally, the method further includes：At least one 3rd semiconductor region is formed in the first semiconductor region
Domain, the surface of the third semiconductor region are flushed with the surface of the first semiconductor region, the 3rd semiconductor
Region has the second conduction type.
Optionally, the method further includes：Formed above the third semiconductor region penetrate through the second insulating layer,
The opening of the doped polysilicon layer, first insulating layer；Contact electrode, the contact are formed in the second insulating layer
Electrode is by penetrating through the opening and the described 3rd half of first insulating layer, the doped polysilicon layer and the second insulating layer
Conductive region contacts.
Optionally, the method further includes：At least one 4th semiconductor region is formed in the first semiconductor region
Domain, the surface of described the fourth semiconductor region are flushed with the surface of the first semiconductor region, the 4th semiconductor
Region has the first conduction type；Opening is formed on first insulating layer above described the fourth semiconductor region, it is described
Doped polysilicon layer is contacted by the opening on first insulating layer with described the fourth semiconductor region.
The diode and its manufacturing method that the embodiment of the present invention is provided, in the first semiconductor with the first conduction type
The second semiconductor regions with the second conduction type on region are set, and insulating materials is set in the second semiconductor regions
Sunk area, so that in the first semiconductor region and the PN junction positively biased of the second semiconductor regions, the second semiconductor regions
In be collected in the how sub- hole on surface and can bypass the edge of sunk area and flow into the first semiconductor region and form excess holes (i.e.
Surplus carrier), the path in hole, the pressure drop in increase lateral resistance area are extended in the lateral resistance area of similary length so that
PN junction bias reduces, and the number of cavities that moment pours in the first semiconductor region by the lateral edges of the second semiconductor regions is reduced；
When the PN junction of the first semiconductor region and the second semiconductor regions bears higher reverse biased, in the first semiconductor region
Excess holes is collected in surface and flows into the second semiconductor regions, and when further being extracted by electrode, in the second semiconductor regions
Also the edge of sunk area can be bypassed, the path in hole is thus extended in the lateral resistance area of similary length, enhancing is laterally
The self-biasing effect of resistance area so that the number of cavities that extraction is reversed by lateral edges moment is reduced, and reduces the electricity at this
Field intensity and corresponding hole concentration effect, so as to reduce the temperature on the surface during Reverse recovery when PN junction reverse biased (i.e.)
Degree.It can be seen that above-mentioned diode can shorten the length in lateral resistance area while surface temperature is reduced, so as to reduce two
The size of pole pipe.
Description of the drawings
The features and advantages of the present invention can be more clearly understood by reference to attached drawing, attached drawing is schematically without that should manage
It solves to carry out any restrictions to the present invention, in the accompanying drawings：
Figure 1A shows Longitudinal cross section schematic during existing diode forward bias；
Figure 1B shows Longitudinal cross section schematic during existing diode reverse biased；
Fig. 2A shows the Longitudinal cross section schematic of another diode according to embodiments of the present invention；
Fig. 2 B show the Longitudinal cross section schematic of another diode according to embodiments of the present invention；
Fig. 3 A show the Longitudinal cross section schematic of another diode according to embodiments of the present invention；
Fig. 3 B show the Longitudinal cross section schematic of another diode according to embodiments of the present invention；
Fig. 4 A show the Longitudinal cross section schematic of another diode according to embodiments of the present invention；
Fig. 4 B show the Longitudinal cross section schematic of another diode according to embodiments of the present invention；
Fig. 5 shows a kind of flow chart of the manufacturing method of diode according to embodiments of the present invention；
Fig. 6 A-6F show the corresponding schematic diagram of each step in the manufacturing method of diode according to embodiments of the present invention；
Fig. 7 shows the flow chart of the manufacturing method of another diode according to the present invention；
Fig. 8 A-8F show the corresponding schematic diagram of each step in the manufacturing method of diode according to embodiments of the present invention.
Specific embodiment
In order to make the purpose of the present invention, advantage, preparation method clearer, below in conjunction with implementation of the attached drawing to the present invention
Example is described in detail, and the example of the embodiment is shown in the drawings, and part-structure has directly given excellent wherein in attached drawing
The structural material of choosing, it is clear that described embodiment is part of the embodiment of the present invention, instead of all the embodiments.It needs
Illustrate, the embodiment being described with reference to the drawings is exemplary, and the structural material shown in embodiment is also exemplary, only
It for explaining the present invention, and is not construed as limiting the claims, the attached drawing of each embodiment of the present invention is merely to signal
Purpose, therefore be not necessarily to scale.Based on the embodiments of the present invention, those skilled in the art are not making wound
All other embodiments obtained under the premise of the property made work, belong to the scope of protection of the invention.
It should be noted that the first conduction type in the application can be N-type, then the second conduction type is p-type；Or
First conduction type is p-type, then the second conduction type is N-type.
Embodiment one
Fig. 2A shows a kind of Longitudinal cross section schematic of diode according to embodiments of the present invention, and as shown in Figure 2 A, this two
Pole pipe includes the first semiconductor region 1, at least one second semiconductor regions 2 and at least one sunk area 6, wherein the first half
Conductive region 1 has the first conduction type, and the second semiconductor regions 2 have second conductive-type opposite with the first conduction type
Type, the surface of the second semiconductor regions 2 are flushed with the surface of the first semiconductor region 1, in the surface of the second semiconductor regions 2
At least one sunk area 6 is formed with, sunk area 6 is with insulating materials.Although a depressed area is illustrated only in Fig. 2A
Domain 6, it should be appreciated to those skilled in the art that more sunk areas 6 are also feasible.The diode of the embodiment of the present invention
Diode especially suitable for high-voltage fast recovery etc..Hereinafter, using the first semiconductor type as N-type, second
Semiconductor type is the detailed description embodiment of the present invention exemplified by p-type.
As shown in Figure 2 A, when being applied in voltage between 1 and second semiconductor regions 2 of the first semiconductor region, such as applied
When adding forward bias, how sub- hole in the second semiconductor regions 2 flows to the first half by the edge of the second semiconductor regions 2 and leads
Body region 1 forms excess holes (i.e. excess carriers) in the first semiconductor region 1.Due to the hole of the second semiconductor regions 2
Concentrate on when the surface flows to the first semiconductor region 1, it is necessary to around sunk area 6 edge, thus in the horizontal stroke of similary length
The path in hole, the pressure drop in increase lateral resistance area are extended into resistance area so that PN junction bias reduces, and moment passes through second
The lateral edges (lateral edges are position shown in thick line in Fig. 2A, and dotted line show hole path) of semiconductor regions 2 pour in first
The number of cavities of semiconductor regions 1 is reduced.
On the other hand, the lateral resistance area shown in Figure 1A is equivalent to R, and the lateral resistance area shown in Fig. 2A is equivalent to R1+
R2+R3, wherein R1 are equivalent to the resistance of the left side edge of sunk area 6, R2 be equivalent to sunk area 6 bottom margin electricity
Resistance, R3 are equivalent to the resistance of the right side edge of sunk area 6.Since the depth of sunk area 6 is deeper, when the second semiconductor regions
When 2 surface dopant concentration is higher, resistance R2 is more than resistance R (doping concentration is higher, and resistance is smaller), the presence of resistance R1, R3
Further increase the resistance in lateral resistance area so that PN junction bias further reduces, the side that moment passes through the second semiconductor regions 2
The number of cavities that edge pours in the first semiconductor region 1 is further reduced.
When being applied in higher reverse biased between 1 and second semiconductor regions 2 of the first semiconductor region, the first half lead
The excess holes of body region flows into the second semiconductor regions 2.When the hole of the near side edges of the second semiconductor regions 2 is collected in
When the surface flows into the second semiconductor regions 2, it is also desirable to around the edge of sunk area 6, thus in the laterally electricity of similary length
Extend the path in hole in resistance area, the self-biasing effect in enhancing lateral resistance area reduces electric field strength at this and corresponding
Hole concentration effect so that by lateral edges moment be reversed extraction number of cavities reduce, so as to reduce Reverse recovery (i.e.
During PN junction reverse biased) during the surface temperature.
It should be added that sunk area 6 can be fully located in lateral resistance area (as shown in Figure 2 A), it can also
Part is located in lateral resistance area (as shown in Figure 2 B).
Above-mentioned diode is set in the first semiconductor region with the first conduction type with the second conduction type
Second semiconductor regions, and the sunk area of insulating materials is set in the second semiconductor regions, so that being led the first half
When body region and the PN junction positively biased of the second semiconductor regions, the how sub- hole on surface is collected in the second semiconductor regions to be bypassed
The edge of sunk area flows into the first semiconductor region and forms excess holes (i.e. excess carriers), in the laterally electricity of similary length
The path in hole, the pressure drop in increase lateral resistance area are extended in resistance area so that PN junction bias reduces, and moment leads by the second half
The number of cavities that the lateral edges of body region pour in the first semiconductor region is reduced；In the first semiconductor region and the second semiconductor region
When the PN junction in domain bears higher reverse biased, the excess holes in the first semiconductor region, which is collected in surface and flows into the second half, leads
Body region, and when further being extracted by electrode, the edge of sunk area can be also bypassed in the second semiconductor regions, thus same
The path in hole is extended in the lateral resistance area of sample length, the self-biasing effect in enhancing lateral resistance area is reduced at this
Electric field strength and corresponding hole concentration effect so that the number of cavities that extraction is reversed by lateral edges moment is reduced, so as to
Reduce the temperature on Reverse recovery when PN junction reverse biased (i.e.) surface in the process.It can be seen that above-mentioned diode can drop
(simulation result shows that the width in lateral resistance area can be reduced the length in shortening lateral resistance area while low surface temperature
To existing 30-70%, for example, 35%, 40%, 45%, 50%, 55%, 60%, 65%), so as to reduce the size of diode.
For example, in 3.3kV fast recovery diodes, lateral resistance sector width is up to 120 μm or more, but the embodiment of the present invention in the prior art
The lateral resistance area of the semiconductor devices provided only needs 50-70 μm, it is possible thereby to reduce the additional area of semiconductor devices, increases
Big active region area improves the utilization rate of semiconductor devices.
Diode in the present embodiment can also include the first insulating layer 41, be arranged on the first semiconductor region and the second half
On the surface of conductive region.Sunk area 6 is integrally formed with first insulating layer 41.
Diode in the present embodiment can also include first electrode 3 and second electrode 5.As shown in Figure 2 A and 2 B,
One electrode 3 is arranged on the surface of the second semiconductor regions 2, and first electrode 3 is in sunk area 6 away from the second semiconductor regions
2 one sides being in contact with the first semiconductor region 1 are contacted with the second semiconductor regions 2.Namely sunk area 6 is located at the first electricity
Between the lateral edges (lateral edges are position shown in thick line in figure) of 3 and second semiconductor regions 2 of pole.In Fig. 2A and Fig. 2 B,
Second electrode 5 is arranged on another surface of the first semiconductor region 1, but the present invention is not limited thereto, in fact, the second electricity
Pole 5 can also be arranged on on the surface of the first semiconductor region 1 of 3 homonymy of first electrode；Alternatively, such as Fig. 2A and Fig. 2 B institutes
Show, can be arranged on and above-mentioned " surface " (upper surface in figure) opposite surface (i.e. lower surface)；Or side can be arranged on
Surface, the application do not limit herein.
As the optional embodiment of the present embodiment, first electrode 3 do not contacted with the surface of sunk area 6 or with it is recessed
Fall into the surface portion contact in region 6.Fig. 2A shows the situation that first electrode 3 is not contacted with the surface of sunk area 6, and Fig. 2 B show
The situation that first electrode 3 is contacted with the surface of sunk area 6 is gone out.
Optionally, in Fig. 2A and Fig. 2 B, the width of sunk area 6 is 30-50 μm, and depth is 2-6 μm, and doping concentration is
1.2e18.The distance of the right side edge of sunk area 6 and the right side edge of the second semiconductor regions 2 is 10-25 μm, sunk area
6 left side edge is 30-40 μm with the distance of first electrode 3.The width of the first semiconductor region 1 is 100-120 μm, and depth is
10-15 μm, surface dopant concentration 1e17-5e17.The inside doping concentration of substrate 1 is 1.5e13-5e13, thickness 200-
250μm。
As a kind of optional embodiment of the present embodiment, which further includes the first insulating layer 41, DOPOS doped polycrystalline silicon
Layer 8 and second insulating layer 42.
First insulating layer 41 is arranged on the surface of 1 and second semiconductor regions 2 of the first semiconductor region.DOPOS doped polycrystalline silicon
Layer 8 is arranged on the first insulating layer 41.Second insulating layer 42 is arranged on doped polysilicon layer 8, is set in second insulating layer 42
There is opening, first electrode 3 is contacted by opening with the doped polysilicon layer 8 of 2 top of the second semiconductor regions.
As shown in Figure 3A, in the lateral resistance area above the second semiconductor regions 2, it is disposed with the first insulating layer
41st, doped polysilicon layer 8 and second insulating layer 42, and opening is provided in second insulating layer.First electrode 3 extends to covering
Second insulating layer 42 above lateral resistance area, and pass through the opening in second insulating layer and contacted with doped polysilicon layer 8.Laterally
The DOPOS doped polycrystalline silicon 8 of resistance area is independently arranged, i.e., is not contacted with the doped polysilicon layer of other parts.
Above-mentioned DOPOS doped polycrystalline silicon can improve the voltage that semiconductor devices is resistant to as field plate.
Embodiment two
Difference lies in the diode in the present embodiment further includes at least one the third semiconductor region 7 with embodiment one.
As shown in Figure 3A, which is arranged in the first semiconductor region 1, and the surface of the third semiconductor region 7
It is flushed with the surface of the first semiconductor region 1, the third semiconductor region 7 has the second conduction type, i.e. p-type.3rd semiconductor
Region 7 has been sequentially arranged above the first insulating layer 41, doped polysilicon layer 8 and second insulating layer 42.
Above-mentioned the third semiconductor region 7 can be used as field limiting ring, improve the pressure-resistant of diode.Above the third semiconductor region
Doped polysilicon layer is independently arranged and (is not contacted with the doped polysilicon layer of other parts), is used as floating field plate, can be with
Further improve the pressure-resistant of diode.Simulation result shows obtaining lateral resistance value same as the prior art (i.e. horizontal electricity
Hinder the resistance value in area) in the case of, the lateral resistance sector width of the semiconductor devices with floating field plate can be reduced in the present embodiment
Existing such as 35%, 40%, 45%, 50%, 55%, 60%, 65%, it is pressure-resistant to reach 3.3kV or so.
Further, which can also include contact electrode 13.As shown in Figure 3B, which is arranged on
On two insulating layers 42, contact electrode 13 is by penetrating through the first insulating layer 41, doped polysilicon layer 8 and the opening of second insulating layer 42
It is contacted with the third semiconductor region 7.Electrode 13 is contacted so that the third semiconductor region 7 and 8 electricity of doped polysilicon layer above it
Property connection, formed contact field plate, it is pressure-resistant in reversely restoring process that diode can be further improved.Such as simulation result table
Bright, the pressure-resistant of semiconductor devices with contact field plate can reach 4.5kV or so.
Embodiment three
Difference lies in the diode in the present embodiment further includes at least one 4th half with embodiment one and embodiment two
Conductive region 9.As shown in Figure 4 A and 4 B shown in FIG., which is arranged in the first semiconductor region 1, and the 4th
The surface of semiconductor regions 9 is flushed with the surface of the first semiconductor region 1, and the fourth semiconductor region 9 has the first conduction type,
That is N-type.The fourth semiconductor region 9 has been sequentially arranged above the first insulating layer 41, doped polysilicon layer 8 and second insulating layer
42, and doped polysilicon layer 8 is contacted by the opening on the first insulating layer 41 with the fourth semiconductor region 9.
Above-mentioned the fourth semiconductor region makees that cut-off ring can be used as, the independently arranged DOPOS doped polycrystalline silicon 8 contacted with cut-off ring
(not contacted with the doped polysilicon layer of other parts) can be used as field plate.
It should be added that in above-described embodiment one, two, three, most of the first semiconductor region 1 is lightly doped district
11, the part contacted with second electrode 5 is heavily doped region 12, so as to form good Ohmic contact with second electrode 5.The second half
Conductive region 2 can be heavy doping；Alternatively, only the place contacted with first electrode 3 be heavy doping, so as to first electrode 3
Form good Ohmic contact.The third semiconductor region 7 can be heavy doping；Alternatively, set contact electrode 13 when, only with
It is heavy doping to contact the place that electrode 13 contacts, so as to form good Ohmic contact with contacting electrode 13.
Example IV
Fig. 5 shows a kind of flow chart of the manufacturing method of diode according to embodiments of the present invention, can be used for manufacturing
Diode described in embodiment one or embodiment two or its any one optional embodiment.As shown in figure 5, this method bag
Include following steps：
S101：The first semiconductor region with the first conduction type is provided.
S102：At least one second semiconductor regions, the table of the second semiconductor regions are formed in the first semiconductor region
Face is flushed with the surface of the first semiconductor region, and the second semiconductor regions have opposite with the first conduction type second to lead
Electric type.
As shown in Figure 6A, 1 be N-type the first semiconductor region, 2 be the second semiconductor regions 2.Form the second semiconductor region
The method in domain 2 can be miscellaneous by the flat surface injection of the techniques such as ion implanting or thermal diffusion to the first semiconductor region 1
Matter ion, so as to form the second semiconductor regions 2.
S103：At least one sunk area is formed in the surface of the second semiconductor regions, sunk area is insulating materials.
As shown in Figure 6B, 6 be sunk area.The method for forming sunk area 6 can be in the first semiconductor region and the
When the surface of two semiconductor regions forms insulating layer, insulating layer filling groove is made to form sunk area 6.
S104：First electrode is set on the surface of the second semiconductor regions, and first electrode is in sunk area away from the
The one side that two semiconductor regions are in contact with the first semiconductor region is contacted with the second semiconductor regions.
As shown in Figure 6 C, the lateral edges of 3 and second semiconductor regions 2 of first electrode are located at the both sides of sunk area 6 respectively.
Step S104 can first form insulating layer on the surface of 1 and second semiconductor regions 2 of the first semiconductor region
4, as shown in Figure 6 D；Then opening is formed on insulating layer 4, opening does not expose the surface of sunk area 6 or the exposing that is open is recessed
The part surface (in figure only by taking the surface that opening does not expose sunk area 6 as an example) in region 6 is fallen into, as illustrated in fig. 6e；Finally opening
First electrode 3 is set at mouthful, as fig 6 f illustrates.
S105：Second electrode is set on another surface of the first semiconductor region.
Such as another surface that can be oppositely arranged on the surface with the first semiconductor 1 sets second electrode 5, it can also be
Side sets second electrode 5, and the application does not limit this.
The manufacturing method of above-mentioned diode is formed in the first semiconductor region with the first conduction type with second
Second semiconductor regions of conduction type, and in the second semiconductor regions formed insulating materials sunk area, so as to
Shorten the length in lateral resistance area while surface temperature is reduced, so as to reduce the size of diode, specifically refer to implementation
Example one.
Embodiment five
Fig. 7 shows the flow chart of the manufacturing method of another diode according to the present invention, can be used for manufacture and implements
Diode described in example one to embodiment three or its any one optional embodiment.As shown in fig. 7, this method is included such as
Lower step：
S201：The first semiconductor region with the first conduction type is provided.
S202：At least one second semiconductor regions and at least one 3rd semiconductor are formed in the first semiconductor region
Region.The surface of second semiconductor regions is flushed with the surface of the first semiconductor region, and the second semiconductor regions have with
The second opposite conduction type of first conduction type.The surface of the third semiconductor region and the surface of the first semiconductor region are neat
Flat, the third semiconductor region has the second conduction type.Second semiconductor regions and the third semiconductor region can be formed synchronously,
It can also be respectively formed, be preferably synchronous formed.
As shown in Figure 8 A, the first semiconductor region can include lightly doped district 11 and heavily doped region 12.Can be light in N-type
By techniques such as ion implanting or thermal diffusions to for setting a face impurity ion of second electrode on the semiconductor of doping,
Form heavily doped region 12.The step of forming heavily doped region 12 only need to be before the step of " setting second electrode 5 ".
As shown in Figure 8 A, 2 be the second semiconductor regions, and 7 be the third semiconductor region, and the third semiconductor region is led for p-type
Electricity.The method for forming the second semiconductor regions 2 and the third semiconductor region 7 can be by works such as ion implanting or thermal diffusions
Skill is to the flat surface implanting impurity ion of the first semiconductor region 1.
S203：Groove is formed on the surface of the second semiconductor regions.
As shown in Figure 8 B, 6 be groove.
S204：At least one the fourth semiconductor region, the table of the fourth semiconductor region are formed in the first semiconductor region
Face is flushed with the surface of the first semiconductor region, and the fourth semiconductor region has the first conduction type.
As shown in Figure 8 C, 9 be the fourth semiconductor region, and the fourth semiconductor region is conductive for N-type.Form the 4th semiconductor region
The method in domain 9 can be miscellaneous by the flat surface injection of the techniques such as ion implanting or thermal diffusion to the first semiconductor region 1
Matter ion, so as to form the fourth semiconductor region 9.
S205：The first insulating layer, while first are formed on the surface of the first semiconductor region and the second semiconductor regions
Insulating layer filling groove forms sunk area；And the first opening is formed on the first insulating layer above the fourth semiconductor region.
As shown in Figure 8 C, 41 be the first insulating layer.First insulating layer 41 fills groove, is integrally formed with sunk area.
It should be added that as formation the third semiconductor region, the 4th semiconductor region in step S202 and S204
A kind of alternative in domain, can also first form opening on the first insulating layer, which uses as ion implanting window
Ion implantation injects ion to the first semiconductor region by window and forms the third semiconductor region or the fourth semiconductor region,
Can the insulating layer of layer be formed in open bottom again before doped polysilicon layer is formed, that is, be formed as shown in Figure 8 C
First insulating layer.If being initially formed the third semiconductor region and the fourth semiconductor region, the first insulating layer 41 is re-formed, then first absolutely
The surface of edge layer can also flush.
S206：Doped polysilicon layer is formed on the first insulating layer.
As in fig. 8d, 8 be doped polysilicon layer.Since the first insulating layer 41 of 9 top of the fourth semiconductor region is formed
There is the first opening, therefore doped polysilicon layer 8 is contacted by the first opening on the first insulating layer with the fourth semiconductor region.It mixes
Miscellaneous polysilicon layer has the first conduction type.
S207：Opening is formed on doped polysilicon layer so that doped polysilicon layer above the second semiconductor regions, the
The doped polysilicon layer above doped polysilicon layer, the fourth semiconductor region above three semiconductor regions disconnects two-by-two, and
Doped polysilicon layer above adjacent the third semiconductor region disconnects two-by-two.
It should be added that the fourth semiconductor region 9 synchronous with doped polysilicon layer can be formed.Specifically, first
Formed doped polysilicon layer 8, then to DOPOS doped polycrystalline silicon layer surface injection with the first conduction type semiconductor impurities (such as
Phosphonium ion).Since the first insulating layer is equipped with opening, the DOPOS doped polycrystalline silicon of the opening is contacted with the first semiconductor region 1,
The 4th semiconductor region is formed so as to which semiconductor impurities can be injected into the first semiconductor region 1 by DOPOS doped polycrystalline silicon herein
Domain.
S208：Second insulating layer is formed on doped polysilicon layer.
As in fig. 8d, 42 be second insulating layer.
S209：The second opening is formed in the second insulating layer above the second semiconductor regions.
S210：The 3rd opening is formed in the first insulating layer, doped polysilicon layer, second insulating layer, the 3rd opening is not
Expose the surface of sunk area or the 3rd opening exposes the part surface of sunk area.
After the step as illustrated in fig. 8e.
S211：First electrode is set on the surface of the second semiconductor regions, and first electrode passes through the second opening and doping
Polysilicon layer contacts.
As shown in Figure 8 F, first electrode 3 is extended in second insulating layer, by second insulating layer 42 second opening with
Doped polysilicon layer contacts.First electrode 3 is in sunk area 6 away from the second semiconductor regions 2 and 1 phase of the first semiconductor region
The one side of contact is contacted with the second semiconductor regions 2.Namely the lateral edges difference position of 3 and second semiconductor regions 2 of first electrode
In the both sides of sunk area 6.
S212：Second electrode is set on another surface of the first semiconductor region.
The step refers to the step S105 of example IV.
It can be formed such as by above-mentioned steps, then in the surface of second insulating layer 42 and first electrode 3 formation passivation layer
Diode shown in Fig. 4 A.
As a kind of optional embodiment of the present embodiment, after step S211, can also as follows be formed such as
Diode shown in Fig. 4 B.
S213：Perforation second insulating layer, doped polysilicon layer, first insulating layer are formed above the third semiconductor region
Opening.
S214：Contact electrode is formed over the second dielectric, and contact electrode is by penetrating through the first insulating layer, DOPOS doped polycrystalline silicon
The opening of layer and second insulating layer is contacted with the third semiconductor region.
As described in Fig. 8 F, 13 be contact electrode.43 be passivation layer.
Although being described in detail on example embodiment and its advantage, those skilled in the art can not depart from
Various change is carried out to these embodiments in the case of the spiritual and defined in the appended claims protection domain of the present invention, is replaced
And modification, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples, ability
The those of ordinary skill in domain should be readily appreciated that the order of processing step can become while keeping in the scope of the present invention
Change.
In addition, the application range of the present invention is not limited to technique, mechanism, the system of the specific embodiment described in specification
It makes, material composition, means, method and step.It, will be easy as those of ordinary skill in the art from the disclosure
Ground understands, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means, method or
Step, the knot that the function or acquisition that the corresponding embodiment that wherein they are performed with the present invention describes is substantially the same are substantially the same
Fruit can apply them according to the present invention.Therefore, appended claims of the present invention are intended to these techniques, mechanism, system
It makes, material composition, means, method or step are included in its protection domain.
Claims (17)
1. a kind of diode, which is characterized in that including：
The first semiconductor region has the first conduction type；
At least one second semiconductor regions, are arranged in the first semiconductor region, and second semiconductor regions
Surface flushed with the surface of the first semiconductor region, second semiconductor regions have and first conduction type
The second opposite conduction type；Wherein,
At least one sunk area is formed in the surface of second semiconductor regions, the sunk area is with exhausted
Edge material.
2. diode according to claim 1, which is characterized in that further include：
First insulating layer is arranged on the surface of the first semiconductor region and second semiconductor regions；
The sunk area is integrally formed with first insulating layer.
3. diode according to claim 2, which is characterized in that further include：
First electrode is arranged on the surface of second semiconductor regions, and the first electrode is in the sunk area
The one side being in contact with the first semiconductor region away from second semiconductor regions, with second semiconductor regions
Contact；
Second electrode is arranged on another surface of the first semiconductor region.
4. diode according to claim 3, which is characterized in that the first electrode not surface with the sunk area
Contact is contacted with the surface portion of the sunk area.
5. diode according to claim 4, which is characterized in that further include：
Doped polysilicon layer is arranged on first insulating layer；
Second insulating layer is arranged on the doped polysilicon layer, and opening, first electricity are provided in the second insulating layer
Pole is contacted by the opening with the doped polysilicon layer above second semiconductor regions.
6. diode according to claim 4, which is characterized in that further include：
At least one the third semiconductor region is arranged in the first semiconductor region, and the third semiconductor region
Surface flushed with the surface of the first semiconductor region, the third semiconductor region have the second conduction type.
7. diode according to claim 6, which is characterized in that further include：Electrode is contacted, is arranged on second insulation
On layer, the contact electrode is by penetrating through opening for first insulating layer, the doped polysilicon layer and the second insulating layer
Mouth is contacted with the third semiconductor region.
8. diode according to claim 5, which is characterized in that further include：
At least one the fourth semiconductor region is arranged in the first semiconductor region, and described the fourth semiconductor region
Surface flushed with the surface of the first semiconductor region, described the fourth semiconductor region have the first conduction type,
And the doped polysilicon layer is contacted by the opening on first insulating layer with described the fourth semiconductor region.
9. according to claim 1 to 8 any one of them diode, which is characterized in that the diode is that high pressure recovers two soon
Pole pipe.
10. a kind of manufacturing method of diode, which is characterized in that including：
The first semiconductor region with the first conduction type is provided；
At least one second semiconductor regions, the surface of second semiconductor regions are formed in the first semiconductor region
It is flushed with the surface of the first semiconductor region, and second semiconductor regions have and the first conduction type phase
The second anti-conduction type；
At least one sunk area is formed in the surface of second semiconductor regions, the sunk area is insulation material
Material.
11. the manufacturing method of diode according to claim 10, which is characterized in that described in second semiconductor region
At least one sunk area is formed in the surface in domain, the sunk area includes for the step of insulating materials：
Groove is formed on the surface of second semiconductor regions；
The first insulating layer, while institute are formed on the surface of the first semiconductor region and second semiconductor regions
It states the first insulating layer filling groove and forms the sunk area.
12. the manufacturing method of diode according to claim 11, which is characterized in that further include：
First electrode is set on the surface of second semiconductor regions, and the first electrode is in the sunk area
Away from the one side that second semiconductor regions are in contact with the first semiconductor region, connect with second semiconductor regions
It touches；
Second electrode is set on another surface of the first semiconductor region.
13. the manufacturing method of diode according to claim 12, which is characterized in that described in second semiconductor
Being set on the surface in region the step of first electrode includes：
Opening is formed on first insulating layer, the opening does not expose the surface of the sunk area or the opening
Expose the part surface of the sunk area；
In the opening, the first electrode is set.
14. the manufacturing method of diode according to claim 13, which is characterized in that set described in the opening
Before the step of first electrode, further include：
Doped polysilicon layer is formed on first insulating layer；
Second insulating layer is formed on the doped polysilicon layer；
Opening is formed in the second insulating layer above second semiconductor regions, the first electrode is opened by described
Mouth is contacted with the doped polysilicon layer.
15. the manufacturing method of diode according to claim 13, which is characterized in that further include：
At least one the third semiconductor region, the surface of the third semiconductor region are formed in the first semiconductor region
It is flushed with the surface of the first semiconductor region, the third semiconductor region has the second conduction type.
16. the manufacturing method of diode according to claim 15, which is characterized in that further include：
It is formed above the third semiconductor region and penetrates through the second insulating layer, the doped polysilicon layer, described first
The opening of insulating layer；
Contact electrode is formed in the second insulating layer, the contact electrode is by penetrating through first insulating layer, described mixing
The opening of miscellaneous polysilicon layer and the second insulating layer is contacted with the third semiconductor region.
17. the manufacturing method of diode according to claim 14, which is characterized in that further include：
At least one the fourth semiconductor region, the surface of described the fourth semiconductor region are formed in the first semiconductor region
It is flushed with the surface of the first semiconductor region, described the fourth semiconductor region has the first conduction type；
Opening is formed on first insulating layer above described the fourth semiconductor region, the doped polysilicon layer passes through institute
The opening stated on the first insulating layer is contacted with described the fourth semiconductor region.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150859A (en) * | 1998-11-18 | 2000-05-30 | Meidensha Corp | Diode |
| US20020195613A1 (en) * | 2001-04-02 | 2002-12-26 | International Rectifier Corp. | Low cost fast recovery diode and process of its manufacture |
| US20050056912A1 (en) * | 2003-09-12 | 2005-03-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN107293599A (en) * | 2017-07-19 | 2017-10-24 | 中国科学院微电子研究所 | Silicon carbide power device terminal and preparation method thereof |
-
2017
- 2017-11-02 CN CN201711061906.4A patent/CN108063165A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150859A (en) * | 1998-11-18 | 2000-05-30 | Meidensha Corp | Diode |
| US20020195613A1 (en) * | 2001-04-02 | 2002-12-26 | International Rectifier Corp. | Low cost fast recovery diode and process of its manufacture |
| US20050056912A1 (en) * | 2003-09-12 | 2005-03-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN107293599A (en) * | 2017-07-19 | 2017-10-24 | 中国科学院微电子研究所 | Silicon carbide power device terminal and preparation method thereof |
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Application publication date: 20180522 |