CN102569207A - Method for integrating Schottky diode in super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) - Google Patents
Method for integrating Schottky diode in super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) Download PDFInfo
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- CN102569207A CN102569207A CN2010106058544A CN201010605854A CN102569207A CN 102569207 A CN102569207 A CN 102569207A CN 2010106058544 A CN2010106058544 A CN 2010106058544A CN 201010605854 A CN201010605854 A CN 201010605854A CN 102569207 A CN102569207 A CN 102569207A
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Abstract
The invention discloses a method for integrating a Schottky diode in a super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The Schottky diode formed by Schottky contact and a substrate is integrated in parallel to the super junction MOSFET; the anode of the Schottky diode is arranged between two adjacent body regions of a structure cell region source end of a super junction MOSFET chip, and is connected with the source end of the super junction MOSFET; and the cathode of the Schottky diode shares a source electrode positioned on the back face of the substrate. The super junction MOSFET is connected in parallel with the structure of the Schottky diode, so that the reverse restoring speed of a super junction MOSFET device is increased by using the rapid switching characteristic of the Schottky diode.
Description
Technical field
The present invention relates to a kind of in super junction MOSFET the method for integrated schottky diode.
Background technology
From the sixties in 20th century of early stage small scale integrated circuit since the epoch, the performance of semiconductor microactuator chip has obtained huge raising.Do more for a short time through device, on chip, place closely more, the speed of chip will be improved.
The method of the reverse resume speed of conventional raising MOSFET device (mos field effect transistor) has two kinds:
A kind of is in N type epitaxial loayer, to mix beavy metal impurity or the method through irradiation forms certain complex centre in N type epitaxial loayer, reduces the reverse recovery time of minority carrier in N type epitaxial loayer thereby reach, the reverse resume speed of raising MOSFET.
A kind of in addition is integrated schottky diode in the MOSFET, this technology be employed in the MOSFET source leak between parallel connection insert Schottky diode, the high-speed switch characteristic through Schottky diode realizes that the snap back of MOSFET recovers.This technology generally is used among the conventional MOSFET of high pressure.
Super junction MOSFET is a kind of Novel MOS FET device that on the basis of power MOSFET, grows up; The method of this devices use charge balance makes the width of depletion region broadening of reverse biased junction improve the withstand voltage of device; Thereby make the doping content that satisfies the drift region of drain terminal under the withstand voltage condition be greatly improved, reduced the conducting resistance of device.The application of super junction MOSFET makes the contradiction of withstand voltage conducting resistance of silicon power device obtain very big improvement.Super junction MOSFET generally understands fast recovery diode chip of parallel connection to improve the reverse resume speed of super junction MOSFET chip as switch module in application; The method of direct integrated schottky diode also can improve the response speed of switch to a certain extent in super junction MOSFET device architecture, has improved the matching of two parallelly connected devices simultaneously.
Summary of the invention
The technical problem that the present invention will solve provide a kind of in super junction MOSFET the method for integrated schottky diode, it will improve the response speed of switch greatly.
For solving the problems of the technologies described above; Of the present invention in super junction MOSFET the method for integrated schottky diode; For: parallel connection is integrated with the Schottky diode that is formed by Schottky contacts and substrate in said super junction MOSFET; The anode of wherein said Schottky diode is arranged between adjacent two tagmas of cellular area source end of super junction MOSFET chip; The anode of said Schottky diode links to each other with the source end of said super junction MOSFET, the shared drain electrode that is positioned at substrate back of the negative electrode of said Schottky diode.
The present invention has improved the switching speed of super junction MOSFET device through parallelly connected Schottky diode in super junction MOSFET.Schottky diode is parallelly connected with MOSFET's, can reduce the effect of parasitic PN junction diode among the super junction MOSFET.Because Schottky diode is a majority carrier device, the physical process that it does not oppositely exist many sons and few son to recover is so it is very short to the intermediate state time the reverse off state from the forward on-state.Behind this device of MOSFET parallel connection, can improve its switching response speed greatly.Utilize the reverse resume speed of the high-speed switch characteristic raising super junction MOSFET device of Schottky diode.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the schematic layout pattern of metal wire;
Fig. 2 is the schematic layout pattern of contact hole;
Fig. 3 is for adopting the prepared super junction MOSFET structural representation of method of the present invention;
Fig. 4 is the structural representation after polysilicon gate forms in the employing method of the present invention;
Fig. 5 is for adopting the structural representation behind the contact hole etching in the method for the present invention.
Embodiment
Method of the present invention; Be parallelly connected Schottky diode in super junction MOSFET; Referring to Fig. 1 to Fig. 3, wherein Fig. 1 is the domain sketch map of polysilicon gate and metal wire, and Fig. 2 is the domain sketch map of polysilicon gate and contact hole; Fig. 3 is for along the sketch map that adds on the basis of the section of the line 1-2 among Fig. 1 and Fig. 2 behind the metal wire, and wherein metal wire is regional for covering whole cellular.Can know by figure; In super junction MOSFET parallel connection the Schottky diode of forming by substrate E and Schottky contacts K; Wherein the anode of Schottky diode is Schottky contacts K; This Schottky contacts links to each other with the source end of super junction MOSFET through metal wire, the negative electrode of Schottky diode is the then shared drain electrode of substrate back.The anode of Schottky diode is generally positioned between adjacent two tagma C (instantiation can be P type well region) of super junction MOSFET chip cellular area source end.
In the manufacturing process of this device, for the flow process of utilizing super junction MOSFET is made this multiple device, the difference of itself and simple super junction MOSFET flow process is:
After the polysilicon deposit is accomplished; When polysilicon gate G opened through mask exposure and quarter; Except the source region is carved open, also carve to the anode place of Schottky diode shown in Figure 3 and open (see figure 4) at Fig. 1, the polysilicon that promptly will be positioned at Schottky diode anode place is simultaneously removed; In the preparation process, need correspondingly revise the figure of mask;
In the first dielectric layer I deposition process; Utilize dielectric layer to cover the source region of MOSFET and the anode contact zone of Schottky diode; Utilize electrode contact hole mask version to open the anode place of source electrode and Schottky diode subsequently; Promptly form source electrode contact hole and Schottky contacts hole K1 (see figure 5), wherein also need revise original electrode contact hole mask, increase the figure in Schottky contacts hole;
Insert metal afterwards, and with metal wire source electrode is contacted H and link to each other with metal wire with Schottky contacts K, useful source metal routing J will link to each other between the two in the practical implementation.So just constituted the composite construction of in super junction MOSFET, introducing the Schottky diode of parallel connection.
In the said method; Distance can be arranged between 0.1 micron to 25 microns between the P type trap of Schottky contacts hole and super junction MOSFET; So neither influencing the MOSFET conducting resistance does not influence the reverse breakdown voltage of schottky device again, utilizes the reverse resume speed of the high-speed switch characteristic raising super junction MOSFET device of Schottky diode simultaneously.The length range of polysilicon gate can be between 1 micron to 50 microns, exceed in the width of polysilicon gate its down the distance between tagma (being the C district) between 0.1 micron to 50 microns.In specifically being provided with, the aperture size in Schottky contacts hole is between 0.1 micron to 10 microns.The Schottky contacts hole can be made as square or strip simultaneously.
Introduce the implementing procedure of integrated schottky diode among the concrete super junction MOSFET below, for:
1) the suitable epitaxial substrate E of line options utilizes mask to carry out ion in the specific region and injects the low-doped tagma C of formation;
2) at substrate surface growth gate oxide;
3) definition and etching deep trench are filled the semi-conducting material opposite with the substrate doping and are formed deep trench tagma D; This step also can be carried out low-doped C district in the first step and injected completion before.
4) deposit polysilicon, and utilize the mask etch polysilicon, form polysilicon gate G, need carve out the Schottky contacts bore region of Schottky diode in the etching simultaneously; This step also can utilize the regional mask carving of end ring to open the contact area of Schottky diode according to the relevant processing step in device end ring zone.
5) utilize ion to inject and form highly doped source region A and highly doped tagma B, as the source end of super junction MOSFET device;
6) the deposit first dielectric layer I, and etching first dielectric layer forms source electrode contact hole and Schottky contacts hole, and this first dielectric layer can be silicon oxide layer;
7) depositing metal forms the source electrode contact of super junction MOSFET and the Schottky contacts of parasitic diode (being Schottky diode) to fill source electrode contact hole and Schottky contacts hole, and this metal is generally the tungsten metal;
8) depositing metal, and utilize mask to carry out metal etch to form required metal interconnection structure, utilize metal wire that source electrode is connected with Schottky diode simultaneously, this metal can be copper, aluminium, or interconnecting metal commonly used such as albronze;
9) deposit passivating film, etching passivating film figure expose metal routing zone;
10) forming electrode at substrate back, is the drain electrode of super junction MOSFET and the negative electrode of Schottky diode simultaneously.
In the method for the present invention's parallelly connected Schottky diode in super junction MOSFET; This method do not increase on the basis of quantity and technical process of mask, just promptly realized the parallelly connected of super junction MOSFET and Schottky diode through revising the polysilicon gate mask and the domain of electrode contact hole mask version.
Claims (7)
1. the method for an integrated schottky diode in super junction MOSFET; It is characterized in that: parallel connection is integrated with the Schottky diode that is formed by Schottky contacts and substrate in said super junction MOSFET; The anode of wherein said Schottky diode is arranged between adjacent two tagmas of cellular area source end of super junction MOSFET chip; The anode of said Schottky diode links to each other with the source end of said super junction MOSFET, the shared drain electrode that is positioned at substrate back of the negative electrode of said Schottky diode.
2. according to the described method of claim 1, it is characterized in that the preparation of integrated schottky diode comprises among the said super junction MOSFET:
After polysilicon deposit in super junction MOSFET was accomplished, etching was removed and is positioned at source region and the polysilicon that is positioned at place, Schottky contacts hole, forms polysilicon gate;
After the first dielectric layer deposit is accomplished; Said first dielectric layer of etching is to epi-layer surface; Form source electrode contact hole and Schottky contacts hole, insert metal afterwards and form source electrode contact and Schottky contacts, said Schottky contacts is the anode of said Schottky diode;
In ensuing metal interconnected formation technology, said source electrode contact is connected with the anode of said Schottky diode with metal wire.
3. according to the described method of claim 2, it is characterized in that: the aperture size in said Schottky contacts hole is between 0.1 micron to 10 microns.
4. according to the described method of claim 2, it is characterized in that: said Schottky contacts hole is elongated or square.
5. according to claim 2 or 3 described methods, it is characterized in that: the length of said polysilicon gate is between 1 micron to 50 microns, and the width that the width of polysilicon gate exceeds in the tagma under it is between 0.1 micron to 50 microns.
6. according to the described method of claim 5, it is characterized in that: the distance in said tagma is arrived between 0.1 micron to 25 microns in said Schottky contacts hole.
7. according to claim 2 or 3 described methods, it is characterized in that: have the deep trench tagma among the said super junction MOSFET, the gash depth of the degree of depth of this groove and simple super junction MOSFET is approximate, and scope is between tens to tens microns.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010106058544A CN102569207A (en) | 2010-12-27 | 2010-12-27 | Method for integrating Schottky diode in super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010106058544A CN102569207A (en) | 2010-12-27 | 2010-12-27 | Method for integrating Schottky diode in super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106129119A (en) * | 2016-08-31 | 2016-11-16 | 西安龙腾新能源科技发展有限公司 | Domain structure of superjunction power VDMOSFET of integrated schottky diode and preparation method thereof |
| CN113782608A (en) * | 2021-09-03 | 2021-12-10 | 杭州芯迈半导体技术有限公司 | Super junction MOS device integrated with TMBS structure and manufacturing method thereof |
| CN117238914A (en) * | 2023-11-13 | 2023-12-15 | 深圳天狼芯半导体有限公司 | SiC device integrated with SBD and preparation method |
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| CN101465374A (en) * | 2007-12-21 | 2009-06-24 | 万国半导体股份有限公司 | MOS device with integrated schottky diode in active region contact trench |
| CN101752311A (en) * | 2008-12-17 | 2010-06-23 | 上海华虹Nec电子有限公司 | Method and structure for integrating power MOS transistor and Schottky diode |
| US20100320538A1 (en) * | 2007-08-29 | 2010-12-23 | Rohm Co., Ltd | Semiconductor device |
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2010
- 2010-12-27 CN CN2010106058544A patent/CN102569207A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100320538A1 (en) * | 2007-08-29 | 2010-12-23 | Rohm Co., Ltd | Semiconductor device |
| CN101465374A (en) * | 2007-12-21 | 2009-06-24 | 万国半导体股份有限公司 | MOS device with integrated schottky diode in active region contact trench |
| CN101752311A (en) * | 2008-12-17 | 2010-06-23 | 上海华虹Nec电子有限公司 | Method and structure for integrating power MOS transistor and Schottky diode |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106129119A (en) * | 2016-08-31 | 2016-11-16 | 西安龙腾新能源科技发展有限公司 | Domain structure of superjunction power VDMOSFET of integrated schottky diode and preparation method thereof |
| CN113782608A (en) * | 2021-09-03 | 2021-12-10 | 杭州芯迈半导体技术有限公司 | Super junction MOS device integrated with TMBS structure and manufacturing method thereof |
| CN117238914A (en) * | 2023-11-13 | 2023-12-15 | 深圳天狼芯半导体有限公司 | SiC device integrated with SBD and preparation method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140103 |
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Application publication date: 20120711 |