CN108091616A - The method for packing and encapsulating structure of a kind of chip - Google Patents
The method for packing and encapsulating structure of a kind of chip Download PDFInfo
- Publication number
- CN108091616A CN108091616A CN201711346047.3A CN201711346047A CN108091616A CN 108091616 A CN108091616 A CN 108091616A CN 201711346047 A CN201711346047 A CN 201711346047A CN 108091616 A CN108091616 A CN 108091616A
- Authority
- CN
- China
- Prior art keywords
- chip
- plastic packaging
- packaged
- packaging layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 104
- 238000012856 packing Methods 0.000 title claims abstract description 63
- 238000004806 packaging method and process Methods 0.000 claims abstract description 229
- 239000010410 layer Substances 0.000 claims description 272
- 238000005520 cutting process Methods 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000005022 packaging material Substances 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 15
- 238000005538 encapsulation Methods 0.000 description 7
- 238000010276 construction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses the method for packing and encapsulating structure of a kind of chip, technical solution of the present invention sets chip to be packaged to be located in plastic packaging layer, the front of the chip to be packaged is flushed with the first surface of plastic packaging layer, there is preferable plasticity before curing for forming the plastic packaging material of plastic packaging layer, the preferable first surface of planarization and second surface can be formed, ensure that the reliability of encapsulating structure.
Description
Technical field
The present invention relates to semiconductor process technique field, more specifically, being related to the encapsulating structure and envelope of a kind of chip
Dress method.
Background technology
With the continuous development of science and technology, more and more electronic equipments are widely used in daily life
And among work, huge facility is brought for daily life and work, it is indispensable to become current people
Important tool.Electronic equipment realizes various functions by a variety of chips.In order to ensure the service life of chip and peace
Full stable operation, chip need to form encapsulating structure by packaging technology, and protection is packaged to chip.
When the prior art is packaged chip, the planarization of the encapsulating structure of formation is poor, after causing chip package
The reliability of encapsulating structure is poor.
The content of the invention
To solve the above-mentioned problems, technical solution of the present invention provides the method for packing and encapsulating structure of a kind of chip,
It can cause the encapsulating structure to be formed that there is preferable planarization, ensure that the reliability of encapsulating structure.
To achieve these goals, the present invention provides following technical solution
A kind of method for packing of chip, the method for packing include：
At least one chip to be packaged is provided, the chip to be packaged has opposite front and the back side, positive mask
There are sensing unit and the weld pad being connected with the sensing unit；
Form the plastic packaging layer at the back side for covering the chip to be packaged, the plastic packaging layer have opposite first surface and
Second surface, the chip to be packaged are located in the plastic packaging layer, and its positive is flushed with the first surface；
Interconnection architecture corresponding with the chip to be packaged is formed in the second surface of the plastic packaging layer；The weld pad passes through
The interconnection architecture is connected with external circuit.
Preferably, in above-mentioned method for packing, multiple chips to be packaged are provided, all chips to be packaged are just
Face is generally aligned in the same plane, and is flushed with the first surface；Each chip to be packaged corresponds to an interconnection architecture；
The method for packing further includes：
By cutting technique, the plastic packaging layer is divided into multiple encapsulating structures, the encapsulating structure includes at least one
The chip to be packaged and its corresponding interconnection architecture.
Preferably, in above-mentioned method for packing, the plastic packaging layer for forming the back side for covering the chip to be packaged includes：
A loading plate is provided, the loading plate has the interim bonding surface for carrying the chip to be packaged；
The interim bonding surface of the positive and loading plate of the chip to be packaged is bonded；
The plastic packaging layer is formed, the plastic packaging layer covers the interim bonding table of the chip to be packaged and the loading plate
Face.
Preferably, in above-mentioned method for packing, the interim bonding surface of the loading plate has multiple carrying grooves；One
The carrying groove is for one chip to be packaged of placement；There is gap between the two neighboring carrying groove；It is described
The depth of carrying groove is identical, and less than the thickness of the chip to be packaged；
The interim bonding surface of the positive and loading plate by the chip to be packaged be bonded including：In each institute
It states to carry and places a chip to be packaged in groove respectively, the front of the chip to be packaged and the bottom of the carrying groove
Portion is oppositely arranged.
Preferably, in above-mentioned method for packing, the formation plastic packaging layer includes：
The first plastic packaging layer is formed, the first plastic packaging layer covers the ephemeral key of the chip to be packaged and the loading plate
Close surface；The first plastic packaging layer is the second surface away from the surface of the chip to be packaged；
Remove the loading plate；
The positive side surface for exposing the chip to be packaged in the first plastic packaging layer forms the second plastic packaging layer；It is described
Second plastic packaging layer is the first surface away from a side surface of the first plastic packaging layer.
Preferably, in above-mentioned method for packing, the front that the chip to be packaged is exposed in the first plastic packaging layer
A side surface formed the second plastic packaging layer include：
Protective layer is formed in the front of the chip to be packaged；
The second plastic packaging layer is formed, the thickness of the second plastic packaging layer is more than the chip to be packaged and exposes described first
The thickness of plastic packaging layer；
After removing the protective layer, the second plastic packaging layer is subtracted away from a side surface of the first plastic packaging layer
It is thin, so that the surface and the front flush of the chip to be packaged.
Preferably, in above-mentioned method for packing, the interim bonding surface is plane；
The interim bonding surface of the positive and loading plate by the chip to be packaged be bonded including：Using thickness
The chip to be packaged is bonded fixation by uniform temporary adhesion film with the interim bonding surface.
Preferably, in above-mentioned method for packing, after forming the plastic packaging layer, before the interconnection architecture is formed, removal
The loading plate；
Or, after the interconnection architecture is formed, before cutting technique is carried out, remove the loading plate.
Preferably, in above-mentioned method for packing, the second surface in the plastic packaging layer is formed and the core to be packaged
The corresponding interconnection architecture of piece includes：
Form patterned metallic circuit layer in the second surface of the plastic packaging layer, the metallic circuit layer include it is multiple with
The one-to-one interconnection architecture of chip to be packaged；
Solder-bump is formed on the interconnection architecture surface, the solder-bump is used to connect with the external circuit.
Preferably, in above-mentioned method for packing, the second surface in the plastic packaging layer forms patterned metal wire
Road floor includes：
Form the metallic circuit layer for the second surface for covering the plastic packaging layer；
Processing is performed etching to the metallic circuit layer, to pattern the metallic circuit layer, formation is multiple to be treated with described
Encapsulate the one-to-one interconnection architecture of chip；
Preferably, in above-mentioned method for packing, the second surface in the plastic packaging layer forms patterned metal wire
Road floor includes：
Using the mask plate of preset pattern structure, the patterned metallic circuit layer is formed by evaporation process.
Preferably, in above-mentioned method for packing, before cutting technique is carried out, formed through the plastic packaging layer first surface
And the through hole of second surface；
One end of the weld pad and metal wire is connected, the other end of the metal wire passes through the through hole and the interconnection
Structure connects；
Wherein, in a first direction, the through hole is not overlapped with the chip to be packaged；On the first direction perpendicular to
The first surface and second surface of the plastic packaging layer.
Preferably, in above-mentioned method for packing, the back side of the chip to be packaged has the pad being connected with the weld pad；
Before the metallic circuit layer is formed, through hole is formed in the second surface of the plastic packaging layer；In a first direction,
The through hole is set with the pad face, for exposing the pad；
Wherein, the interconnection architecture is connected by the through hole with the pad；Perpendicular to described on the first direction
The first surface and second surface of plastic packaging layer.
Preferably, in above-mentioned method for packing, before the metallic circuit layer is formed, formed through the plastic packaging layer
First through hole；
The second through hole through the chip front side to be packaged and the back side is formed in the first through hole, in first party
Upwards, second through hole is set with the weld pad face, for exposing the weld pad；
Wherein, the metallic circuit layer is connected by the first through hole and the through hole with the weld pad；Described
Perpendicular to the first surface and second surface of the plastic packaging layer on one direction.
Preferably, in above-mentioned method for packing, before cutting technique is carried out, further include：
The insulating protective layer for covering the metallic circuit layer is formed, the surface of the insulating protective layer has for setting
State the opening of solder-bump.
Preferably, in above-mentioned method for packing, the chip to be packaged is image sensing chip；
After the cutting technique is completed, the method for packing further includes：
Using the plastic packaging layer of the encapsulating structure as substrate, in the periphery fixing bracket of the first surface of the plastic packaging layer；
Transparent cover plate is set on the bracket.
The present invention also provides a kind of encapsulating structure of chip, the encapsulating structure includes：Plastic packaging layer, the plastic packaging layer tool
There are opposite first surface and second surface；
At least one chip to be packaged in the plastic packaging layer, the chip to be packaged have opposite front and
The back side, front have sensing unit and the weld pad being connected with the sensing unit；
Positioned at the second surface of plastic packaging layer interconnection architecture corresponding with the chip to be packaged, the weld pad passes through institute
Interconnection architecture is stated to be connected with external circuit；
Wherein, the plastic packaging layer has opposite first surface and second surface, and the chip to be packaged is located at described
In plastic packaging layer, and its positive is flushed with the first surface；.
Preferably, in above-mentioned encapsulating structure, there are multiple chips to be packaged in the plastic packaging layer；It is treated described in all
The front of encapsulation chip is generally aligned in the same plane, and is flushed with the first surface；Each chip to be packaged corresponds to an institute
State interconnection architecture.
Preferably, in above-mentioned encapsulating structure, the plastic packaging layer includes：First plastic packaging layer and the second plastic packaging layer；
The first plastic packaging layer has the multiple and one-to-one groove of chip to be packaged, and the depth of the groove is small
In the thickness of the chip to be packaged, the back side and the bottom of the groove of the chip to be packaged are oppositely arranged；Described first
Plastic packaging layer is the second surface away from the surface of the chip to be packaged；
The second plastic packaging layer covers the first plastic packaging layer towards a side surface of the chip to be packaged, and described second
Plastic packaging layer is the first surface away from a side surface of the first plastic packaging layer.
Preferably, in above-mentioned encapsulating structure, the interconnection architecture is located at same patterned metallic circuit layer；
The interconnection architecture surface has solder-bump, and the solder-bump is used to connect with the external circuit.
Preferably, in above-mentioned encapsulating structure, the plastic packaging layer has through the first surface and second table
The through hole in face；
One end of the weld pad and one end of metal wire connect, the other end of the metal wire by the through hole with it is described
Interconnection architecture connects；
Wherein, in a first direction, the through hole is not overlapped with the chip to be packaged；On the first direction perpendicular to
The first surface and second surface of the plastic packaging layer.
Preferably, in above-mentioned encapsulating structure, the back side of the chip to be packaged has the pad being connected with the weld pad；
The second surface of the plastic packaging layer has through hole；In a first direction, the through hole is set with the pad face,
For exposing the pad；
Wherein, the interconnection architecture is connected by the through hole with the pad；Perpendicular to described on the first direction
The first surface and second surface of plastic packaging layer.
Preferably, in above-mentioned encapsulating structure, the plastic packaging layer has first through hole；
The back side of the chip to be packaged have with one-to-one second through hole of the first through hole, in a first direction
On, second through hole is set with the weld pad face, for exposing the weld pad；
Wherein, the metallic circuit layer is connected by the through hole with the weld pad；Perpendicular to institute on the first direction
State the first surface and second surface of plastic packaging layer.
Preferably, in above-mentioned encapsulating structure, the interconnection architecture surface also has insulating protective layer, the insulation protection
The surface of layer has the opening for setting the solder-bump.
Preferably, in above-mentioned encapsulating structure, the chip to be packaged is image sensing chip.
Preferably, in above-mentioned encapsulating structure, the first surface of the plastic packaging layer is additionally provided with stent；
Transparent cover plate is installed on the stent.
By foregoing description, the method for packing and encapsulating structure of a kind of chip that technical solution of the present invention provides
In, chip to be packaged is located in plastic packaging layer, and the front of the chip to be packaged is flushed with the first surface of plastic packaging layer, for being formed
The plastic packaging material of plastic packaging layer has preferable plasticity before curing, can form the preferable first surface of planarization and the second table
Face ensure that the reliability of encapsulating structure.
Description of the drawings
It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of existing structure diagram of multichip packaging structure；
Fig. 2 a- Fig. 5 c are a kind of flow diagram of the method for packing of chip provided in an embodiment of the present invention；
Fig. 6-Figure 13 is a kind of flow diagram of the forming method of plastic packaging layer provided in an embodiment of the present invention；
Figure 14-Figure 15 is the flow diagram of the forming method of another plastic packaging layer provided in an embodiment of the present invention；
Figure 16-Figure 17 is the flow diagram of the method for packing of another chip provided in an embodiment of the present invention；
Figure 18-Figure 19 is the flow diagram of the method for packing of another chip provided in an embodiment of the present invention；
Figure 20 is a kind of encapsulating structure schematic diagram provided in an embodiment of the present invention；
Figure 21 is another encapsulating structure schematic diagram provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment belongs to the scope of protection of the invention.
Generally, the encapsulating structure to be formed is packaged to chip as shown in Figure 1, Fig. 1 is a kind of encapsulation knot of multi-chip
The structure diagram of structure, in the chip-packaging structure, chip 11 is adhesively fixed by glue-line 12 and circuit board 13, and circuit board 13 is carried on the back
One side surface of off-chip piece 11 has metallic circuit and the solder-bump 14 connected with metallic circuit, for connecting with external circuit
It connects.Chip 11 is connected by routing technique with metallic circuit.The side surface that circuit board 13 is provided with chip 11 is provided with encirclement
The stent 15 of chip 11 is provided with transparent cover plate 16 on stent 15.When chip 11 is image sensing chip, the transparent cover plate
16 be lens element.
In Fig. 1 illustrated embodiments, using circuit board 13 as the loading plate of chip 11, bonded by glue-line 12 and chip 11
It is fixed, it can not ensure the planarization of chip-packaging structure.And during multiple 11 integral packagings of chip, it can not ensure each chip 11
High flatness.When setting stent 15, since stent 15 needs to connect separately through glue-line and circuit board 13, can not accurately control
Stent 15 processed is compared with 11 height and position of chip, for image sensing chip, can not accurately control the focal length of lens element.It is above-mentioned
The reliability for the encapsulating structure that problem can result in is poor.
To solve the above-mentioned problems, an embodiment of the present invention provides the encapsulating structure and method for packing of a kind of chip, lead to
It crosses plastic packaging layer to be packaged chip, there is the characteristic of preferable plasticity so that the encapsulation of formation before curing using plastic packaging material
Structure has preferable planarization, ensures the reliability of encapsulating structure.Meanwhile the plastic packaging layer tool formed after being cured using plastic packaging material
There is preferable mechanical strength, bearing substrate can be multiplexed with, for carrying support member, such as carrying bracket, by described
The components such as stent installation cover board.When setting the support member by the plastic packaging layer, since the plastic packaging layer has preferably
Planarization, therefore height of the support member compared with the chip can be accurately controlled, be effectively ensured plastic package structure can
By property.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
An embodiment of the present invention provides a kind of method for packing of chip, the method for packing includes：
Step S1：At least one chip to be packaged is provided.
The chip to be packaged have opposite front and the back side, front have sensing unit and with the sensing
The weld pad of unit connection.
Step S2：Form the plastic packaging layer at the back side for covering the chip to be packaged.
The plastic packaging layer has opposite first surface and second surface, and the chip to be packaged is located at the plastic packaging layer
It is interior, and its positive is flushed with the first surface.
Step S3：Interconnection architecture corresponding with the chip to be packaged is formed in the second surface of the plastic packaging layer；It is described
Weld pad is connected by the interconnection architecture with external circuit.
Method for packing described in the embodiment of the present invention is directly packaged chip protection by plastic packaging layer, and plastic packaging layer has
Opposite first surface and the second plane.First surface and second surface are plane, and parallel.Chip to be packaged is just
Face and first surface flush.
The plastic packaging layer can be packaged protection to chip to be packaged.Moreover, the plastic packaging layer surface directly sets institute
Interconnection architecture is stated, is connected with the weld pad, at this point, the plastic packaging layer is multiplexed with circuit board, in order to chip to be packaged and outside
Circuit connects.In this way, chip to be fixed on to the conventional method of circuit board with respect to glue-line, plastic packaging layer have both circuit board and
The effect of glue-line, enormously simplifies encapsulating structure.And plastic packaging layer has larger mechanical strength, it can be real by relatively thin thickness
Existing larger mechanical strength substantially reduces the thickness of encapsulating structure.
Meanwhile chip is packaged by plastic packaging layer, there is the characteristic of preferable plasticity before curing using plastic packaging material,
So that the encapsulating structure formed has preferable planarization, ensure the reliability of encapsulating structure.Meanwhile after being cured using plastic packaging material
The plastic packaging layer of formation has preferable mechanical strength, can be multiplexed with bearing substrate, for carrying support member, is such as used to carry
Stent installs the components such as cover board by the stent.When setting the support member by the plastic packaging layer, due to the modeling
Sealing has preferable planarization, therefore can accurately control height of the support member compared with the chip, is effectively ensured
The reliability of plastic package structure.
When being packaged simultaneously to multiple chips, multiple chips to be packaged, all chips to be packaged are provided
Front be generally aligned in the same plane, flushed with the first surface；Each chip to be packaged corresponds to a mutual connection
Structure.At this point, the method for packing further includes：By cutting technique, the plastic packaging layer is divided into multiple encapsulating structures, the envelope
Assembling structure includes at least one chip to be packaged and its corresponding interconnection architecture.
When being packaged simultaneously to multiple chips, the method for packing is as shown in Fig. 2-Fig. 5 a.
Show with reference to figure 2- Fig. 5 c, Fig. 2 a- Fig. 5 c for a kind of flow of the method for packing of chip provided in an embodiment of the present invention
It is intended to, which includes：
Step S11：Multiple chips to be packaged are provided.
As shown in Figure 2 a and 2 b, Fig. 2 a are the sectional drawing of the chip to be packaged to the structure of the chip to be packaged, are schemed
2b is the positive top view of the chip to be packaged, and shown chip 20 to be packaged has with opposite front 201 and the back side
202, front 201 has sensing unit 203 and the weld pad 204 being connected with the sensing unit 203.
In mode shown in Fig. 2 a and Fig. 2 b, multiple weld pads 204 are segmented into two row, and sensing unit 203 is located at two row
Between weld pad 204.In other embodiment, weld pad 204 can also be uniformly arranged on sensing unit 203 surrounding or
Multiple weld pads 204 are arranged on to the same side of sensing unit 203.
The number of the chip 20 to be packaged is not limited in the embodiment of the present invention, it can be according to the design of encapsulating structure
Parameter specifically sets the number of the chip to be packaged 20.20 array arrangement of chip to be packaged.
Step S12：As shown in figure 3, form the plastic packaging layer 21 at the back side for covering the chip 20 to be packaged.
The front of all chips 20 to be packaged is generally aligned in the same plane；The plastic packaging layer 21 has opposite first surface
211 and second surface 212, the chip 20 to be packaged be located in the plastic packaging layer 21, and its front 201 with first table
Face 211 flushes.There is gap, in order to subsequently carry out cutting technique between adjacent chip to be packaged 20.
Step S13：As shown in figure 4, the formation of second surface 212 in the plastic packaging layer 21 is right with the chip 20 to be packaged
The interconnection architecture 22 answered.
The weld pad 204 is connected by the interconnection architecture 22 with external circuit.Plastic packaging layer 21 has through hole 41, passes through position
In conducting wire connection weld pad 204 and interconnection architecture 22 in through hole 41, weld pad 204 and interconnection can also be electrically connected by other means
Structure 22.
In the step, formed and the 20 corresponding interconnection of chip to be packaged in the second surface 212 of the plastic packaging layer 21
Structure 22, specifically includes：Patterned metallic circuit layer, the metal wire are formed in the second surface 212 of the plastic packaging layer 21
Road floor includes the multiple and 20 one-to-one interconnection architecture 22 of chip to be packaged；It is formed and welded on 22 surface of interconnection architecture
Protrusion 25 is connect, the solder-bump 25 is used to connect with the external circuit.
Include specifically, the second surface 212 in the plastic packaging layer 21 forms patterned metallic circuit layer：It is formed
Cover the metallic circuit layer of the second surface of the plastic packaging layer；Processing is performed etching to the metallic circuit layer, to pattern
Metallic circuit layer is stated, forms the multiple and one-to-one interconnection architecture of chip to be packaged；It is alternatively, described in the plastic packaging layer
21 second surface 212, which forms patterned metallic circuit layer, to be included：Using the mask plate of preset pattern structure, by the way that work is deposited
Skill forms the patterned metallic circuit layer.
Optionally, before cutting technique is carried out, further include：The insulating protective layer for covering the metallic circuit layer is formed,
The surface of the insulating protective layer has the opening for setting the solder-bump.The insulating protective layer not shown in Fig. 4.
Step S14：As shown in figure 5 a and 5b, by cutting technique, the plastic packaging layer 22 is divided into multiple encapsulation and is tied
Structure.
The encapsulating structure includes to wrap with multiple chips 20 to be packaged and its corresponding interconnection architecture 22
Include a chip 20 to be packaged and its corresponding interconnection architecture 22.When the encapsulating structure has multiple cores to be packaged
During piece 20, the plurality of 20 arrangement mode of chip to be packaged can arbitrarily be set, the multiple to be packaged in such as encapsulating structure
Chip 20 can be with array arrangement.The embodiment of the present invention does not limit the number of the chip 20 to be packaged.
In mode shown in Fig. 5 a and Fig. 5 b, each encapsulating structure has 3 chips 20 to be packaged, and three to be packaged
Chip 20 is located at same straight line.In other modes, as shown in Figure 5 c, three chips 20 to be packaged can also be located at one three respectively
Three angular vertex.
In method for packing described in the embodiment of the present invention, the modeling for forming the back side for covering all chips 20 to be packaged
For the method for sealing 21 as shown in Fig. 6-Figure 13, Fig. 6-Figure 13 is a kind of forming method of plastic packaging layer provided in an embodiment of the present invention
Flow diagram, this method include：
Step S21：As shown in fig. 6, providing a loading plate 23, the loading plate has to carry the chip to be packaged
20 interim bonding surface 231.
In the embodiment, the interim bonding surface 231 of the loading plate 23 has multiple carrying grooves 232；One institute
It states and carries groove 232 for placing a chip 20 to be packaged；There is gap between the two neighboring carrying groove 23
233；The depth of the carrying groove 232 is identical, and less than the thickness of the chip 20 to be packaged.
The loading plate 23 can be glass plate or plastic plate.The tool of loading plate 23 is described interim there are one plane
Bonding surface 231.It is different according to the material of the loading plate 23, may be employed Shooting Technique formed the carrying groove 232 or
It is that the carrying groove 232 is formed by etching technics.
Step S22：As shown in fig. 7, the front 201 of the chip 20 to be packaged is bonded with the interim of loading plate 23
Surface 231 is bonded.
It is described by the chip 20 to be packaged in the step during loading plate 23 for having and carrying groove 232 using above-mentioned
Front 201 be bonded with the interim bonding surface 231 of the loading plate 23 including：It is put respectively in each carrying groove 232
A chip 20 to be packaged is put, the front 201 of the chip 20 to be packaged is opposite with the bottom of the carrying groove 232 to be set
It puts.Since the depth for carrying groove 232 is identical, and the front of chip to be packaged 20 and the bottom of corresponding carrying groove 232 are seamless
Contact, in this way, the front 201 of each chip to be packaged 20 can be caused to be generally aligned in the same plane.
Step S23：As shown in Fig. 8-Figure 13, the plastic packaging layer 21 is formed, the plastic packaging layer 21 covers the core to be packaged
The interim bonding surface 231 of piece 20 and the loading plate 23.
During the loading plate 23 for having and carrying groove 232 using above-mentioned, in the step, the bag for forming the plastic packaging layer 21
It includes：
First, as shown in figure 8, forming the first plastic packaging layer 21a.The first plastic packaging layer 21a covers the chip to be packaged
20 and the interim bonding surface 231 of the loading plate 23.The first plastic packaging layer 21a deviates from the table of the chip 20 to be packaged
Face is the second surface 212.
Then, as shown in figure 9, removing the loading plate 23.
For another example shown in Figure 10-Figure 13, the front 201 of the chip 20 to be packaged is exposed in the first plastic packaging layer 21a
One side surface forms the second plastic packaging layer 21b.The side surface that the second plastic packaging layer 21b deviates from the first plastic packaging layer 21a is
The first surface 211.In this embodiment, it is described to expose the chip 20 to be packaged in the first plastic packaging layer 21a
The method that one side surface in front 201 forms the second plastic packaging layer 21b includes：First, as shown in Figure 10 so that the core to be packaged
The front 201 of piece 20 forms protective layer 24 upward, in the front 201 of the chip 20 to be packaged；Then, as shown in figure 11, shape
Into the second plastic packaging layer 21b, the thickness of the second plastic packaging layer 21b exposes first modeling more than the chip 20 to be packaged
The thickness of sealing 21a；Again as shown in figure 12, the protective layer 24 is removed, finally, as shown in figure 13, to the second plastic packaging layer
21b is thinned away from a side surface of the first plastic packaging layer 21a, so that the surface and the chip 20 to be packaged are just
Face 201 flushes.
In Fig. 6-Figure 13 illustrated embodiments, loading plate 23, which has, carries groove 232.In other embodiments, also
Can the plastic packaging layer 21, as shown in Figure 14-Figure 15, Figure 14-figure directly be formed using the loading plate 23 of slab construction
15 be the flow diagram of the forming method of another plastic packaging layer provided in an embodiment of the present invention, is used in this method such as Figure 14 institutes
The loading plate 23 for the slab construction shown, the interim bonding surface 231 of the loading plate 23 is plane.In this way, as shown in figure 15, it is described
The front 201 of the chip 20 to be packaged is bonded with the interim bonding surface 231 of the loading plate 23 including：It is equal using thickness
The chip 20 to be packaged is bonded fixation by even temporary adhesion film 25 with the interim bonding surface 231.Which is using thick
It spends uniform temporary adhesion film unification and the chip 20 to be packaged is bonded and fixed at the interim bonding surface 231, due to
The interim bonding surface 231 is plane, and chip 20 to be packaged is adhesively fixed using same layer adhesive film 25, therefore can be ensured each
The front 201 of a chip 20 to be packaged is located at same surface.
When the interim bonding surface 231 is plane, optionally, the method for packing is forming the plastic packaging layer 21
Afterwards, before the interconnection architecture 22 is formed, the loading plate 23 is removed；Alternatively, after the interconnection architecture 22 is formed,
Before carrying out cutting technique, the loading plate 23 is removed.
In the above-described embodiment, the weld pad 204 of each chip 20 to be packaged passes through routing technique and corresponding institute
State interconnection architecture connection.Specifically, before cutting technique is carried out, formed through 21 first surface 211 of plastic packaging layer and
The through hole 41 of second surface 212 can prepare the through hole 41 by laser boring technique；By the weld pad 204 and metal wire
42 one end connection, the other end of the metal wire 42 are connected by the through hole 41 with the interconnection architecture 22；Wherein,
On one direction, the through hole 41 is not overlapped with the chip 20 to be packaged；Perpendicular to the plastic packaging layer 21 on the first direction
First surface 211 and second surface 212.
In another embodiment, the interconnection architecture 22 can also be carried on the back directly by through hole and the chip 20 to be packaged
The pad connection in face, and then be connected by the pad with the weld pad.Specifically, as shown in Figure 16-Figure 17, Figure 16-Figure 17
For the flow diagram of the method for packing of another chip provided in an embodiment of the present invention, the back side of the chip 20 to be packaged
202 have the pad 162 being connected with the weld pad 204；Before the metallic circuit layer is formed, the of the plastic packaging layer 21
Two surfaces 212 form through hole 161, and the through hole 161 can be prepared by laser boring technique；In a first direction, it is described logical
Hole 161 is set with the pad face, for exposing the pad 162；Wherein, the interconnection architecture 22 passes through the through hole
161 are connected with the pad 162；Perpendicular to 211 and second table of first surface of the plastic packaging layer 21 on the first direction
Face 212.In which, it is necessary to back side of the chip to be packaged 20 forms back side interconnection architecture by TSV techniques and (does not show in figure
Go out), the back side 202 of chip 20 to be packaged has through hole at this time, which is located at the weld pad in its front 201 for exposing, so as to
It is connected in pad 162 by back side interconnection architecture and weld pad 204.In which, after cutting, encapsulating structure such as Figure 17 institutes of formation
Show.As above-mentioned, 20 numbers of chip to be packaged do not limit in the encapsulating structure formed after cutting, can be one or multiple.
The back side interconnection architecture includes：Its back side 202 and the insulating layer of the through-hole side wall are covered, it is logical that insulating layer corresponds to this
The region in bottom hole portion has opening for exposing weld pad；Cover the insulating layer and the wiring layer again of the via bottoms；Covering
The solder mask of the wiring layer again, the solder mask be located at region outside the through hole have expose described in again wiring layer open
Mouthful, which is used to set the pad 161.The specific level and structure of the back side interconnection architecture not shown in Figure 16, can
It is formed with the TSV techniques with reference to traditional die, details are not described herein.In which, each interconnection architecture 22 is at least through one
Through hole 161 and the pad 162 at corresponding 20 back side 202 of chip to be packaged connect, and each through hole 161 corresponds to a pad 162.
In another embodiment, the interconnection architecture can also by run through the plastic packaging layer 21 first through hole and
The second through hole through the chip is connected with the weld pad.Specifically, as shown in Figure 18-Figure 19, Figure 18-Figure 19 is the present invention
The flow diagram of the method for packing for another chip that embodiment provides, before the metallic circuit layer is formed, formation is passed through
Wear the first through hole 171 of the plastic packaging layer 21；It is formed in the first through hole 171 through 20 front of chip to be packaged
201 and second through hole 172 at the back side 202, in a first direction, second through hole 172 is set with the weld pad face, is used
In the exposing weld pad；Wherein, the metallic circuit layer passes through the first through hole 171 and the through hole 172 and the weldering
Pad connection；Perpendicular to the first surface 211 of the plastic packaging layer 21 and second surface 212 on the first direction.In order to avoid
It is short-circuit between the substrate of the interconnection architecture 22 and the chip to be packaged 20, it is also needed to before the interconnection architecture 22 is formed
The insulating layer for covering 172 side wall of the second through hole is formed, which exposes the weld pad of 172 bottom of the second through hole, should
Insulating layer can also cover the side wall of first through hole 171 and the second surface 212.In which, after cutting, the envelope of formation
Assembling structure is as shown in figure 19.
In which, 171 and second through hole 172 of first through hole corresponds, and is formed with described 21 mask plate of plastic packaging layer
Second through hole 172.Since chip 20 to be packaged by TSV techniques without forming back side interconnection architecture, manufacture craft is simple,
It is at low cost；Since the area of encapsulating structure by routing technique, need not be reduced.
In method for packing described in the embodiment of the present invention, the chip 20 to be packaged is image sensing chip；Complete institute
After stating cutting technique, the method for packing further includes：It is substrate with the plastic packaging layer 21 of the encapsulating structure, in the plastic packaging layer
First surface periphery fixing bracket；Transparent cover plate is set on the bracket, and the transparent cover plate can be lens.Due to
The front 201 of the chip to be packaged 20 is generally aligned in the same plane, can be to avoid described to be packaged when setting the transparent cover plate
Height tolerance between chip 20 and the transparent cover plate.At this point, when the encapsulating structure tool there are one chip to be packaged when, thoroughly
Bright cover board individually corresponds to a chip to be packaged, and when the encapsulating structure has multiple chips to be packaged, transparent cover plate is right simultaneously
Answer the multiple chip to be packaged.
In method for packing described in the embodiment of the present invention, multiple chips 20 to be packaged are located in same plastic packaging layer 21, described to treat
The front of encapsulation chip 20 is flushed with the first surface 211 of plastic packaging layer 21, in this way, default loading plate 23 may be employed for shape
Into the plastic packaging layer 21 so that the first surface 211 of the plastic packaging layer 21 has preferable planarization, so that each wait to seal
The front 201 of cartridge chip 20 is generally aligned in the same plane, and ensure that the front 201 of multiple chips 20 to be packaged in same encapsulating structure has
Have and preferably flush characteristic, ensure that the reliability of encapsulating structure.Since the capsulation material for preparing the plastic packaging layer 21 is curing
There is larger hardness later, on the one hand, protection can be packaged to chip 20 to be packaged, on the other hand, base can be used as
Plate sets other support members, such as the stent for setting transparent cover plate.
Based on above-mentioned method for packing, another embodiment of the present invention additionally provides a kind of encapsulating structure of chip, the encapsulation
Structure includes：Plastic packaging layer, the plastic packaging layer have opposite first surface and second surface；In the plastic packaging layer extremely
A few chip to be packaged, the chip to be packaged have opposite a front and the back side, front have sensing unit and
The weld pad being connected with the sensing unit；Positioned at the mutual connection corresponding with the chip to be packaged of the second surface of the plastic packaging layer
Structure, the weld pad are connected by the interconnection architecture with external circuit；Wherein, the plastic packaging layer have opposite first surface with
And second surface, the chip to be packaged are located in the plastic packaging layer, and its positive is flushed with the first surface.
When encapsulating structure tool is there are one during chip to be packaged, the seal structure can be as shown in figure 20, and Figure 20 is this
A kind of encapsulating structure schematic diagram that inventive embodiments provide.Chip 20 to be packaged is located in plastic packaging layer 21.Chip 20 to be packaged has
There are whole face 201 and the back side 202, front 201 has weld pad 204 and sensing unit (not shown), and chip 20 to be packaged can
With with reference to above-described embodiment, details are not described herein.Plastic packaging layer has first surface 211 and second surface 212, and the back side 212 has
Have and 20 corresponding interconnection architecture 22 of chip to be packaged.Plastic packaging layer 21 has through hole 41, and metal wire 42 is provided in through hole 41, uses
In connection interconnection architecture 22 and weld pad 204, other modes connection interconnection architecture 22 and weld pad 204 can also be used, including not office
It is limited to mode described in above-described embodiment.
In encapsulating structure described in the embodiment of the present invention, when the encapsulating structure has multiple chips to be packaged, the modeling
There are multiple chips to be packaged in sealing；The front of all chips to be packaged is generally aligned in the same plane, with described
One surface flushes；Each chip to be packaged corresponds to an interconnection architecture.At this point, encapsulating structure can be such as Figure 21 institutes
Show.
With reference to figure 21, Figure 21 is another encapsulating structure schematic diagram provided in an embodiment of the present invention, which includes：
Plastic packaging layer 21, the plastic packaging layer 21 have opposite first surface 211 and second surface 212；In the plastic packaging layer 21
Multiple chips 20 to be packaged, the chip 20 to be packaged have opposite front 201 and the back side 212, front 201 has
Sensing unit and the weld pad being connected with the sensing unit；The front 201 of all chips 20 to be packaged is located at same flat
Face, and its positive is flushed with the first surface 211；Positioned at multiple interconnection architectures of the second surface 212 of the plastic packaging layer 21
22, the interconnection architecture 22 is corresponded with the chip 20 to be packaged；The weld pad passes through the interconnection architecture 22 and outside
Circuit connects.The structure of the chip to be packaged 20 may be referred to structure described in above-described embodiment, and details are not described herein.
In a kind of mode, the plastic packaging layer 21 includes：First plastic packaging layer and the second plastic packaging layer；The first plastic packaging layer tool
There is the multiple and one-to-one groove of chip to be packaged, the depth of the groove is less than the thickness of the chip to be packaged,
The back side and the bottom of the groove of the chip to be packaged are oppositely arranged；The first plastic packaging layer deviates from the chip to be packaged
Surface be the second surface；The second plastic packaging layer covers the first plastic packaging layer towards the one side of the chip to be packaged
Surface, the second plastic packaging layer are the first surface away from a side surface of the first plastic packaging layer.Another way, it is described
Plastic packaging layer 21 is the single layer structure formed using the loading plate of a slab construction.The concrete structure of the two ways and formation work
Skill may be referred to above-described embodiment, and details are not described herein.
In encapsulating structure described in the embodiment of the present invention, the interconnection architecture 22 is located at same patterned metallic circuit
Layer；22 surface of interconnection architecture has solder-bump 25, and convex 25 of the welding is used to connect with the external circuit.It is described
The pad in 20 front 201 of chip to be packaged is connected with the interconnection architecture 22, and then passes through the solder-bump 25 and external electrical
Road connects.Optionally, 22 surface of interconnection architecture also has insulating protective layer, and the surface of the insulating protective layer, which has, to be used for
The opening of the solder-bump 25 is set.The insulating protective layer not shown in Figure 21.
In Figure 21 illustrated embodiments, the plastic packaging layer 21 has through the first surface 211 and described second
The through hole 41 on surface 212；One end of the weld pad is connected with one end of metal wire 42, and the other end of the metal wire 42 passes through institute
Through hole 41 is stated to be connected with the interconnection architecture 22；Wherein, in a first direction, the through hole 41 and the chip 20 to be packaged be not
It is overlapping；Perpendicular to the first surface 211 of the plastic packaging layer 21 and second surface 212 on the first direction.
Optionally, the chip to be packaged 22 is image sensing chip.The first surface 211 of the plastic packaging layer 21 is also set up
There is stent 181；Transparent cover plate 182 is installed on the stent 181.The transparent cover plate can be transparent lens, for institute
The light that stating influences sensing chip transmitting or gather is regulated and controled.
As described in above-described embodiment, in another embodiment, the back side 212 of the chip 20 to be packaged have with it is described
The pad of weld pad connection；The second surface 212 of the plastic packaging layer 21 has through hole；In a first direction, the through hole with it is described
Pad face is set, for exposing the pad；Wherein, the interconnection architecture is connected by the through hole with the pad.It should
Encapsulating structure described in mode may be referred to shown in Figure 17, and details are not described herein.Electric connection structure may be referred to above-mentioned method for packing
Corresponding embodiment, details are not described herein.
As described in above-described embodiment, in another embodiment, the plastic packaging layer 21 has first through hole；It is described to be packaged
The back side 202 of chip 20 has and one-to-one second through hole of the first through hole, in a first direction, second through hole
It is set with the weld pad face, for exposing the weld pad；Wherein, the metallic circuit layer passes through the through hole and the weld pad
Connection.Encapsulating structure described in which may be referred to shown in Figure 19, and details are not described herein.Electric connection structure may be referred to above-mentioned envelope
Dress method corresponds to embodiment, and details are not described herein.
By foregoing description, in encapsulating structure described in the embodiment of the present invention, multiple chips 20 to be packaged are located at same
In plastic packaging layer 21, the front of the chip 20 to be packaged is flushed with the first surface 211 of plastic packaging layer 21, in this way, may be employed pre-
If loading plate 23 for forming the plastic packaging layer 21 so that the first surface 211 of the plastic packaging layer 21 has preferable smooth
Property so that the front 201 of each chip to be packaged 20 is generally aligned in the same plane, ensure that and multiple in same encapsulating structure wait to seal
The front 201 of cartridge chip 20, which has, preferably flushes characteristic, ensure that the reliability of encapsulating structure.Due to preparing the plastic packaging layer
21 capsulation material has larger hardness after curing, on the one hand, can be packaged protection to chip 20 to be packaged, separately
On the one hand, other support members, such as the stent for setting transparent cover plate can be set as substrate.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.For encapsulation disclosed in embodiment
For structure, due to its with embodiment disclosed in method for packing it is corresponding, so description is fairly simple, related part is referring to envelope
Fill method part illustration.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications of these embodiments will be apparent for those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide scope caused.
Claims (26)
1. a kind of method for packing of chip, which is characterized in that the method for packing includes：
At least one chip to be packaged is provided, the chip to be packaged has opposite front and the back side, and front has sense
Answer unit and the weld pad being connected with the sensing unit；
The plastic packaging layer at the back side for covering the chip to be packaged is formed, the plastic packaging layer has opposite first surface and second
Surface, the chip to be packaged are located in the plastic packaging layer, and its positive is flushed with the first surface；
Interconnection architecture corresponding with the chip to be packaged is formed in the second surface of the plastic packaging layer；The weld pad passes through described
Interconnection architecture is connected with external circuit.
2. method for packing according to claim 1, which is characterized in that multiple chips to be packaged are provided, it is all described
The front of chip to be packaged is generally aligned in the same plane, and is flushed with the first surface；Each chip to be packaged corresponds to one
The interconnection architecture；
The method for packing further includes：
By cutting technique, the plastic packaging layer is divided into multiple encapsulating structures, the encapsulating structure includes at least one described
Chip to be packaged and its corresponding interconnection architecture.
3. method for packing according to claim 2, which is characterized in that described to form the back side for covering the chip to be packaged
Plastic packaging layer include：
A loading plate is provided, the loading plate has the interim bonding surface for carrying the chip to be packaged；
The interim bonding surface of the positive and loading plate of the chip to be packaged is bonded；
The plastic packaging layer is formed, the plastic packaging layer covers the interim bonding surface of the chip to be packaged and the loading plate.
4. method for packing according to claim 3, which is characterized in that the interim bonding surface of the loading plate has multiple
Carry groove；One groove that carries is for one chip to be packaged of placement；Between the two neighboring carrying groove
With gap；The depth of the carrying groove is identical, and less than the thickness of the chip to be packaged；
The interim bonding surface of the positive and loading plate by the chip to be packaged be bonded including：It described is taken each
It carries and places a chip to be packaged in groove respectively, the front of the chip to be packaged and the bottom phase of the carrying groove
To setting.
5. method for packing according to claim 4, which is characterized in that the formation plastic packaging layer includes：
The first plastic packaging layer is formed, the first plastic packaging layer covers the interim bonding table of the chip to be packaged and the loading plate
Face；The first plastic packaging layer is the second surface away from the surface of the chip to be packaged；
Remove the loading plate；
The positive side surface for exposing the chip to be packaged in the first plastic packaging layer forms the second plastic packaging layer；Described second
Plastic packaging layer is the first surface away from a side surface of the first plastic packaging layer.
6. method for packing according to claim 5, which is characterized in that described to wait to seal described in the first plastic packaging layer exposing
A positive side surface for cartridge chip, which forms the second plastic packaging layer, to be included：
Protective layer is formed in the front of the chip to be packaged；
The second plastic packaging layer is formed, the thickness of the second plastic packaging layer is more than the chip to be packaged and exposes first plastic packaging
The thickness of layer；
After removing the protective layer, the second plastic packaging layer is thinned away from a side surface of the first plastic packaging layer, with
So that the surface and the front flush of the chip to be packaged.
7. method for packing according to claim 3, which is characterized in that the interim bonding surface is plane；
The interim bonding surface of the positive and loading plate by the chip to be packaged be bonded including：It is uniform using thickness
Temporary adhesion film the chip to be packaged is bonded fixation with the interim bonding surface.
8. method for packing according to claim 7, which is characterized in that after forming the plastic packaging layer, forming the interconnection
Before structure, the loading plate is removed；
Or, after the interconnection architecture is formed, before cutting technique is carried out, remove the loading plate.
9. method for packing according to claim 2, which is characterized in that the second surface in the plastic packaging layer formed with
The corresponding interconnection architecture of the chip to be packaged includes：
Form patterned metallic circuit layer in the second surface of the plastic packaging layer, the metallic circuit layer include it is multiple with it is described
The one-to-one interconnection architecture of chip to be packaged；
Solder-bump is formed on the interconnection architecture surface, the solder-bump is used to connect with the external circuit.
10. method for packing according to claim 9, which is characterized in that the second surface in the plastic packaging layer is formed
Patterned metallic circuit layer includes：
Form the metallic circuit layer for the second surface for covering the plastic packaging layer；
Processing is performed etching to the metallic circuit layer, to pattern the metallic circuit layer, formed it is multiple with it is described to be packaged
The one-to-one interconnection architecture of chip.
11. method for packing according to claim 9, which is characterized in that the second surface in the plastic packaging layer is formed
Patterned metallic circuit layer includes：
Using the mask plate of preset pattern structure, the patterned metallic circuit layer is formed by evaporation process.
12. method for packing according to claim 9, which is characterized in that before cutting technique is carried out, formed through described
The through hole of plastic packaging layer first surface and second surface；
One end of the weld pad and metal wire is connected, the other end of the metal wire passes through the through hole and the interconnection architecture
Connection；
Wherein, in a first direction, the through hole is not overlapped with the chip to be packaged；Perpendicular to described on the first direction
The first surface and second surface of plastic packaging layer.
13. method for packing according to claim 9, which is characterized in that the back side of the chip to be packaged have with it is described
The pad of weld pad connection；
Before the metallic circuit layer is formed, through hole is formed in the second surface of the plastic packaging layer；In a first direction, it is described
Through hole is set with the pad face, for exposing the pad；
Wherein, the interconnection architecture is connected by the through hole with the pad；Perpendicular to the plastic packaging on the first direction
The first surface and second surface of layer.
14. method for packing according to claim 9, which is characterized in that before the metallic circuit layer is formed, formation is passed through
Wear the first through hole of the plastic packaging layer；
The second through hole through the chip front side to be packaged and the back side is formed in the first through hole, in a first direction
On, second through hole is set with the weld pad face, for exposing the weld pad；
Wherein, the metallic circuit layer is connected by the first through hole and the through hole with the weld pad；The first party
Upwards perpendicular to the first surface and second surface of the plastic packaging layer.
15. method for packing according to claim 9, which is characterized in that before cutting technique is carried out, further include：
The insulating protective layer for covering the metallic circuit layer is formed, the surface of the insulating protective layer has to set the weldering
Connect the opening of protrusion.
16. according to claim 1-5 any one of them method for packing, which is characterized in that the chip to be packaged passes for image
Sense chip；
After the cutting technique is completed, the method for packing further includes：
Using the plastic packaging layer of the encapsulating structure as substrate, in the periphery fixing bracket of the first surface of the plastic packaging layer；
Transparent cover plate is set on the bracket.
17. a kind of encapsulating structure of chip, which is characterized in that the encapsulating structure includes：Plastic packaging layer, the plastic packaging layer have phase
To first surface and second surface；
At least one chip to be packaged in the plastic packaging layer, the chip to be packaged have opposite front and the back of the body
Face, front have sensing unit and the weld pad being connected with the sensing unit；
Positioned at the second surface of plastic packaging layer interconnection architecture corresponding with the chip to be packaged, the weld pad pass through it is described mutually
It is coupled structure to be connected with external circuit；
Wherein, the plastic packaging layer has opposite first surface and second surface, and the chip to be packaged is located at the plastic packaging
In layer, and its positive is flushed with the first surface.
18. encapsulating structure according to claim 17, which is characterized in that have in the plastic packaging layer multiple described to be packaged
Chip；The front of all chips to be packaged is generally aligned in the same plane, and is flushed with the first surface；It is each described to be packaged
Chip corresponds to an interconnection architecture.
19. encapsulating structure according to claim 18, which is characterized in that the plastic packaging layer includes：First plastic packaging layer and
Second plastic packaging layer；
The first plastic packaging layer has the multiple and one-to-one groove of chip to be packaged, and the depth of the groove is less than institute
The thickness of chip to be packaged is stated, the back side and the bottom of the groove of the chip to be packaged are oppositely arranged；First plastic packaging
Layer is the second surface away from the surface of the chip to be packaged；
The second plastic packaging layer covers the first plastic packaging layer towards a side surface of the chip to be packaged, second plastic packaging
Layer is the first surface away from a side surface of the first plastic packaging layer.
20. encapsulating structure according to claim 18, which is characterized in that the interconnection architecture is located at same patterned gold
Belong to line layer；
The interconnection architecture surface has solder-bump, and the solder-bump is used to connect with the external circuit.
21. encapsulating structure according to claim 20, which is characterized in that the plastic packaging layer has through the first surface
And the through hole of the second surface；
One end of the weld pad and one end of metal wire connect, and the other end of the metal wire passes through the through hole and the interconnection
Structure connects；
Wherein, in a first direction, the through hole is not overlapped with the chip to be packaged；Perpendicular to described on the first direction
The first surface and second surface of plastic packaging layer.
22. encapsulating structure according to claim 20, which is characterized in that the back side of the chip to be packaged have with it is described
The pad of weld pad connection；
The second surface of the plastic packaging layer has through hole；In a first direction, the through hole is set with the pad face, is used for
Expose the pad；
Wherein, the interconnection architecture is connected by the through hole with the pad；Perpendicular to the plastic packaging on the first direction
The first surface and second surface of layer.
23. encapsulating structure according to claim 20, which is characterized in that the plastic packaging layer has first through hole；
The back side of the chip to be packaged has and one-to-one second through hole of the first through hole, in a first direction, institute
It states the second through hole to set with the weld pad face, for exposing the weld pad；
Wherein, the metallic circuit layer is connected by the through hole with the weld pad；Perpendicular to the modeling on the first direction
The first surface and second surface of sealing.
24. encapsulating structure according to claim 20, which is characterized in that the interconnection architecture surface also has insulation protection
Layer, the surface of the insulating protective layer have the opening for setting the solder-bump.
25. according to claim 17-24 any one of them encapsulating structures, which is characterized in that the chip to be packaged is image
Sensing chip.
26. encapsulating structure according to claim 24, which is characterized in that the first surface of the plastic packaging layer is additionally provided with branch
Frame；
Transparent cover plate is installed on the stent.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711346047.3A CN108091616A (en) | 2017-12-15 | 2017-12-15 | The method for packing and encapsulating structure of a kind of chip |
| US16/107,632 US10680033B2 (en) | 2017-12-15 | 2018-08-21 | Chip packaging method and chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711346047.3A CN108091616A (en) | 2017-12-15 | 2017-12-15 | The method for packing and encapsulating structure of a kind of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108091616A true CN108091616A (en) | 2018-05-29 |
Family
ID=62176502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711346047.3A Pending CN108091616A (en) | 2017-12-15 | 2017-12-15 | The method for packing and encapsulating structure of a kind of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108091616A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346534A (en) * | 2018-11-23 | 2019-02-15 | 中国电子科技集团公司第四十四研究所 | A kind of ceramic cartridge structure and its encapsulating structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232002A (en) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | Package with a marking structure and method of the same |
| CN101587847A (en) * | 2009-06-15 | 2009-11-25 | 美新半导体（无锡）有限公司 | Perpendicular interconnection multi-chip assembly encapsulation method by PCB substrate |
| CN105244359A (en) * | 2015-10-28 | 2016-01-13 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and packaging method |
| CN106449554A (en) * | 2016-12-06 | 2017-02-22 | 苏州源戍微电子科技有限公司 | Chip embedded packaging structure with sealed cavity and manufacturing method of structure |
| CN107146799A (en) * | 2017-05-11 | 2017-09-08 | 北京工业大学 | A kind of image chip encapsulating structure based on silicon substrate and preparation method thereof |
| CN207637778U (en) * | 2017-12-15 | 2018-07-20 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure of chip |
-
2017
- 2017-12-15 CN CN201711346047.3A patent/CN108091616A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232002A (en) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | Package with a marking structure and method of the same |
| CN101587847A (en) * | 2009-06-15 | 2009-11-25 | 美新半导体（无锡）有限公司 | Perpendicular interconnection multi-chip assembly encapsulation method by PCB substrate |
| CN105244359A (en) * | 2015-10-28 | 2016-01-13 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and packaging method |
| CN106449554A (en) * | 2016-12-06 | 2017-02-22 | 苏州源戍微电子科技有限公司 | Chip embedded packaging structure with sealed cavity and manufacturing method of structure |
| CN107146799A (en) * | 2017-05-11 | 2017-09-08 | 北京工业大学 | A kind of image chip encapsulating structure based on silicon substrate and preparation method thereof |
| CN207637778U (en) * | 2017-12-15 | 2018-07-20 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure of chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346534A (en) * | 2018-11-23 | 2019-02-15 | 中国电子科技集团公司第四十四研究所 | A kind of ceramic cartridge structure and its encapsulating structure |
| CN109346534B (en) * | 2018-11-23 | 2024-05-07 | 中国电子科技集团公司第四十四研究所 | Ceramic tube shell structure and packaging structure thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101193416B1 (en) | Three-dimensionally integrated semiconductor device and method for manufacturing the same | |
| CN100479135C (en) | Semiconductor device and a method for manufacturing of the same | |
| US6731010B2 (en) | Resin sealed stacked semiconductor packages with flat surfaces | |
| US8900993B2 (en) | Semiconductor device sealed in a resin section and method for manufacturing the same | |
| JPH06168980A (en) | Semiconductor-chip mounting method and substrate structure | |
| TW201401398A (en) | Substrate-less stackable package with wire-bond interconnect | |
| CN102956594A (en) | Power overlay structure with leadframe connections | |
| CN107046008A (en) | A kind of encapsulating structure and method for packing of fingerprint recognition chip | |
| CN104900627B (en) | Semiconductor device, the manufacturing method of semiconductor device, localization tool | |
| JP2015216263A (en) | Semiconductor device | |
| US9972560B2 (en) | Lead frame and semiconductor device | |
| CN108269766A (en) | A kind of ultra-thin packed substrate structure and its processing method | |
| CN109300882A (en) | Stack embedded packaging structure and preparation method thereof | |
| CN109509727B (en) | Semiconductor chip packaging method and packaging structure | |
| CN107958882A (en) | Encapsulating structure of chip and preparation method thereof | |
| CN208655635U (en) | Stack embedded packaging structure | |
| CN108091616A (en) | The method for packing and encapsulating structure of a kind of chip | |
| JP6631905B2 (en) | Multi-chip module and manufacturing method thereof | |
| TWI771901B (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN105845585A (en) | Chip packaging method and chip packaging structure | |
| TWI777337B (en) | Semiconductor device and method for manufacturing the same | |
| CN207637778U (en) | A kind of encapsulating structure of chip | |
| CN211150512U (en) | Fan-out type three-dimensional packaging structure | |
| CN107863363A (en) | Encapsulating structure of chip and preparation method thereof | |
| JP2010087321A (en) | Mems module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |