CN108074900B - 形成三维导线环的方法和使用该方法形成的导线环 - Google Patents

形成三维导线环的方法和使用该方法形成的导线环 Download PDF

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CN108074900B
CN108074900B CN201711095362.3A CN201711095362A CN108074900B CN 108074900 B CN108074900 B CN 108074900B CN 201711095362 A CN201711095362 A CN 201711095362A CN 108074900 B CN108074900 B CN 108074900B
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bond
kink
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CN108074900A (zh
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杰弗里·格里杰尔多
金定民
李俊浩
朴致宽
宋景耀
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ASMPT Singapore Pte Ltd
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Abstract

本发明提供了一种使用键合工具在第一键合点和第二键合点之间键合线的方法。它包括以下步骤:利用键合工具在第一键合点处形成第一键合,形成位于第一键合之上的第一扭结部,以及将键合工具移动到与第一扭结部间隔开预定距离的第一位置以从键合工具释放一定长度的线。该方法还包括将键合工具沿远离第二键合点的方向移动到在包括第一键合点、第二键合点和第一扭结部的平面外的第二位置的步骤。该方法还包括形成位于所述平面之外的第二扭结部,并且将键合工具移动到第二键合点以形成第二键合的步骤。

Description

形成三维导线环的方法和使用该方法形成的导线环
技术领域
本发明涉及一种在半导体器件上的不同键合点之间形成导线环的方法,例如在芯片上方和在板上的导线键合应用中形成导线环。本发明还涉及使用该方法形成的导线环。
背景技术
在某些半导体组装过程中,将半导体芯片放置在诸如引线框架基板的载体上。然后在半导体芯片和引线框架基板之间,各个芯片之间或引线框架基板上的不同点之间形成导线键合形式的电连接。金线、铝线、银线或铜线通常用于制造这些导线键合。
导线键合形成在要进行电连接的键合位置。通常,超声换能器用于产生超声能量以将无空气球(FAB)从毛细管劈刀 (capillary)附接到半导体芯片或载体上。先在第一键合位置形成球形键合(ball bond)。随后,毛细管劈刀在移动至第二键合位置的过程中持续馈送出键合线,而使得两位置间形成导线环(wire loop),然后在第二键合位置点形成针脚键合,该针脚键合通常位于载体上并与半导体芯片的周边相邻。这完成了将第一键合位置电连接至第二键合位置的导线键合过程。在完成所有必要的导线键合之后,用树脂材料封装芯片、导线环和载体以保护它们,从而制造出半导体封装件。
在半导体行业中希望持续开发更小的半导体封装件。由于导线环应该被完全封装在最终的半导体封装件中,并且导线环键合位置通常定位成邻近半导体芯片周边,所以封装件所占据的表面积将受到导线环键合位置的位置的影响。这意味着导线环键合位置越靠近芯片的周边,最终的半导体封装件会越小。
虽然期望将导线环键合位置定位成更靠近芯片的周边,但是在半导体封装件的设计期间,此能力受到各种因素的限制。一个限制因素是毛细管劈刀尺寸。在导线键合期间保持和分配键合线的毛细管劈刀的尺寸将物理地限制导线环键合位置可以接近芯片周边的程度。另一个限制因素是在键合线朝向第二键合位置弯曲的点处的键合线的颈部的弱点。导线环键合位置越靠近芯片的周边,形成导线环的键合线必须越多地向第二键合位置弯曲,导致键合线在颈部破裂的风险增加。如果键合线断裂,则得到的电连接将变得不可靠或不稳定。
图1a和1b分别是在芯片上导线键合应用中采用的常规导线环10的侧视图和俯视图。导线环10和半导体芯片20形成在基板30上。导线环10形成在半导体芯片20的顶表面上方。
导线环10在基板30上的第一键合点32处键合。导线环10基本沿垂直方向上延伸且其大致上平行于半导体芯片20的第一侧边,在第一扭结部12处朝向第二键合点34弯曲。导线环10的跨距部16从第一扭结部12基本沿水平方向上延伸并大致上平行于半导体芯片20的顶表面,在第二扭结部14处朝向第二键合点34弯曲。导线环10的倾斜部18在半导体芯片20的相对的第二侧边处从第二扭结部12开始,并且朝向第二键合点34倾斜,在该第二键合点34处倾斜部18键合到基板30。导线环10基本上位于垂直平面上。换句话说,第一键合点32、第一扭结部12、跨距部16、第二扭结部14和第二键合点34都基本上位于相同的垂直平面上。
从图1a所示的侧视图看,侧视水平跨长(horizontal span length)被定义为基本上平行于第一扭结部12和第二扭结部14之间的半导体芯片20的宽度的水平距离。从图1a所示的侧视图看,侧视倾斜部水平长度(horizontal slope length)被定义为第二扭结部14与第二键合点34之间的水平距离。将侧视水平跨长和侧视倾斜部水平长度表示为侧视总水平距离(包括两个长度的总和)的百分比通常更有意义。从图1a所示的侧视图看,第二扭结部垂直高度是第二扭结部14与第二键合点34之间的垂直距离。从图1a所示的侧视图看,侧视纵向着陆角是形成在基板30的表面或第二键合点34与倾斜部18之间形成的第二键合点34处的角度。
为了使封装件更小,则希望第一键合点32和第二键合点34尽可能靠近半导体芯片20的相应侧。因此,应当理解,侧视水平跨长百分比应尽可能高,优选地在侧视总水平距离的85%以上,并且侧视纵向着陆角应尽可能高,优选高于80度。然而,诸如在导线键合期间保持和分配键合线的毛细管劈刀的形状和尺寸的因素将导线环10的侧视纵向着陆角物理地限制在80度以下,并且将侧视水平跨长限制在侧视总水平距离的80%以下。
此外,第二扭结部垂直高度应足够高,以便提供距半导体芯片20的表面的足够的间隙。这是为了避免导线环10与半导体芯片20接触并引起短路。应当注意,通过增加第二扭结部垂直高度,侧视纵向着陆角也将增加(假设侧视水平跨长和侧视倾斜部水平长度保持恒定)。
发明内容
本发明的一个目的是寻求提供一种克服现有技术的局限性的改进的形成导线环的方法。
根据本发明的第一方面,提供了一种使用键合工具在第一键合点和第二键合点之间键合线的方法,包括以下步骤:利用所述键合工具在所述第一键合点处形成第一键合;形成位于所述第一键合之上的第一扭结部;将所述键合工具移动到与所述第一扭结部间隔开预定距离的第一位置以从所述键合工具释放一定长度的线;将所述键合工具沿远离第二键合点的方向移动到在包括所述第一键合点、所述第二键合点和所述第一扭结部的平面外的第二位置;形成位于所述平面外的第二扭结部;以及将所述键合工具移动到所述第二键合点以形成第二键合。
根据本发明的第二方面,提供了一种键合在第一键合点和第二键合点之间的导线环,包括:位于所述第一键合点之上的第一扭结部,其中所述第一键合点、所述第二键合点和所述第一扭结部位于第一平面上;位于所述第一平面外的第二扭结部;以及连接所述第一扭结部和所述第二扭结部的跨距部,其中所述第一扭结部、所述第二扭结部和所述第一键合点位于与所述第一平面成角度地设置的第二平面上。
以下通过参照说明本发明优选实施例的附图更详细地描述本发明将是方便的。附图和相关描述的特殊性不应被理解为取代由权利要求限定的本发明的广泛识别的一般性。
附图说明
现在将参考附图描述根据本发明的方法和形成的导线环的示例,如下述附图记录。
图1a和1b分别是在芯片上导线键合应用中采用的常规导线环的侧视图和俯视图。
图2a和2b分别是在芯片上导线键合应用中采用的本发明的优选实施例的侧视图和俯视图。
图 3a和3b分别是采用根据本发明的导线键合方法的导线键合装置的环运动轨迹的优选实施例的侧视图和俯视图表示。
图4(a)至(j)是示出根据本发明的优选实施例的导线环形成期间键合工具的不同位置处的键合线的形状的示意图。
图5示出了使用本发明的优选实施例形成的导线环的部分的透视照片视图。
具体实施方式
应该指出,为了说明的目的,图中的某些方面被夸大了。图2a和2b分别是在芯片上导线键合应用中采用的本发明的优选实施例的侧视图和俯视图。导线环40和半导体芯片20形成在基板30上。导线环40形成在半导体芯片20的顶表面上方,而不与半导体芯片20接触。导线环40在第一键合点32和第二键合点34处与基板30键合。
导线环40在基板30上的第一键合点32处键合。导线环40基本沿垂直方向延伸且大致上平行于半导体芯片20的第一侧边,在第一扭结部42处弯曲。导线环40的跨距部46从第一扭结部42基本沿水平方向延伸且大致平行于半导体芯片20的顶表面朝向半导体芯片20的相对的第二侧边延伸到第二扭结部44。导线环40在第二扭结部44处朝向第二键合点34弯曲。导线环40的倾斜部48从半导体芯片20的第二侧边处的第二扭结部42开始,并朝向与基板30键合的第二键合点34倾斜。
与常规导线环10不同的是,根据本发明的优选实施例的导线环40基本上不位于单个垂直平面上。第一键合点32、第二键合点34和第一扭结部42基本上位于第一垂直平面50上。第一键合点32、第一扭结部42、跨距部46和第二扭结部44基本上位于第二垂直平面52。第二扭结部44、倾斜部48和第二键合点34基本上位于第三垂直平面54内。第一,第二和第三垂直平面50,52,54相交以形成具有基本上均匀的横截面积的三角形棱柱。换句话说,第二垂直平面52与第一垂直平面50成角度地设置,第三垂直平面54与第一垂直平面50和第二垂直平面52成角度地设置。
第二扭结部44与第一垂直平面50的水平间隔距离可以是从第一扭结部42到第二扭结部44的导线环40的长度的约1%至约20%之间。优选地,第二扭结部44与第一垂直平面的水平间隔距离为从第一扭结部42到第二扭结部44的导线环40的长度的约5%至约10%之间。
导线环40的第二扭结部44与第一垂直平面50的距离间隔具有如下几个相关联的优点。倾斜部48现在可以更长,而不会增加侧视总水平距离(如从图2a所示的侧视图看到的)。实际上,这也意味着在半导体封装件的设计期间,第二键合点34可以移动得更靠近半导体芯片20的侧面。尽管倾斜部48的实际倾斜度现在变得比较平缓(与图1a和1b所示的常规导线环10相比),但是导线环40的侧视纵向着陆角(如从图2a所示的侧视图看到的)现在可以比常规方法中的更大。这有效地避免了如图1a和1b所示的常规导线环10所面对的侧视纵向着陆角的大小的限制。因此,与图1a和1b所示的常规导线环10相比,导线环40的侧视水平跨长(如从图2a所示的侧视图看到的)也将更长。本发明的优选实施例可以允许侧视水平跨长大于侧视总水平距离的90%,并且允许侧视纵向着陆角为约80度至约90度(如从图2a所示的侧视图看到的)。例如,侧视总水平距离为2.0mm,侧视水平跨长为1.9mm,侧视倾斜部水平长度为0.1mm。在该示例中,侧视水平跨长百分比是侧视总水平距离的95%。
此外,跨距部46现在可以进一步延伸到半导体芯片20的周边外部,而不会导致侧视总水平距离增加(从图2a所示的侧视图看到的)。该延伸的优点是在导线环40和半导体芯片20表面之间的第二扭结部44处将存在更大的间隙,以防止导线环40和半导体芯片20之间的接触。
图3a和3b分别是使用根据本发明的导线键合方法的导线键合装置的弧线运动轨迹(loop motion profile)的优选实施例的侧视图和俯视图。图4(a)至(j)是示出根据本发明的优选实施例的导线环形成期间的键合线60在诸如毛细管劈刀62的键合工具的不同位置处的形状的示意图。
毛细管劈刀62馈送键合线60以将键合线60键合在第一键合表面64和第二键合表面66之间以形成导线环40。第一键合70首先在第一键合表面64上的第一键合点32(点A)处制成。然后,将毛细管劈刀62从第一键合70移开预定的距离。这可以通过将毛细管劈刀62基本上垂直向上移动一定距离到点B,并且通过远离第二键合表面66上的第二键合点34(点J)的反作用运动移动到点C来完成。该后一运动弯曲键合线60以形成第一扭结部42。如图3b所示,点A、点B、点C和点J位于第一垂直平面50上。点A和点B位于点C和点J之间,如图3b所示的俯视图中看到的。
从点C开始,毛细管劈刀62以正作用运动朝向第二键合点34(点J)并且垂直向上移动到点D,然后进一步移动到点E。此后,毛细管劈刀62再次基本上垂直向上移动到点F,然后通过反作用运动以及向上移动到点G。从点C到点G的毛细管劈刀62的运动释放一定长度的键合线60以允许足够长的键合线60被馈送出以形成导线环40的跨距部46。如图3b所示,点A(和点B)、点C、点D、点E、点F、点G和点J都位于第一垂直平面50上。
毛细管劈刀62在对角线向下运动中从点G移动到点H,并且在与第二垂直平面50成锐角的反向和横向作用运动中远离第二键合点34(点J)。毛细管劈刀62的对角线向下运动及反向和横向运动的这种组合使键合线60弯曲而形成第二扭结部44,使得导线环40的跨距部46设置成与第一垂直平面50成一定角度。如图3b所示,点H位于第一垂直平面50之外,并且水平定位成比点G更远离点J。
从H点开始,毛细管劈刀62向上移动,并且在正横向作用运动中朝向第一垂直平面50并沿第二键合点34(点J)的方向回移。自点H的垂直运动在位于第一键合点32(点A)的基本垂直上方的点I处终止。从点H到点I的毛细管劈刀62的运动允许馈送出足够长的键合线60以形成导线环40的倾斜部48。此后,毛细管劈刀62向下移动并且以正作用运动移动到第二键合点34(点J)以形成第二键合72。至此形成导线环40。
图5示出了使用本发明的优选实施例形成的导线环40的部分的透视照片视图。跨距部46延伸到半导体芯片20的周边外部,使得在导线环40和半导体芯片20表面之间的第二扭结部44处具有大的间隙,以避免导线环40和半导体芯片20之间的接触。类似地,在半导体封装件的设计期间,第二键合点34也可以移动得更靠近半导体芯片20的侧面。
虽然已经参照本发明的某些实施例相当详细地描述了本发明,但是其它实施例也是可能的。
例如,本发明不限于在芯片上导线键合应用中采用的导线环。本发明可以用于需要导线键合的任何其它应用中,例如板上导线键合应用。
除了具体描述的那些之外,本文描述的发明易于进行变化、修改和/或添加,并且应当理解,本发明包括落在上述说明的精神和范围内的所有这样的变化、修改和/或添加。

Claims (15)

1.一种使用键合工具在第一键合点和第二键合点之间键合线的方法,其特征在于,包括以下步骤:
利用所述键合工具在所述第一键合点处形成第一键合;
当形成第一扭结部时,通过仅沿着包含第一键合点、第二键合点及第一扭结部的垂直平面移动所述键合工具来形成位于第一键合上的第一扭结部;
将所述键合工具移动到与所述第一扭结部间隔开预定距离的第一位置以从所述键合工具释放一定长度的线;
将所述键合工具沿远离第二键合点的方向移动到在包括所述第一键合点、所述第二键合点和所述第一扭结部的所述垂直平面外的第二位置;
形成位于所述垂直平面外的第二扭结部;和
将所述键合工具移动到所述第二键合点以形成第二键合。
2.如权利要求1所述的键合线的方法,其特征在于:形成位于所述第一键合之上的所述第一扭结部的步骤还包括以下步骤:使所述键合工具沿远离所述第二键合点的方向移动、接着使所述键合工具沿反向朝向所述第二键合点移动。
3.如权利要求2所述的键合线的方法,其特征在于:将所述键合工具移动到所述第二位置的步骤还包括以下步骤:使所述键合工具向下移动以形成所述第二扭结部,从而使得所述第一扭结部与第二扭结部之间的线的一部分设置成与所述垂直平面成一角度。
4.如权利要求3所述的键合线的方法,其特征在于:所述第二扭结部与所述垂直平面水平地间隔开的距离为所述第一扭结部和第二扭结部之间的所述线的一部分的长度的1%至20%之间。
5.如权利要求4所述的键合线的方法,其特征在于:所述第二扭结部与所述垂直平面水平地间隔开的距离为所述第一扭结部和第二扭结部之间的所述线的一部分的长度的5%至10%之间。
6.如权利要求1所述的键合线的方法,其特征在于:使所述键合工具移动到与所述第一键合间隔开所述预定距离的所述第一位置的步骤包括以下步骤:使所述键合工具向上移动并沿朝向所述第二键合点的方向移动。
7.如权利要求1所述的键合线的方法,其特征在于:形成在所述第一扭结部和第二扭结部之间的导线环的一部分的侧视水平跨长大于所述第一键合和第二键合之间的侧视总水平距离的90%。
8.如权利要求7所述的键合线的方法,其特征在于:所述侧视水平跨长是所述第一键合和第二键合之间的侧视总水平距离的95%。
9.如权利要求1所述的键合线的方法,其特征在于:所述第二扭结部和所述第二键合之间的所述线的一部分的侧视纵向着陆角在80度和90度之间。
10.一种键合在第一键合点和第二键合点之间的导线环,其特征在于,其形成于键合有半导体芯片的基板上,所述第一键合点邻接于所述半导体芯片的第一侧边,所述第二键合点邻接于所述半导体芯片的第一侧边相对的第二侧边,所述导线环形成于所述半导体芯片的第一侧边与第二侧边之间的半导体芯片的顶表面上方,所述导线环包括:
位于所述第一键合点上方的第一扭结部,其中所述第一键合点、所述第二键合点和所述第一扭结部位于第一垂直平面上;
位于所述第一垂直平面外的第二扭结部;和
连接所述第一扭结部和所述第二扭结部的跨距部,所述跨距部沿所述半导体芯片的第一侧边朝向半导体芯片的第二侧边延伸,其中第一扭结部、所述第二扭结部、所述跨距部和所述第一键合点位于与所述第一垂直平面成角度地设置的第二垂直平面上。
11.如权利要求10所述的导线环,其特征在于,还包括:
连接所述第二扭结部和所述第二键合点的倾斜部,其中,所述第二扭结部、所述倾斜部和所述第二键合点位于与所述第一垂直平面和所述第二垂直平面成角度地设置的第三平面上。
12.如权利要求11所述的导线环,其特征在于:在所述第二扭结部和所述第二键合之间的所述导线环的一部分的侧视纵向着陆角在80度和90度之间。
13.如权利要求10所述的导线环,其特征在于:形成在所述第一扭结部和第二扭结部之间的所述导线环的一部分的侧视水平跨长大于所述第一键合点和第二键合点之间的侧视总水平距离的90%。
14.如权利要求10所述的导线环,其特征在于:所述第二扭结部与所述第一垂直平面水平间隔距离为所述第一扭结部和第二扭结部之间的线的一部分的长度的1%至20%之间。
15.如权利要求14所述的导线环,其特征在于:所述第二扭结部与所述第一垂直平面水平间隔距离为所述第一扭结部和第二扭结部之间的所述线的一部分的长度的5%至10%之间。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5961029A (en) * 1997-01-13 1999-10-05 Kabushiki Kaisha Shinkawa Wire bonding method
TW413876B (en) * 1998-06-25 2000-12-01 Shinkawa Kk Wire bonding method
JP2007073937A (ja) * 2005-08-12 2007-03-22 Kaijo Corp ボンディングワイヤのループ形状及びそのループ形状を備えた半導体装置並びにボンディング方法
CN107039294A (zh) * 2012-02-07 2017-08-11 奥托戴尼电气公司 引线环成型系统和利用该系统的方法

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MY152355A (en) * 2011-04-11 2014-09-15 Carsem M Sdn Bhd Short and low loop wire bonding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5961029A (en) * 1997-01-13 1999-10-05 Kabushiki Kaisha Shinkawa Wire bonding method
TW413876B (en) * 1998-06-25 2000-12-01 Shinkawa Kk Wire bonding method
JP2007073937A (ja) * 2005-08-12 2007-03-22 Kaijo Corp ボンディングワイヤのループ形状及びそのループ形状を備えた半導体装置並びにボンディング方法
CN107039294A (zh) * 2012-02-07 2017-08-11 奥托戴尼电气公司 引线环成型系统和利用该系统的方法

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