CN108074814B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108074814B CN108074814B CN201611002333.3A CN201611002333A CN108074814B CN 108074814 B CN108074814 B CN 108074814B CN 201611002333 A CN201611002333 A CN 201611002333A CN 108074814 B CN108074814 B CN 108074814B
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- H01L29/7848—
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Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate is provided with a plurality of isolation structures; forming a gate structure on the substrate between adjacent isolation structures; forming stress layers in the substrate on two sides of the gate structure; and forming a cap layer on the stress layer, wherein the process for forming the cap layer comprises a spin coating process. According to the technical scheme, after the stress layer is formed, the cap layer is formed on the stress layer, and the process for forming the cap layer comprises a spin coating process. The cap layer is formed through a spin coating process, so that the appearance of the formed cap layer cannot change along with the change of the appearance of the stress layer, and a plurality of cap layers between the gate structures have flush surfaces, so that the formed cap layer can better repair the appearance of the stress layer, the surface appearance of the formed cap layer can be improved, and the electrical performance of the formed semiconductor structure can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Transistors are currently being widely used as the most basic semiconductor devices. As the density and integration of devices in integrated circuits increases, the size of transistors becomes smaller and smaller. As transistor dimensions shrink, the channel length and gate length of the transistor also shrink. The shortening of the channel length of the transistor makes the approximation of the graded channel no longer true, which causes short channel effect, and further generates leakage current, which affects the performance of the semiconductor device. By introducing stress into the channel region of the transistor, the mobility of carriers in the channel can be improved, and further the driving current of the transistor is improved, so that the leakage current of the transistor is suppressed.
The method for introducing stress into the channel region of the transistor comprises the step of forming a stress layer in the transistor, wherein the stress layer is used for providing compressive stress for the channel region of the PMOS transistor and introducing tensile stress for the channel region of the NMOS transistor, so that the mobility of carriers in the channel region of the transistor is improved, and the performance of the transistor is improved. Specifically, the stress layer is generally formed of a silicon germanium material or a silicon carbon material, and a compressive stress or a tensile stress is formed by lattice mismatch between the stress layer and the silicon crystal.
However, the semiconductor structure with the stress layer formed in the prior art often has the problem of poor electrical performance.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the electrical performance of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of isolation structures; forming a gate structure on the substrate between adjacent isolation structures; forming stress layers in the substrate on two sides of the gate structure; and forming a cap layer on the stress layer, wherein the process for forming the cap layer comprises a spin coating process.
Optionally, the step of forming a cap layer on the stress layer includes: forming a precursor layer on the stress layer by a spin coating process; and curing the precursor layer to form the cap layer.
Optionally, in the step of forming a precursor layer on the stress layer by a spin coating process, the precursor layer is a polysilane layer.
Optionally, in the step of forming a precursor layer on the stress layer by a spin coating process, a material of the precursor layer includes one or two of polysilane and cyclopentasilane.
Optionally, in the step of forming a precursor layer on the stress layer by a spin coating process, the precursor layer further includes a solvent, the solvent is a hydrocarbon, and the number of carbon atoms in the hydrocarbon is greater than 4.
Optionally, in the step of forming a precursor layer on the stress layer by a spin coating process, the hydrocarbon is C5H12。
Optionally, after forming the precursor layer and before the curing, the forming method further includes: and removing part of the thickness of the precursor layer by back etching.
Optionally, the step of etching back the precursor layer includes: and etching back the precursor layer by a dry etching mode.
Optionally, the step of performing a curing process on the precursor layer includes: baking the precursor layer; and annealing the baked precursor layer to form the cap layer.
Optionally, in the step of performing a baking process on the precursor layer, the temperature of the baking process is in a range of 150 ℃ to 350 ℃, and the time of the baking process is in a range of 5 minutes to 15 minutes.
Optionally, in the step of annealing the baked precursor layer, the annealing temperature is in a range of 350 ℃ to 800 ℃, and the annealing time is in a range of 2 minutes to 8 minutes.
Optionally, one or both of the step of forming a precursor layer on the stress layer by a spin coating process and the step of performing a curing process on the precursor layer includes: the spin coating process or the curing process is performed under an atmosphere of an inert gas having a pressure in a range of 200Torr to 500 Torr.
Optionally, the step of forming the stress layer includes: forming openings in the substrate on two sides of the grid structure; and filling a stress material into the opening to form the stress layer.
Optionally, the step of forming the stress layer includes: a stress layer is formed in a shape of a sigma.
Optionally, the step of forming the stress layer includes: the stress layer is made of a germanium-silicon material.
Optionally, the step of filling the opening with a stress material includes: and filling stress materials into the opening in an epitaxial growth mode.
Optionally, after forming the cap layer, the forming method further includes: and forming a metal layer covering the cap layer.
Optionally, in the step of forming the metal layer, the metal layer is made of nickel.
Accordingly, the present invention also provides a semiconductor structure comprising:
a substrate having a plurality of isolation structures therein; a gate structure on the substrate between adjacent isolation structures; stress layers positioned in the substrates at two sides of the gate structure; and the cap layer is positioned on the stress layer and is formed by a spin coating process.
Optionally, the material of the cap layer comprises silicon.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, after the stress layer is formed, the cap layer is formed on the stress layer, and the process for forming the cap layer comprises a spin coating process. The process for forming the cap layer comprises a spin coating process, so that the appearance of the formed cap layer cannot change along with the change of the appearance of the stress layer, and a plurality of cap layers among the gate structures have flush surfaces, so that the formed cap layer can better realize the repair of the appearance of the stress layer, the surface appearance of the formed cap layer is favorably improved, and the electrical performance of the formed semiconductor structure is favorably improved.
In an alternative aspect of the invention, after the cap layer of polysilane material is formed, a metal layer covering the cap layer is formed to form metal silicide to reduce contact resistance. Compared with the technical scheme for forming the repairing layer, the technical scheme of the invention directly realizes the repairing of the stress layer appearance through the cap layer, simplifies the process steps, is beneficial to reducing the process difficulty and improving the yield.
Drawings
FIGS. 1 to 3 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure having a stress layer;
fig. 4 to 9 are schematic structural diagrams corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As known from the background art, the semiconductor structure with stress layer in the prior art has the problem of poor electrical performance. The cause of the performance failure problem is analyzed in combination with a method for forming a semiconductor structure with a stress layer:
referring to fig. 1 to 3, schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure with a stress layer are shown.
Referring to fig. 1, a substrate 10 is provided, the substrate 10 having an isolation structure 11 therein; forming a gate structure 12 on the substrate 10 between adjacent isolation structures 11; forming a stress layer 13 in the substrate 100 at two sides of the gate structure 12; a cap layer 14 is formed on the stress layer 13.
Specifically, the step of forming the stress layer 13 includes: forming openings in the substrate 100 on both sides of the gate structure 12; and filling a stress material into the opening to form the stress layer 13.
The stress layer 12 is made of silicon germanium. In the process of epitaxially growing and filling the germanium-silicon material, the growth speeds of the germanium-silicon material on different crystal planes of the silicon substrate are different, and the growth speed on the (100) plane is higher than that on the (111) plane. Therefore, during the formation of the stress layer 13, a relatively serious facet effect (facet effect) often occurs in the stress layer 13 adjacent to the isolation structure 11, so that the stress layer 13 adjacent to the isolation structure 13 cannot completely fill the opening, and the profile of the formed stress layer 13 is defective (as shown in a circle 15 in fig. 1).
The appearance of the stress layer 13 is defective, so that the cap layer 14 formed on the stress layer 13 is also easily defective, the difficulty of the process for forming the cap layer 13 is increased, and the appearance of the formed cap layer 14 is difficult to ensure; therefore, the cap layer 14 is easily damaged to expose the stress layer 13 in the subsequent process, especially in the process of forming the contact hole. The exposure of the stress layer 13 may increase the possibility of damage to the stress layer 13, thereby affecting the yield of the semiconductor structure and the performance of the semiconductor structure.
In order to improve the defects of the topography of the stress layer 13, one method is to control the process conditions of the growth of the stress layer 13 to reduce the occurrence of the facet effect of the stress layer 13 as much as possible so as to improve the topography of the stress layer 13. But this has a limited effect on improving the topography defects of the stress layer 13.
In another method, as shown in fig. 2, a repair layer 15 of polysilicon is formed on the gate structure 12 and the stress layer 13; then, as shown in fig. 3, the repair layer 15 (as shown in fig. 2) on the top and the sidewall of the gate structure 12 is removed by etching back, so that the repair layer 15 remaining on the stress layer 13 corrects the morphology of the stress layer 13.
However, in the method of repairing the morphology of the stress layer 13 by using the repair layer 15, the difficulty in controlling the thickness of the repair layer 15 and the difficulty in controlling the process of etching back the repair layer 15 are both large:
if the thickness of the repair layer 15 is too large, or the thickness of the repair layer 15 is etched back too small, since the repair layer 15 of polysilicon material is usually conformally covered on the gate structure 12 and the stress layer 13, the repair layer 15 tends to easily remain on the sidewall of the gate structure 12 (as shown in the circle 18 in fig. 3) when the repair layer 15 is etched back. When a plug is formed subsequently, the repairing layer 15 remained on the sidewall of the gate structure 12 is easy to form metal silicide, so that short circuit occurs between the formed plug and the gate structure 12, and the performance of the formed semiconductor structure is affected.
If the thickness of the formed repairing layer 15 is too small, or the thickness of the etched-back repairing layer 15 is too large, the removed repairing layer 15 is too large, the remaining repairing layer 15 is too small, and the function of the repairing layer 15 for repairing the defect of the stress layer 13 is not obvious (as shown in a ring 17 in fig. 3).
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
providing a substrate, wherein the substrate is provided with a plurality of isolation structures; forming a gate structure on the substrate between adjacent isolation structures; forming stress layers in the substrate on two sides of the gate structure; and forming a cap layer on the stress layer, wherein the process for forming the cap layer comprises a spin coating process.
According to the technical scheme, after the stress layer is formed, the cap layer is formed on the stress layer, and the process for forming the cap layer comprises a spin coating process. The cap layer is formed through a spin coating process, so that the appearance of the formed cap layer cannot change along with the change of the appearance of the stress layer, and a plurality of cap layers between the gate structures have flush surfaces, so that the formed cap layer can better repair the appearance of the stress layer, the surface appearance of the formed cap layer can be improved, and the electrical performance of the formed semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 4 to 9, schematic structural diagrams corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention are shown.
Referring to fig. 4, a substrate 100 is provided, the substrate 100 having a plurality of isolation structures 101 therein.
The substrate 100 is used to provide a process platform.
In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials, or the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
The isolation structure 101 is used to electrically isolate adjacent Active Areas (AA).
The isolation structure 101 is made of silicon oxide. In other embodiments of the present invention, the material of the isolation structure 101 may also be other insulating materials such as fluorosilicate glass, fluorine-doped silicate glass, and tetraethyl orthosilicate.
The step of forming the isolation structure 101 includes: forming an isolation pattern layer on the substrate 100; etching the substrate 100 by using the isolation pattern layer as a mask, and forming an isolation opening in the substrate 100; and filling a dielectric material into the isolation opening to form the isolation structure 101.
In this embodiment, the semiconductor structure is a planar transistor, and thus the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure may also be a fin field effect transistor; accordingly, the substrate has discrete fins thereon. The isolation structure is located on the substrate with the exposed fin portion. The top surface of the isolation structure is lower than the top surface of the fin part and covers the surface of the partial side wall of the fin part.
With continued reference to fig. 4, a gate structure 112 is formed on the substrate 100 between adjacent isolation structures 101.
The gate structure 112 is used to control the conduction and the cut-off of the channel in the formed semiconductor structure. In this embodiment, the gate structure 112 is a gate structure of a semiconductor structure to be formed. In other embodiments of the present invention, the gate structure may also be a dummy gate structure in a "gate last process" for occupying a spatial position for a subsequently formed gate.
In this embodiment, the forming method further includes: in the process of forming the gate structure 112, a dummy gate structure 111 located on the isolation structure 101 is formed. In this embodiment, the gate structure 112 and the dummy gate structure 111 have the same structure, and include a gate layer and a sidewall on a sidewall of the gate layer.
The gate layer may be a single layer structure or a stacked layer structure. The gate layer comprises an electrode layer; or the gate layer comprises a gate dielectric layer positioned on the substrate and an electrode layer positioned on the gate dielectric layer. The electrode layer is made of polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the gate dielectric layer is made of silicon oxide or silicon oxynitride. The side wall can be of a single-layer structure or a laminated structure. The material of the sidewall may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and in this embodiment, the gate structure 112 and the dummy gate structure 111 are both formed by an electrode layer of polysilicon, a gate dielectric layer of silicon oxide, and a sidewall of silicon nitride.
The gate structure 112 and the dummy gate structure 111 may be simultaneously formed. Specifically, the step of forming the gate structure 112 and the dummy gate structure 111 includes: forming a gate material layer on the substrate 100; forming a gate pattern layer on the gate material layer; etching the gate material layer by using the gate pattern layer as a mask, and removing part of the gate material layer on the substrate 100 to form a gate layer; forming a sidewall spacer material layer covering the substrate 100 and the gate layer; and removing the side wall material layer on the substrate 100 and the gate layer to form the side wall.
In other embodiments of the present invention, the semiconductor structure is a fin field effect transistor; correspondingly, in the step of forming the gate structure, the gate structure crosses over the fin and covers the top of the fin and part of the surface of the side wall.
Referring to fig. 4 and 5 in combination, a stress layer 130 is formed in the substrate 100 on both sides of the gate structure 112.
The stress layer 130 is used to form a source region or a drain region of a transistor.
Specifically, the semiconductor structure is a P-type transistor, so the stress layer 130 is made of a silicon germanium material. In this embodiment, the step of forming the stress layer 130 includes: the stress layer 130 is formed in a "sigma" shape such that the stress layer 130 has a protruding tip pointing towards the channel region, introducing more stress into the channel region.
The step of forming the stress layer 130 includes: as shown in fig. 4, the substrate 100 on both sides of the gate structure 112 is etched, and an opening 120 is formed in the substrate 100 on both sides of the gate structure 112; as shown in fig. 5, a stress material is filled in the opening 120 to form the stress layer 130.
The opening 120 is used to provide a process space for the formation of the stress layer.
Since the stress layer 130 is formed in a "sigma" shape, the opening 120 is shaped in a "sigma" shape. In this embodiment, the substrate 100 is made of silicon, so the bottom of the opening 120 is a (100) plane, and the sidewall of the opening 120 is a (111) plane.
In this embodiment, a first opening 121 is located between adjacent gate structures 112. The first opening 121 is located in the substrate 100, i.e. is surrounded by the substrate 100; the opening 120 between the gate structure 112 and the dummy gate structure 111 is a second opening 122. The second opening 122 is adjacent to the isolation structure 101, i.e. the second opening 122 is enclosed by the substrate 100 and the isolation structure 101.
The step of filling the stress material is used to form the stress layer 130.
Specifically, the step of filling the opening 120 with the stress material includes: and filling a stress material into the opening 120 by means of epitaxial growth to form a stress layer 130. Since the stress layer 130 is made of a germanium-silicon material, the stress material is a germanium-silicon material.
In this embodiment, the stress layer 130 located in the first opening 121 (as shown in fig. 4) is a first stress layer 131; the stress layer 130 located within the second opening 122 (shown in fig. 4) is a second stress layer 132.
Since the bottom of the opening 120 is a (100) plane and the sidewall of the opening 120 is a (111) plane, the growth rate of the stress layer 130 on the sidewall of the opening 120 is less than the growth rate of the stress layer 130 on the bottom of the opening 120 in the process of filling the stress material by epitaxial growth. In addition, the growth rate of the stress layer 130 on the surface of the isolation structure 101 is less than that of the stress layer 130 on the surface of the substrate 100.
Therefore, the growth rates of both sides of the first stress layer 131 are similar, so that the first stress layer 131 can completely fill the first opening 121, i.e., the surface topography of the first stress layer 131 is better; the growth rate of the second stress layer 132 near the isolation structure 101 is slow, so the second stress layer 132 cannot completely fill the second opening 132, a defect (as shown in the circle 133 in fig. 5) occurs near the isolation structure 101, and the morphology of the second stress layer 132 is poor.
In this embodiment, the forming method further includes: and carrying out ion doping on the stress layer 130 to form a source drain doped region. Specifically, the step of performing ion doping on the stress layer 130 may be performed by performing in-situ self-doping during the process of forming the stress layer 130; or after the stress layer 130 is formed, ion implantation is performed on the stress layer 130. In this embodiment, the semiconductor structure is a P-type transistor, so the dopant ions are P-type ions, such as B, Ga or In.
Referring to fig. 6 to 9, a cap layer 140 is formed on the stress layer 130, and the step of forming the cap layer 140 includes a spin coating process.
The cap layer 140 is used for subsequent reaction with metal to form metal silicide to reduce the contact resistance of the stress layer. In addition, the cap layer 140 is also used for repairing the morphological defects of the stress layer 130, so as to improve the performance of the formed semiconductor structure.
Since the process of forming the cap layer includes a spin coating process. Because the spin coating process utilizes centrifugal force to uniformly distribute the glue solution on the substrate rotating at high speed, the morphology of the formed cap layer 140 cannot change along with the change of the morphology of the stress layer 130, and the plurality of cap layers 140 between the gate structures 112 have flush surfaces, so that the formed cap layer 140 can better realize the repair of the morphology of the stress layer 130, thereby being beneficial to improving the surface morphology of the formed cap layer 140 and improving the electrical performance of the formed semiconductor structure.
Specifically, the step of forming the cap layer 140 on the stress layer 130 includes:
as shown in fig. 6 and 7, a precursor layer 141 is formed on the stress layer 130 by a spin coating process.
The precursor layer 141 is used to form the cap layer.
Specifically, in the step of forming the precursor layer 141 on the stress layer 130 by a spin coating process, the precursor layer 141 is a polysilane layer. In this embodiment, the material of the precursor layer 141 includes one or two of polyethylsilane (polydihydrosilane) and cyclopentasilane (croppentasilan).
In addition, in the step of forming the precursor layer 141 on the stress layer 130 by the spin coating process,the precursor layer 141 further comprises a solvent, which is a hydrocarbon compound having a carbon number greater than 4, such as C5H12。
Thus, either polyethylsilane (polydihydrosilane) or cyclopentasilane (Crropentasan) and a hydrocarbon solvent form a silicon-containing precursor. The silicon-containing precursor has certain fluidity; a silicon-containing precursor substance having fluidity is applied on the stress layer 130 by a spin coating process to form the precursor layer 141.
In order to promote the deposition of gas in the precursor layer 141, reduce the formation of bubbles in the precursor layer 141, and improve the quality of the formed precursor layer 141, in this embodiment, the step of forming the precursor layer on the stress layer by a spin coating process includes: the spin coating process is performed under a low pressure atmosphere filled with an inert gas. Specifically, the spin coating process is carried out in N2He, Ne or Ar.
If the pressure of the inert gas is too high, the gas in the formed precursor layer 141 is not favorably separated out, and the formation of bubbles in the precursor layer 141 is not favorably reduced; if the pressure of the inert gas is too low, energy waste is caused, and the process difficulty is increased. In this embodiment, the pressure of the inert gas is in the range of 200Torr to 500 Torr.
After the precursor layer 141 is formed, referring to fig. 8 and 9, the precursor layer 141 (shown in fig. 7) is cured to form the cap layer 140.
In the present embodiment, in order to completely fill the formed precursor layer 141 between the adjacent gate structures 112, the precursor layer 141 covers the gate structures 112. Therefore, after the precursor layer 141 is formed and before the curing process is performed, the forming method further includes: a portion of the thickness of the precursor layer 141 is removed by etching back.
The step of etching back the precursor layer 141 is to remove a portion of the material of the precursor layer 141, so that the formed precursor layer 141 has a target thickness, and the gate structure 112 and the dummy gate structure 111 are exposed. Specifically, the step of etching back the precursor layer 141 includes etching back the precursor layer 141 by dry etching.
The curing process is used to remove a solvent or the like in the precursor layer 141, so as to cure the precursor layer 141, thereby improving the lattice quality of the cap layer 140.
Specifically, the step of performing the curing process on the precursor layer 141 includes: performing a baking process 151 on the precursor layer 141; the baked precursor layer 141 (shown in fig. 8) is annealed 152 to form the cap layer 140.
The baking process 151 is used to remove the solvent in the precursor layer 141, increase the hardness of the precursor layer 141, and primarily cure the precursor layer 141.
The temperature of the baking process 151 should not be too high or too low.
If the baking temperature is too low, the removal of the solvent in the precursor layer 141 is not facilitated, and the preliminary curing of the precursor layer 141 is not facilitated, a solvent residue may be formed in the precursor layer 141, which affects the quality of the formed cap layer 140, and affects the subsequent reaction between the cap layer 140 and the metal layer; if the baking temperature is too high, unnecessary process risks may be caused, damage may be caused to the stress layer 130, and other semiconductor structures on the substrate 100 may be affected. In this embodiment, in the step of performing the baking process 151 on the precursor layer 141, the temperature of the baking process 151 is in a range of 150 ℃ to 350 ℃.
The baking process 151 should not be performed for too long or too short a time.
If the time of the baking process 151 is too short, the solvent in the precursor layer 141 is not removed, and the preliminary curing of the precursor layer 141 is not performed, a solvent residue may be formed in the precursor layer 141, which affects the quality of the formed cap layer 140, and affects the reaction between the subsequent cap layer 140 and the metal layer; if the baking process 151 is performed for a long time, unnecessary process risks may be caused, the stress layer 130 may be damaged, and other semiconductor structures on the substrate 100 may be affected, and the production efficiency may be affected due to the long time of the baking process 151. In this embodiment, in the step of performing the baking process 151 on the precursor layer 141, the time of the baking process 151 is in a range from 5 minutes to 15 minutes.
The temperature and time of the baking process 151 cooperate with each other to remove the solvent in the precursor layer 141, so that the precursor layer 141 is primarily cured. The temperature and time of the baking process 151 are set within a reasonable range so that the efficiency and effect of the baking process 151 are balanced with each other.
The annealing treatment 152 is used for curing the precursor layer 141 to form the cap layer 140, and increasing the order of atomic arrangement in the cap layer 140, thereby improving the quality of the formed cap layer 140.
The temperature of the annealing treatment 152 is not preferably too high or too low.
If the annealing temperature is too low, the curing of the precursor layer 141 is not facilitated, the increase of the order of the atomic arrangement in the cap layer 140 is not facilitated, the quality of the formed cap layer 140 is affected, and the reaction of the cap layer 140 and a metal layer formed subsequently is affected; if the annealing temperature is too high, unnecessary process risks may be caused, damage may be caused to the stress layer 130, and other semiconductor structures on the substrate 100 may be affected. In this embodiment, in the step of performing the annealing 152 on the baked precursor layer 141, the temperature of the annealing 152 is in a range of 350 ℃ to 800 ℃.
The annealing treatment 152 is preferably not too long nor too short.
If the annealing treatment 152 is too short, it is not favorable for the solidification of the precursor layer 141, and is unfavorable for the increase of the order of the atomic arrangement in the cap layer 140, which may affect the quality of the formed cap layer 140, and affect the reaction of the cap layer 140 with the subsequently formed metal layer; if the annealing treatment 152 is too long, unnecessary process risks may be caused, damage may be caused to the stress layer 130, other semiconductor structures on the substrate 100 may be affected, and the production efficiency may be affected due to too long processing time caused by too long annealing treatment 152. In this embodiment, in the step of performing the annealing 152 on the baked precursor layer 141, the time of the annealing 152 is in a range from 2 minutes to 8 minutes.
The temperature and time of the annealing treatment 152 cooperate with each other to remove the solvent in the precursor layer 141, so that the precursor layer 141 is cured to form the cap layer 140. The temperature and time of the annealing process 152 are set within reasonable ranges so that the efficiency and effectiveness of the annealing process 152 are balanced.
It should be noted that, in order to improve the quality of the formed cap layer 140 and reduce the formation of the holes in the cap layer 140, in this embodiment, the step of performing a curing process on the precursor layer 141 includes: the curing process is performed in a low pressure atmosphere filled with an inert gas, that is, the baking process 151 and the annealing process 152 are both performed in a low pressure atmosphere filled with an inert gas.
Specifically, the baking treatment 151 and the annealing treatment 152 are performed in the presence of N2He, Ne or Ar. During the baking process 151 and the annealing process 152, the polysilane or cyclopentasilane reacts to form the cap layer 140. By-products of the reaction, e.g. O2Or H2The gases are purged out by an inert gas.
If the pressure of the inert gas is too high, the separation of the gas in the formed cap layer 140 is not facilitated, and the formation of holes in the cap layer 140 is not facilitated to be reduced; if the pressure of the inert gas is too low, energy waste is caused, and the process difficulty is increased. In this embodiment, the pressure of the inert gas is in the range of 200Torr to 500 Torr.
In this embodiment, after the cap layer 140 is formed, the forming method further includes: a metal layer is formed overlying the cap layer 140. Specifically, the metal layer includes nickel. The metal layer reacts with the cap layer 140 to form a metal silicide for reducing the contact resistance of the stress layer 130.
Because the cap layer 140 is formed by a spin coating process, the morphology of the cap layer 140 does not change with the change of the morphology of the stress layer 130, and the cap layer 140 can repair the morphology defect of the second stress layer 132, so that the surface flatness of the cap layer 140 on the second stress layer 132 and the first stress layer 132 is higher, the occurrence of the damage phenomenon of the cap layer 140 in the subsequent process can be effectively reduced, the formation of the subsequent metal silicide is facilitated, and the performance of the formed semiconductor structure is improved.
Correspondingly, the invention also provides a semiconductor structure.
Referring to fig. 9, a cross-sectional structure diagram of an embodiment of a semiconductor structure of the invention is shown.
The semiconductor structure includes:
a substrate 100, wherein the substrate 100 has a plurality of isolation structures 101 therein; a gate structure 112 on the substrate 100 between adjacent isolation structures 101; stress layers 130 located in the substrate 100 at two sides of the gate structure 112; a cap layer 140 located on the stress layer 130, wherein the cap layer 140 is formed by a spin coating process.
The substrate 100 is used to provide a process platform.
In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate may also be other semiconductor materials, or the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
The isolation structure 101 is used to electrically isolate adjacent Active Areas (AA).
The isolation structure 101 is made of silicon oxide. In other embodiments of the present invention, the material of the isolation structure 101 may also be other insulating materials such as fluorosilicate glass, fluorine-doped silicate glass, and tetraethyl orthosilicate.
In this embodiment, the semiconductor structure is a planar transistor, and thus the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure may also be a fin field effect transistor; accordingly, the substrate has discrete fins thereon. The isolation structure is located on the substrate with the exposed fin portion. The top surface of the isolation structure is lower than the top surface of the fin part and covers the surface of the partial side wall of the fin part.
The gate structure 112 is used to control the conduction and the cut-off of the channel in the semiconductor structure.
In this embodiment, the gate structure 112 is a gate structure of the semiconductor structure. In other embodiments of the present invention, the gate structure may also be a dummy gate structure in a "gate last process" for occupying a spatial position for the gate of the semiconductor structure.
In addition, the semiconductor structure further includes: and the dummy gate structure 111 is positioned on the isolation structure 101. In this embodiment, the gate structure 112 and the dummy gate structure 111 have the same structure, and include a gate layer and a sidewall on a sidewall of the gate layer.
The gate layer may be a single layer structure or a stacked layer structure. The gate layer comprises an electrode layer; or the gate layer comprises a gate dielectric layer positioned on the substrate and an electrode layer positioned on the gate dielectric layer. The electrode layer is made of polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the gate dielectric layer is made of silicon oxide or silicon oxynitride. The side wall can be of a single-layer structure or a laminated structure. The material of the sidewall may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and in this embodiment, the gate structure 112 and the dummy gate structure 111 are both formed by an electrode layer of polysilicon, a gate dielectric layer of silicon oxide, and a sidewall of silicon nitride.
In other embodiments of the present invention, the semiconductor structure is a fin field effect transistor; correspondingly, the gate structure crosses the fin part and covers the top of the fin part and part of the surface of the side wall.
The stress layer 130 is used to form a source region or a drain region of a transistor.
Specifically, the semiconductor structure is a P-type transistor, so the stress layer 130 is made of a silicon germanium material. In this embodiment, the stress layer 130 is a "sigma" shaped stress layer, such that the stress layer 130 has a protruding tip pointing towards the channel region, introducing more stress into the channel region.
The stress layer 130 includes a first stress layer 131 between adjacent gate structures 112 and a second stress layer 132 between the gate structures 112 and the dummy gate structure 111. Since the second stress layer 132 is located on the gate structure 112 and the dummy gate structure 111, and the dummy gate structure 111 is located on the isolation structure 101, the second stress layer 132 is adjacent to the isolation structure 101. Since the material of the substrate 100 is different from the material of the isolation structure 101, the growth rate of the second stress layer 132 on the surface adjacent to the substrate 100 is different from the growth rate of the second stress layer 132 on the surface adjacent to the isolation structure 101. Specifically, the growth rate of the second stress layer 132 on the surface adjacent to the isolation structure 101 is relatively low, so that the second stress layer 132 cannot completely fill the second opening 132, and a defect occurs on the side close to the isolation structure 101, thereby causing poor morphology.
It should be noted that the stress layer 130 has doped ions therein to form a source/drain doped region. In this embodiment, the semiconductor structure is a P-type transistor, so the dopant ions In the stress layer 130 are P-type ions, such as B, Ga or In.
The cap layer 140 is used for subsequent reaction with metal to form metal silicide to reduce the contact resistance of the stress layer 130. In addition, the cap layer 140 is also used for repairing the morphology defect of the stress layer 130, so as to improve the performance of the semiconductor structure.
Because the cap layer is formed by a spin coating process, and the spin coating process utilizes centrifugal force to uniformly distribute glue solution on the substrate rotating at high speed, the appearance of the cap layer 140 cannot change along with the change of the appearance of the stress layer 130, and the plurality of cap layers 140 between the gate structures 112 have flush surfaces, so that the cap layer 140 can better realize the repair of the appearance of the stress layer 130, thereby being beneficial to improving the surface appearance of the cap layer 140 and improving the electrical performance of the semiconductor structure.
In addition, since the cap layer 140 is also used for forming a metal silicide by subsequent reaction with a metal to reduce the contact resistance of the stress layer 130, the material of the cap layer 140 includes silicon.
In other embodiments of the present invention, the semiconductor structure further includes: a metal layer covering the cap layer 140. Specifically, the material of the metal layer comprises nickel.
In summary, according to the technical solution of the present invention, after the stress layer is formed, the cap layer is formed on the stress layer, and the process of forming the cap layer includes a spin coating process. The process for forming the cap layer comprises a spin coating process, so that the appearance of the formed cap layer cannot change along with the change of the appearance of the stress layer, and a plurality of cap layers among the gate structures have flush surfaces, so that the formed cap layer can better realize the repair of the appearance of the stress layer, the surface appearance of the formed cap layer is favorably improved, and the electrical performance of the formed semiconductor structure is favorably improved. In the alternative of the invention, after the cap layer of the polysilane material is formed, a metal layer covering the cap layer is formed to form metal silicide to reduce the contact resistance. Compared with the technical scheme for forming the repairing layer, the technical scheme of the invention directly realizes the repairing of the stress layer appearance through the cap layer, simplifies the process steps, is beneficial to reducing the process difficulty and improving the yield.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of isolation structures;
forming a gate structure on the substrate between adjacent isolation structures;
forming stress layers in the substrate on two sides of the gate structure;
forming a cap layer on the stress layer, wherein the process for forming the cap layer comprises a spin coating process;
and forming a metal layer covering the cap layer.
2. The method of forming of claim 1, wherein forming a cap layer over the stress layer comprises:
forming a precursor layer on the stress layer by a spin coating process;
and curing the precursor layer to form the cap layer.
3. The forming method according to claim 2, wherein in the step of forming a precursor layer on the stress layer by a spin coating process, the precursor layer is a polysilane layer.
4. The method of forming as claimed in claim 2 or 3, wherein in the step of forming a precursor layer on the stress layer by a spin coating process, a material of the precursor layer includes one or both of polyethylsilane and cyclopentasilane.
5. The method of forming of claim 2, wherein in the step of forming a precursor layer over the stress layer by a spin-on process, the precursor layer further comprises a solvent, the solvent is a hydrocarbon, and an atomic number of carbon in the hydrocarbon is greater than 4.
6. The method of forming of claim 5, wherein in the step of forming a precursor layer on the stress layer by a spin coating process, the hydrocarbon is C5H12。
7. The method of forming as claimed in claim 2, wherein after forming the precursor layer and before curing, the method further comprises: and removing part of the thickness of the precursor layer by back etching.
8. The method of forming as claimed in claim 7, wherein the step of etching back the precursor layer includes: and etching back the precursor layer by a dry etching mode.
9. The method of claim 2, wherein curing the precursor layer comprises:
baking the precursor layer;
and annealing the baked precursor layer to form the cap layer.
10. The forming method of claim 9, wherein the step of subjecting the precursor layer to a baking process, the baking process temperature is in a range of 150 ℃ to 350 ℃, and the baking process time is in a range of 5 minutes to 15 minutes.
11. The forming method of claim 9, wherein the annealing of the baked precursor layer is performed at a temperature in a range of 350 ℃ to 800 ℃ for a time in a range of 2 minutes to 8 minutes.
12. The method of forming of claim 2, wherein one or both of the step of forming a precursor layer over the stress layer by a spin coating process and the step of curing the precursor layer comprises: the spin coating process or the curing process is performed under an atmosphere of an inert gas having a pressure in a range of 200Torr to 500 Torr.
13. The method of forming of claim 1, wherein forming the stress layer comprises:
forming openings in the substrate on two sides of the grid structure;
and filling a stress material into the opening to form the stress layer.
14. The method of forming of claim 1 or 13, wherein the step of forming the stress layer comprises: a stress layer is formed in a shape of a sigma.
15. The method of forming of claim 1 or 13, wherein the step of forming the stress layer comprises: the stress layer is made of a germanium-silicon material.
16. The method of forming of claim 13, wherein filling the opening with a stress material comprises: and filling stress materials into the opening in an epitaxial growth mode.
17. The forming method according to claim 1, wherein in the step of forming the metal layer, a material of the metal layer is nickel.
18. A semiconductor structure formed by the method of any one of claims 1-17, comprising:
a substrate having a plurality of isolation structures therein;
a gate structure on the substrate between adjacent isolation structures;
stress layers positioned in the substrates at two sides of the gate structure;
and the cap layer is positioned on the stress layer and is formed by a spin coating process.
19. The semiconductor structure of claim 18, wherein the material of the cap layer comprises silicon.
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