CN108054904B - Method for updating firmware of power unit of frequency converter on line - Google Patents
Method for updating firmware of power unit of frequency converter on line Download PDFInfo
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- CN108054904B CN108054904B CN201711385594.2A CN201711385594A CN108054904B CN 108054904 B CN108054904 B CN 108054904B CN 201711385594 A CN201711385594 A CN 201711385594A CN 108054904 B CN108054904 B CN 108054904B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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Abstract
The invention discloses an online updating method of firmware of a power unit of a frequency converter, which comprises the following steps: the upper computer sends the updating instruction and the unit number corresponding to the power unit of the firmware to be updated to the FPGA unit through the DSP unit; the FPGA unit controls a power unit of the firmware to be updated to enter a starting loading mode; the FPGA unit breaks the connection between the upper computer and the DSP unit, and simultaneously establishes communication connection between the FPGA unit and the upper computer and communication connection between the upper computer and the updatable unit in the array to be updated; the FPGA unit sends firmware updating confirmation information to the upper computer; and the upper computer sends the updating code to the updating unit after receiving the information for confirming the updating of the firmware. And after the firmware is updated, the FPGA unit restores the connection between the DSP unit and the upper computer. The invention can finish the firmware update of the power unit through the upper computer without disassembling the power unit, and has the characteristic of high update efficiency.
Description
Technical Field
The invention relates to the technical field of firmware updating, in particular to an online updating method for firmware of a power unit of a frequency converter.
Background
In a medium-high voltage frequency converter formed by cascading power units, there are many power units, and along with technical improvement and upgrading, in order to meet the use requirements, firmware upgrading and updating are generally required to be performed on the power units in the frequency converter. The existing firmware updating method for the power unit generally includes detaching the power unit of the firmware to be updated, performing firmware updating operation on the power unit of the firmware to be updated through operation of a professional, and reassembling the power unit into the frequency converter after updating is completed. The power unit is required to be assembled and disassembled in the mode, the operation is complex, the occupied time is long, the operation can be carried out only by professional personnel, and the upgrading and updating process is complex.
Disclosure of Invention
In order to solve the problems in the prior art, the application provides an online updating method for firmware of a power unit of a frequency converter, wherein the frequency converter comprises a DSP unit and an FPGA unit which are connected with each other, the DSP unit is connected with an upper computer through the FPGA unit, and the FPGA unit is connected with the power unit. The method can finish the firmware upgrade of the power unit through the upper computer without disassembling the power unit, and has the characteristic of high update efficiency. The method for updating the firmware of the power unit of the frequency converter on line comprises the following steps:
the upper computer sends an updating instruction and a unit number corresponding to a power unit of the firmware to be updated to the FPGA unit through the DSP unit;
the FPGA unit sends the update instruction to the power unit of the firmware to be updated according to the unit number to control the power unit to enter a loading starting mode; after the power unit of the firmware to be updated enters a loading starting mode, sending confirmation information to the FPGA unit;
when the FPGA unit does not receive the confirmation information within the preset time, the FPGA unit sends an updating instruction to the power unit of the firmware to be updated again, and when the confirmation information is not received after the preset time is exceeded, the FPGA unit deletes the power unit of the firmware to be updated from the array to be updated;
when the FPGA unit receives the confirmation information within preset time, the power unit of the firmware to be updated is determined as an updatable unit and is kept in an array to be updated;
after the array to be updated is determined, the FPGA unit disconnects the upper computer and the DSP unit, and meanwhile, communication connection between the FPGA unit and the upper computer and communication connection between the upper computer and the updatable unit in the array to be updated are established;
the FPGA unit sends firmware updating confirmation information to the upper computer; and after receiving the firmware updating confirmation information, the upper computer sends an updating code to the updatable unit to control the updatable unit to complete firmware updating.
Optionally, after the step of sending, by the upper computer, an update code to the updateable unit to control the updateable unit to complete firmware update, the method further includes:
the FPGA unit disconnects the communication connection between the FPGA unit and the upper computer and the communication connection between the upper computer and the renewable unit, and meanwhile, the connection between the upper computer and the DSP unit is recovered.
Optionally, the sending, by the upper computer, an update code to the updateable unit includes:
the upper computer sends an updating code to the updatable unit in a segmented mode; the updatable unit sends response information to the FPGA unit every time the updatable unit receives one section of updating code;
when the FPGA unit does not receive the response information within the preset response time, the FPGA unit deletes the updatable unit from the array to be updated; when the FPGA unit receives the response information within the preset response time, the FPGA unit sends the response information to the upper computer;
and the upper computer continues to send the next section of updating code to the updating unit after receiving the response information until all the updating codes are sent.
Optionally, the upper computer sends the update instruction and the unit number corresponding to the power unit of the firmware to be updated to the FPGA unit through the DSP unit, including:
the upper computer sends an updating instruction and a unit number corresponding to a power unit of the firmware to be updated to the DSP unit through an RS485 communication line;
and the DSP unit sends the received update instruction and the unit number corresponding to the power unit of the firmware to be updated to the FPGA unit in a bus communication mode.
Optionally, the sending, by the FPGA unit, the update instruction to the power unit of the firmware to be updated according to the unit number includes:
the FPGA unit sends the updating instruction to the power unit of the firmware to be updated through the downlink optical fiber of the power unit of the firmware to be updated according to the unit number;
correspondingly, after the power unit of the firmware to be updated enters a start loading mode, the power unit sends confirmation information to the FPGA unit, specifically:
and after the power unit of the firmware to be updated enters a loading starting mode, sending confirmation information to the FPGA unit through the uplink optical fiber of the power unit.
Optionally, the FPGA unit establishes communication connections between itself and the upper computer and between the upper computer and the updateable unit, including:
the FPGA unit establishes communication connection between the FPGA unit and an RX port in an RS485 communication line of the upper computer and communication connection between a TX port in the RS485 communication line of the upper computer and a downlink optical fiber of the updatable unit.
The method comprises the steps that an update instruction and a unit number corresponding to a power unit of firmware to be updated are sent to an FPGA unit through a DSP unit by an upper computer; the FPGA unit controls a power unit of the firmware to be updated to enter a starting loading mode; the FPGA unit breaks the connection between the upper computer and the DSP unit, and simultaneously establishes communication connection between the FPGA unit and the upper computer and communication connection between the upper computer and the updatable unit in the array to be updated; the FPGA unit sends firmware updating confirmation information to the upper computer; and the upper computer sends the updating code to the updating unit after receiving the information for confirming the updating of the firmware. And after the firmware is updated, the FPGA unit restores the connection between the DSP unit and the upper computer. Therefore, under the condition that the power units are not disassembled, firmware updating of the power units can be completed through the upper computer, firmware updating of specific power units can be performed, firmware updating of all the power units can be completed at one time, and the power unit firmware updating system has the advantage of being high in updating efficiency.
Drawings
Fig. 1 is a schematic flowchart of an online firmware updating method for a power unit of a frequency converter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the connection between an upper computer and a DSP unit;
fig. 3 is a schematic diagram of connection between the upper computer and the FPGA unit and between the upper computer and the power unit.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating an online firmware updating method for a power unit of a frequency converter in the present embodiment, which is used for implementing firmware updating of the power unit in the frequency converter. The frequency converter comprises a DSP unit and an FPGA unit which are connected through a bus, wherein the DSP unit is connected with an upper computer through an RS485 communication line through the FPGA unit, and the FPGA unit is connected with a power unit through an uplink optical fiber and a downlink optical fiber, as shown in figure 2.
The method for updating the firmware of the power unit of the frequency converter on line specifically comprises the following steps:
and S101, the upper computer sends the updating instruction and the unit number corresponding to the power unit of the firmware to be updated to the FPGA unit through the DSP unit.
It should be noted that, in the initial state, the upper computer is in communication connection with the DSP unit through the RS485 communication line, so that after the power unit of the firmware to be updated is selected in the upper computer software, the following manner is adopted in this embodiment for sending the update instruction and the unit number corresponding to the power unit of the firmware to be updated:
the upper computer firstly sends an updating instruction and a unit number corresponding to a power unit of the firmware to be updated to the DSP unit through an RS485 communication line; and after receiving the information, the DSP unit sends the received update instruction and the unit number corresponding to the power unit of the firmware to be updated to the FPGA unit in a bus communication mode, and the FPGA unit carries out the next processing on the update instruction and the unit number corresponding to the power unit of the firmware to be updated.
And S102, the FPGA unit sends an update instruction to the power unit of the firmware to be updated according to the unit number to control the power unit to enter a loading starting mode.
It should be noted that, in order to ensure that the subsequent firmware update is performed smoothly, it is necessary to determine that the corresponding power unit enters the BootLoader mode, that is, the boot load mode. Therefore, in this embodiment, after the power unit of the firmware to be updated enters the boot loading mode, the confirmation information needs to be sent to the FPGA unit, so that the FPGA unit can determine whether the corresponding power unit has entered the BootLoader mode.
And the updating instruction is sent to the power unit of the firmware to be updated by the FPGA unit through the downlink optical fiber of the power unit of the firmware to be updated, and the confirmation information is sent to the FPGA unit by the power unit entering the BootLoader mode through the uplink optical fiber of the power unit of the firmware to be updated.
S103, the FPGA unit determines an array to be updated.
It should be noted that the above steps are to determine which power units have entered the BootLoader mode, that is, which power units may be subjected to firmware update. Specifically, the following method is adopted for determining the array to be updated in the embodiment:
and the FPGA unit judges whether confirmation information sent by the power unit of the firmware to be updated is received within preset time, wherein the confirmation information indicates that the corresponding power unit enters a BootLoader mode. And when the FPGA unit does not receive the confirmation information within the preset time, the FPGA unit can send an updating instruction to the power unit of the firmware to be updated again, and if the confirmation information is not received within the preset time, the FPGA unit deletes the power unit of the firmware to be updated from the array to be updated and does not update the firmware.
And when the FPGA unit receives the confirmation information within the preset time, the power unit of the firmware to be updated is determined to be an updatable unit, and the updatable unit is kept in the array to be updated so as to update the firmware of the updatable unit.
And S104, after the array to be updated is determined, the FPGA unit disconnects the upper computer from the DSP unit, and simultaneously establishes communication connection between the FPGA unit and the upper computer and communication connection between the upper computer and the updatable unit in the array to be updated.
It should be noted that, because the upper computer and the DSP unit are connected by the FPGA unit, the change to the communication line is realized by changing its internal line by the FPGA unit, specifically, the change to the communication line is:
the FPGA unit disconnects the connection between the upper computer and the DSP unit, meanwhile, the FPGA unit establishes communication connection between the FPGA unit and an RX port in an RS485 communication line of the upper computer and communication connection between a TX port in the RS485 communication line of the upper computer and a downlink optical fiber of the updatable unit, and the changed communication lines are shown in figure 3.
And S105, the FPGA unit sends the firmware updating confirmation information to the upper computer.
It should be noted that, when the communication line is changed, the FPGA unit may send the update confirmation firmware information to the upper computer through the RX port in the RS485 communication line of the upper computer, and inform the upper computer that the update code may be sent to the power unit at this time.
And S106, after receiving the firmware updating confirmation information, the upper computer sends an updating code to the updating unit to control the updating unit to complete firmware updating.
In the above steps, the upper computer sends the update code to the corresponding renewable unit directly through the downlink optical fiber of the power unit via the changed communication line, and the upper computer sends the update code to the renewable unit in a segmented manner; the updatable unit sends response information to the FPGA unit every time the updatable unit receives one section of the updating code;
when the FPGA unit does not receive the response information within the preset response time, the FPGA unit deletes the updatable unit from the array to be updated and stops updating the firmware of the unit; when the FPGA unit receives the response information within the preset response time, the FPGA unit sends the response information to the upper computer; and the upper computer continues to send the next section of updating code to the updating unit after receiving the response information, and the process is repeated until all the updating codes are sent.
After the firmware of the power unit is updated, the upper computer displays the power unit with failed firmware update, and the FPGA unit restores the communication line to the initial state shown in FIG. 2, namely the FPGA unit disconnects the communication connection between the FPGA unit and the upper computer and between the upper computer and the updatable unit, and restores the connection between the upper computer and the DSP unit.
The method comprises the steps that an update instruction and a unit number corresponding to a power unit of firmware to be updated are sent to an FPGA unit through a DSP unit by an upper computer; the FPGA unit controls a power unit of the firmware to be updated to enter a starting loading mode; the FPGA unit breaks the connection between the upper computer and the DSP unit, and simultaneously establishes communication connection between the FPGA unit and the upper computer and communication connection between the upper computer and the updatable unit in the array to be updated; the FPGA unit sends firmware updating confirmation information to the upper computer; and the upper computer sends the updating code to the updating unit after receiving the information for confirming the updating of the firmware. And after the firmware is updated, the FPGA unit restores the connection between the DSP unit and the upper computer. Therefore, under the condition that the power units are not disassembled, firmware updating of the power units can be completed through the upper computer, firmware updating of specific power units can be performed, firmware updating of all the power units can be completed at one time, and the power unit firmware updating system has the advantage of being high in updating efficiency.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. The method for updating the firmware of the power unit of the frequency converter on line is characterized by comprising the following steps of:
the upper computer sends an updating instruction and a unit number corresponding to a power unit of the firmware to be updated to the FPGA unit through the DSP unit; the upper computer sends an updating instruction and a unit number corresponding to a power unit of the firmware to be updated to the DSP unit through an RS485 communication line; the DSP unit sends the received updating instruction and the unit number corresponding to the power unit of the firmware to be updated to the FPGA unit in a bus communication mode;
the FPGA unit sends the update instruction to the power unit of the firmware to be updated according to the unit number to control the power unit to enter a loading starting mode; after the power unit of the firmware to be updated enters a loading starting mode, sending confirmation information to the FPGA unit;
when the FPGA unit does not receive the confirmation information within the preset time, the FPGA unit sends an updating instruction to the power unit of the firmware to be updated again, and when the confirmation information is not received after the preset time is exceeded, the FPGA unit deletes the power unit of the firmware to be updated from the array to be updated;
when the FPGA unit receives the confirmation information within preset time, the power unit of the firmware to be updated is determined as an updatable unit and is kept in an array to be updated;
after the array to be updated is determined, the FPGA unit disconnects the upper computer and the DSP unit, and meanwhile, communication connection between the FPGA unit and the upper computer and communication connection between the upper computer and the updatable unit in the array to be updated are established;
the FPGA unit sends firmware updating confirmation information to the upper computer; and after receiving the firmware updating confirmation information, the upper computer sends an updating code to the updatable unit to control the updatable unit to complete firmware updating.
2. The method for updating firmware of a power unit of a frequency converter in an online manner as claimed in claim 1, wherein after the step of sending an update code to the updateable unit by the upper computer to control the updateable unit to complete firmware update, the method further comprises:
the FPGA unit disconnects the communication connection between the FPGA unit and the upper computer and the communication connection between the upper computer and the renewable unit, and meanwhile, the connection between the upper computer and the DSP unit is recovered.
3. The method of claim 1, wherein the host computer sends an update code to the updateable unit, comprising:
the upper computer sends an updating code to the updatable unit in a segmented mode; the updatable unit sends response information to the FPGA unit every time the updatable unit receives one section of updating code;
when the FPGA unit does not receive the response information within the preset response time, the FPGA unit deletes the updatable unit from the array to be updated; when the FPGA unit receives the response information within the preset response time, the FPGA unit sends the response information to the upper computer;
and the upper computer continues to send the next section of updating code to the updating unit after receiving the response information until all the updating codes are sent.
4. The method for updating firmware of a power unit of a frequency converter according to claim 1, wherein the FPGA unit sends the update instruction to the power unit of the firmware to be updated according to the unit number, specifically:
the FPGA unit sends the updating instruction to the power unit of the firmware to be updated through the downlink optical fiber of the power unit of the firmware to be updated according to the unit number;
correspondingly, after the power unit of the firmware to be updated enters a start loading mode, the power unit sends confirmation information to the FPGA unit, specifically:
and after the power unit of the firmware to be updated enters a loading starting mode, sending confirmation information to the FPGA unit through the uplink optical fiber of the power unit.
5. The method of claim 1, wherein the FPGA unit establishes communication connections between itself and the host computer and between the host computer and the updateable unit, comprising:
the FPGA unit establishes communication connection between the FPGA unit and an RX port in an RS485 communication line of the upper computer and communication connection between a TX port in the RS485 communication line of the upper computer and a downlink optical fiber of the updatable unit.
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| CN112255527A (en) * | 2020-09-24 | 2021-01-22 | 胜达克半导体科技(上海)有限公司 | Testing component and integrated circuit testing machine |
| CN113360177A (en) * | 2021-06-07 | 2021-09-07 | 中电科思仪科技股份有限公司 | Device and method for online upgrading firmware program of vector network analyzer |
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| US10496775B2 (en) * | 2013-01-31 | 2019-12-03 | General Electric Company | Method and system for use in dynamically configuring data acquisition systems |
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| CN101814036A (en) * | 2010-03-09 | 2010-08-25 | 广州市聚晖电子科技有限公司 | RF remote upgrading method and system |
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