CN108054085B - The preparation method of memory - Google Patents
The preparation method of memory Download PDFInfo
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- CN108054085B CN108054085B CN201711288985.2A CN201711288985A CN108054085B CN 108054085 B CN108054085 B CN 108054085B CN 201711288985 A CN201711288985 A CN 201711288985A CN 108054085 B CN108054085 B CN 108054085B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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Abstract
Present invention discloses a kind of memories and forming method thereof.By forming the first pattern layer to define the first groove, and by forming the first adjustment layer to form the second groove in the first groove, so as to be directed at filling second adjustment layer in the second groove, the part exposed in removal the first adjustment layer is to form the second pattern layer, and first gap is formed between the first pattern layer and the second pattern layer, and then when by the pattern transfer of the first pattern layer and the second pattern layer into substrate, the first groove corresponding with first gap of formation correspondingly is in the substrate.Using the forming method of memory provided by the invention, it is capable of forming the lesser first groove of width dimensions, to be conducive to reduce the distance between adjacent active regions when defining multiple active areas using first groove.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of memory and preparation method thereof.
Background technique
With being constantly progressive for semiconductor technology, the process node of semiconductor devices just constantly reduces.However, due to by
The limitation of existing photoetching process precision is difficult to meet semiconductor devices with the mask pattern that existing photoetching process is formed and continues
The demand for reducing characteristic size (Critical Dimension, abbreviation CD), especially when characteristic size is reduced to 30nm or less,
Existing photoetching process can not prepare fine pattern, contain the development of semiconductor technology.
Summary of the invention
The object of the present invention is to provide a kind of preparation methods of memory, can accurately prepare small characteristic size
Pattern.
In order to solve the above technical problems, the present invention provides a kind of preparation method of memory, comprising:
A kind of forming method of memory characterized by comprising
One substrate is provided；
Form multiple first pattern layers over the substrate, first pattern layer is in strip structure and along a first direction
Extend, multiple first pattern layers sequentially arrange over the substrate along second direction, and adjacent two described the
One pattern layer defines one first groove；
Form a first adjustment layer over the substrate, the first adjustment layer covers first pattern layer and covers institute
The side wall and bottom wall of the first groove are stated, to utilize the part for covering first recess sidewall and bottom wall in the first adjustment layer
Second groove extended along the first direction is formed in first groove；
Alignment one second adjustment layer of filling makes to cover described first in the first adjustment layer in second groove
The part of recess sidewall exposes；
The part that first recess sidewall is covered in the first adjustment layer is removed, to form one along the first party
To extension first gap between first pattern layer and the second adjustment layer, and retain position in the first adjustment layer
Part below the second adjustment layer, to be constituted one the using the second adjustment layer and the remaining the first adjustment layer
Two pattern layers, and second pattern layer and first pattern layer define the first gap in this second direction
Width boundary；And
The figure of first pattern layer and the figure of second pattern layer are transferred in the substrate simultaneously, with shape
In the substrate at first groove corresponding with the first gap, and the adjacent first groove is deposited for defining
The active area of reservoir.
Optionally, after removing the first adjustment layer partially to form second pattern layer, and by figure turn
Before moving in the substrate, further includes:
Multiple third pattern layers are formed in first pattern layer and the second pattern layer, the third pattern layer is in bar shaped
Structure simultaneously along the second direction extend so that the third pattern layer in this second direction successively with first figure
Pattern layer and second pattern layer intersect, and an opening is constituted between the third pattern layer of adjacent two, passes through the opening
Expose the part that do not intersect with the third pattern layer in first pattern layer and second pattern layer；And
It is empty to form second using the third pattern layer as the first pattern layer described in mask etching and second pattern layer
In first pattern layer and second pattern layer, the Second gap and the first gap are interconnected gap.
Optionally, after forming the Second gap, after the figure of first pattern layer after etching and etching
Second pattern layer pattern transfer into the substrate, to be formed simultaneously corresponding with the first gap described first
In the substrate, the first groove and the second groove are mutual for groove and second groove corresponding with the Second gap
Connection defines multiple active areas for constituting isolated groove, and by the isolated groove；
Wherein, multiple active areas are arranged in array, and multiple active areas in same row are described
Arrangement is aligned on first direction, multiple active areas in the same row are aligned arrangement in this second direction.
Optionally, after removing the first adjustment layer partially to form second pattern layer, and by figure turn
Before moving in the substrate, further includes:
Third pattern layer is formed in first pattern layer and the second pattern layer, is formed in the third pattern layer more
Row aperture, aperture described in multirow along the first direction arrange and every a line in multiple apertures along described
The arrangement of two directions, and the aperture of adjacent rows is mutually staggered along the second direction, so that described in odd-numbered line opens
Hole exposes part first pattern layer, and the aperture in even number line exposes part second pattern layer；
Using the third pattern layer as the first pattern layer described in mask etching and second pattern layer, with formed with it is described
The corresponding Second gap of position of opening is in first pattern layer and second pattern layer, the Second gap and described
One gap is interconnected.
Optionally, after forming the Second gap, after the figure of first pattern layer after etching and etching
Second pattern layer pattern transfer into the substrate, to be formed simultaneously corresponding with the first gap described first
In the substrate, the first groove and the second groove are mutual for groove and second groove corresponding with the Second gap
Connection defines multiple active areas for constituting isolated groove, and by the isolated groove；
Wherein, multiple active areas are arranged in array, and multiple active areas in same row are described
The multiple active areas being aligned in arrangement and adjacent column on first direction are mutually staggered along the first direction.
Optionally, the part of the first pattern layer side wall is covered in the first adjustment layer in this second direction
Thickness value is less than the half of the width value of first groove in this second direction.
Optionally, the first direction and second direction have an acute angle.The angle of the acute angle is for example situated between
Between 5 °~85 °.
Optionally, a pattern transfer layer is formed between the substrate and first pattern layer.Wherein, the figure
The hardness of transfer layer is for example between 1HV~10HV.
Optionally, the thickness of the first adjustment layer is between 5nm~30nm.
Optionally, before forming the first adjustment layer, multiple first pattern layers are defined using photoetching process
Figure, and the spacing of two adjacent first pattern layers in this second direction be more than or equal to 30nm.
Based on the forming method of above-described memory, the present invention also provides a kind of memories, comprising:
Substrate is formed with multiple first grooves in the substrate, and the first groove extends along a first direction, Yi Jiduo
A first groove is successively arranged along second direction, and the adjacent first groove is for defining an active area, wherein
The width of the first groove in this second direction is between 5nm~30nm.
Optionally, multiple second grooves are also formed in the substrate, the second groove is prolonged along the second direction
It stretches and multiple second grooves is successively arranged along a first direction, the second groove and first groove intersection are simultaneously
It is interconnected to constitute isolated groove, multiple active areas is defined by the isolated groove；
Wherein, multiple active areas are arranged in array, and multiple active areas in same row are described
Arrangement is aligned on first direction, multiple active areas in the same row are aligned arrangement in this second direction.
Optionally, multirow second groove is also formed in the substrate, second groove described in multirow is along the first party
Multiple second grooves into arrangement and every a line are arranged along the second direction, second ditch of adjacent rows
Slot is mutually staggered along the second direction, and the second groove extends to first ditch along the second direction
Slot to be interconnected with the first groove to constitute isolated groove, and is defined by the isolated groove multiple described active
Area；
Wherein, multiple active areas are arranged in array, and multiple active areas in same row are described
The multiple active areas being aligned in arrangement and adjacent column on first direction are mutually staggered along the first direction.
In memory provided by the invention and preparation method thereof, it is recessed to define first to form multiple first pattern layers
Slot, and using the first groove by forming the first adjustment layer further to define the second groove, so as to be directed at filling second
For adjustment layer in the second groove, so i.e. available first pattern layer and second adjustment layer are exposure mask, are removed in the first adjustment layer
The part exposed to form the second pattern layer, and forms first gap between the first pattern layer and the second pattern layer, in reality
When existing pattern transfer, first groove corresponding with first gap can be formed in the substrate.It can be seen that providing according to the present invention
Forming method, the lesser first groove of width dimensions can be prepared, thus defining memory using first groove
When active area, it can correspondingly make the distance between active area adjacent in the multiple active areas defined smaller, be conducive to reality
The reduction of existing reservoir size.
For example, defining the figure of the first pattern layer, using photoetching process correspondingly to define the width of the first groove
Spend size.However, the width value minimum of first groove only can achieve photoetching process most under the limitation of photoetching process
Small line-spacing value, and can not accomplish again small.At this point, forming the first pattern layer and the second pattern using method provided by the invention
After layer, the smaller first gap of width dimensions can be defined, and then the width with first gap can be formed in the substrate
The corresponding first groove of size, it is clear that the width dimensions of first gap and then are conducive to reality less than the width dimensions of the first groove
The reduction of existing device size.
Detailed description of the invention
Fig. 1 is the flow diagram of the forming method of the memory in present invention implementation one；
Fig. 2 a is top view of the memory when it executes step S110 to step S120 in present invention implementation one；
Fig. 2 b is the memory in the embodiment of the present invention one shown in Fig. 2 a when it executes step S110 to step S120
Along AA ' and BB ' diagrammatic cross-section in direction；
Fig. 3 a is top view of the memory when it executes step S130 in present invention implementation one；
Fig. 3 b be memory shown in Fig. 3 a in the embodiment of the present invention one when it executes step S130 along AA ' and
The diagrammatic cross-section in the direction BB '；
Fig. 4 a is top view of the memory when it executes step S140 in present invention implementation one；
Fig. 4 b be memory shown in Fig. 4 a in the embodiment of the present invention one when it executes step S140 along AA ' and
The diagrammatic cross-section in the direction BB '；
Fig. 5 a is top view of the memory when it executes step S150 in present invention implementation one；
Fig. 5 b be memory shown in Fig. 5 a in the embodiment of the present invention one when it executes step S150 along AA ' and
The diagrammatic cross-section in the direction BB '；
Fig. 6 a is top view of the memory when it executes step S160 in present invention implementation one；
Fig. 6 b be memory shown in Fig. 6 a in the embodiment of the present invention one when it executes step S160 along AA ' and
The diagrammatic cross-section in the direction BB '；
Fig. 7 a is top view of the memory when it executes step S170 in present invention implementation one；
Fig. 7 b be memory shown in Fig. 7 a in the embodiment of the present invention one when it executes step S170 along AA ' and
The diagrammatic cross-section in the direction BB '；
Fig. 8 a~Fig. 9 a is top view of the memory when it executes step S180 in present invention implementation one；
Fig. 8 b and Fig. 9 b, which are respectively memory in the embodiment of the present invention one shown in Fig. 8 a and Fig. 9 a, executes step at it
Along AA ' and BB when S180 ' diagrammatic cross-section in direction；
Figure 10 is the flow diagram of the forming method of the memory in the embodiment of the present invention two；
Figure 11 a is top view of the memory when it executes step S260 in present invention implementation two；
Figure 11 b be memory shown in Figure 11 a in the embodiment of the present invention two when it executes step S260 along AA ' and
The diagrammatic cross-section in the direction BB '；
Figure 12 a is top view of the memory when it executes step S270 in present invention implementation two；
Figure 12 b be memory shown in Figure 12 a in the embodiment of the present invention two when it executes step S270 along AA ' and
The diagrammatic cross-section in the direction BB '；
Figure 13 a is top view of the memory when it executes step S280 in present invention implementation two；
Figure 13 b be memory shown in Figure 13 a in the embodiment of the present invention two when it executes step S280 along AA ' and
The diagrammatic cross-section in the direction BB '.
Wherein, appended drawing reference is as follows:
100- substrate；
101/101 '-isolated groove；
101a- first groove；
101b/101c- second groove；
102/102 '-active area；
103- isolation structure；
110- pattern transfer layer；
The first transfer layer of 111-；
The second transfer layer of 112-；
The first pattern layer of 120-；
The first groove of 120a-；
The second pattern layer of 130-；
The second groove of 130a-；
131- the first adjustment layer；
132- second adjustment layer；
140- first gap；
Third pattern layer；
250a- aperture；
Second gap.
Specific embodiment
It is described in more detail below in conjunction with preparation method of the schematic diagram to memory of the invention, which show
The preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify invention described herein, and still realize
Advantageous effects of the invention.Therefore, following description should be understood as the widely known of those skilled in the art, and not
As limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Embodiment one
Fig. 1 is the flow diagram of the forming method of the memory in present invention implementation one.Below in conjunction with Fig. 1 and each step
The forming method of the memory in the present embodiment is described in detail in structural schematic diagram in rapid.
Fig. 2 a is top view of the memory when it executes step S110 to step S120 in present invention implementation one, Fig. 2 b
For the memory in the embodiment of the present invention one shown in Fig. 2 a when it executes step S110 to step S120 along AA ' and BB '
The diagrammatic cross-section in direction.
In step s 110, as shown in Figure 2 a and 2 b, a substrate 100 is provided.In subsequent process flow, i.e., in institute
It states in substrate 100 and forms isolated groove, so as to further define the active area of memory.Specifically, the substrate 100
Material can be for example the semiconductor substrate of silicon, germanium or silicon-on-insulator.
With continued reference to shown in Fig. 2 a and Fig. 2 b, in the present embodiment, a pattern transfer layer is also formed on the substrate 100
110, the pattern transfer layer 110 for example can be used as hard mask layer, and hardness for example can be between 1HV~10HV.Rear
In continuous technique, the pattern transfer for the isolated groove for needing to be defined, at this time can be preferentially by isolating trenches into substrate 100
For the pattern transfer of slot into the pattern transfer layer 110, then recycling pattern transfer layer 110 is exposure mask, and figure is further
It is transferred to substrate 100.
Further, the pattern transfer layer 110 can be laminated construction.In the present embodiment, the pattern transfer layer 110
Including the first transfer layer 111 and the second transfer layer 112 being laminated from the bottom to top, wherein first transfer layer 111 and second turn
The etching selection ratio for moving layer 112 is more than or equal to 5, and the hardness range of first transfer layer 111 and the second transfer layer 112 can be
1HV~10HV.For example, the material of first transfer layer 111 is silicon nitride (SiN), the material of second transfer layer 112 is
Carbon (C).
In the step s 120, with continued reference to shown in Fig. 2 a and Fig. 2 b, multiple first pattern layers 120 of formation are in the substrate
On 100, first pattern layer 120 is in strip structure and (Y-direction) extension along a first direction, multiple first pattern layers
120 along second direction (X-direction) sequence arrangement, and two adjacent 120 boundaries of the first pattern layer over the substrate
Make one first groove 120a.
In the present embodiment, first pattern layer 120 is formed on pattern transfer layer 110.Specifically, first pattern
The forming method of layer 120 includes the following steps.
Firstly, forming one first pattern material layer on the pattern transfer layer 110.The first pattern material layer can be with
Including layer of material layer or multilayer laminated material layer.Specifically, when the first pattern material layer includes being laminated from the bottom to top
Two layers of material when, then can make in the first pattern material layer positioned at the material layer of bottom and positioned at the material layer of top layer
Etching selection ratio is more than or equal to 5.For example, the material layer silicon oxide layer for being located at bottom in the first pattern material layer can be made,
The material layer for being located at top layer in the first pattern material layer is organic polymer layers.
Then, photoresist design layer is formed on the first pattern material layer, and using the photoresist design layer as exposure mask, it is right
The first pattern material layer performs etching.In the etching process of the present embodiment, top is located in the first pattern material layer
The material layer of layer can be consumed, and, the material layer in the first pattern material layer positioned at bottom can be then patterned, into
And the first pattern layer 120 corresponding with the photoresist design layer is formed, first pattern layer 120 of adjacent two defines
One first groove 120a.Alternatively, it will also be appreciated that forming photoresist design layer using photoetching process, described in defining
While the figure of first pattern layer 120, the figure of the first groove 120a has correspondingly been defined.
Due to being influenced by photoetching process accuracy, it is restricted the spacing of the adjacent photoresist design layer, such as most
It is small to accomplish 30nm or so, but can not accomplish again small.In this way, by the pattern transfer of photoresist design layer to the first figure
In case material layer, when forming multiple first pattern layers 120, the distance values K1 of adjacent first pattern layer 120 is also corresponding
Be restricted, and can not accomplish again small.If when directly by the pattern transfer of first pattern layer 120 into substrate 100,
Then correspondingly will lead to width value of the isolated groove being formed in the substrate 100 in a second direction (in X-direction) is also
K1, the distance values being equivalent between the adjacent active area defined are K1.At this point it is possible to think, defined by photoetching process
Width value K1 out is the minimum line of photoetching process away from value.
As it can be seen that if define the figure of isolated groove merely with photoetching process, and then when defining the active area of memory,
Due to the limitation of photoetching process, it will directly restrict the lasting reduction of dimensions of semiconductor devices.
It is adjacent active further to reduce in order to reduce the width value for the isolated groove being subsequently formed in substrate 100
The distance between area then continues to execute step S130.
Fig. 3 a is top view of the memory when it executes step S130 in present invention implementation one, and Fig. 3 b is shown in Fig. 3 a
The embodiment of the present invention one in memory when it executes step S130 along AA ' and BB ' diagrammatic cross-section in direction.
In step s 130, with specific reference to shown in Fig. 3 a and Fig. 3 b, one the first adjustment layer 131 of formation is in the substrate 100
On, the first adjustment layer 131 covers first pattern layer 120 and covers the side wall and bottom wall of the first groove 120a,
With using covering the part of the first groove 120a side wall and bottom wall in the first adjustment layer 131 in first groove
A second groove 130a extended along the first direction (Y-direction) is defined in 120a.
Wherein, the material of the first adjustment layer 131 can be generally silica, silicon nitride or silicon oxynitride etc., institute
Atomic deposition (Atomic Layer Deposition) technique or plasma vapor deposition can be used by stating the first adjustment layer 131
The preparation of (Chemical Vapor Deposition) technique.In the present embodiment, it is covered in the first adjustment layer 131 described
The part of first groove 120a bottom wall correspondingly covers the pattern transfer layer 110 exposed.
With continued reference to shown in Fig. 3 b, the deposition thickness of the first adjustment layer 131 is preferably less than first groove
The half of the width of 120a in a second direction, i.e., the width of the described first groove 120a in a second direction are greater than 2 times
The first adjustment layer 131 deposition thickness, specifically, covering first pattern layer 120 in the first adjustment layer 131
Its thickness value of the part of side wall is less than the half of the width value of the first groove 120a in a second direction, to guarantee
The second groove 130a can be formed on the first groove 120a by stating the first adjustment layer 131, so as to utilize described the
Two groove 130a define the pattern of subsequent the second pattern layer that need to be formed.Wherein, the deposition thickness of the first adjustment layer 131
H1 is the first adjustment layer 131 perpendicular to the thickness in the first groove 120a sidewall direction.For example, described first adjusts
The thickness H1 of flood 131 is preferably 5nm~30nm, for example, 8nm, 10nm, 15nm, 20nm or 25nm etc..
Further, since the distance between second pattern layer and the first pattern layer 120 for being subsequently formed are by the first adjustment
The deposition thickness of layer 131 determines indirectly, therefore can adjust described first by the thickness of the adjusting the first adjustment layer 131
The spacing of pattern layer 120 and the second pattern, so as to adjust the width for the isolated groove being formed in the substrate 100, into
The distance between one successive step adjacent active regions.
Fig. 4 a is top view of the memory when it executes step S140 in present invention implementation one, and Fig. 4 b is shown in Fig. 4 a
The embodiment of the present invention one in memory when it executes step S140 along AA ' and BB ' diagrammatic cross-section in direction.
In step S140, alignment one second adjustment layer 132 of filling is in the second groove 130a, so that described first
The part that the first groove 120a side wall is covered in adjustment layer 131 exposes.Wherein, the material of the second adjustment layer 132
It can be generally silica, silicon nitride or silicon oxynitride etc..
Specifically, making the alignment of second adjustment layer 132 be filled in the second groove 130a in combination with flatening process
In.For example, be initially formed a second adjustment material layer on the substrate 100, the second adjustment material layer covering described the
One adjustment layer 131 simultaneously fills the second groove 130a；Then, using flatening process, the second adjustment material layer is removed
In be located at the part of first pattern layer, 120 top, be located at described the in the first adjustment layer 131 correspondingly to expose
The part of one pattern layer, 120 top, and retain the part being filled in second groove 130 in second adjustment material layer, it uses
In the composition second adjustment layer 132.Wherein, the flatening process for example, chemical mechanical milling tech or is etched back to work
Skill.
Fig. 5 a is top view of the memory when it executes step S150 in present invention implementation one, and Fig. 5 b is shown in Fig. 5 a
The embodiment of the present invention one in memory when it executes step S150 along AA ' and BB ' diagrammatic cross-section in direction.
In step S150, described is covered in the first adjustment layer 131 with specific reference to removing shown in Fig. 5 a and Fig. 5 b
The part of one groove 120a side wall, to form first gap 140 that one extends along the first direction (Y-direction) described the
Between one pattern layer 120 and the second adjustment layer 132, and retains and be located at the second adjustment layer in the first adjustment layer
The part of 132 lower sections, to be constituted one second pattern using the second adjustment layer 132 and the remaining the first adjustment layer 131
Layer 130, and second pattern layer 130 and first pattern layer 120 define the first gap 140 described second
Width boundary on direction (X-direction).
In the present embodiment, it is formed with pattern transfer layer 110 on the substrate 100, therefore, the pattern transfer layer 100
In part between second pattern layer 130 and first pattern layer 120 pass through the first gap 140 exposure
Out.That is, in this step, the first gap 140 is through on the pattern transfer layer 110, so that 120 He of the first pattern layer
Second pattern layer 130 is mutually separated by the first gap 140.
The part on top and side wall due to being located at first pattern layer 120 in the first adjustment layer is exposed,
So the part in the first adjustment layer on the top and side wall of first pattern layer 120 can be all removed, it is only remaining
The first adjustment layer 131 positioned at 132 lower section of second adjustment layer.Wherein it is possible to using the technique removal described first of etching
The part of 120 side wall of the first pattern layer is covered in adjustment layer 131, specifically, the first adjustment layer 131 and described second
The etching selection ratio of adjustment layer 132 is more than or equal to 4, for example, when the material of the first adjustment layer 131 is silica, it is described
The material of second adjustment layer 132 is silicon nitride.Therefore, big to the etch rate of the first adjustment layer 131 in etching process
In the etch rate to the second adjustment layer 132, to make first on the top and side wall of first pattern layer 120 to adjust
Flood 131 can be all removed, and, the first adjustment layer positioned at 132 lower section of second adjustment layer is by the second adjustment
Layer 132 is blocked and is retained, and certainly in the process, the part at 132 top of second adjustment layer may be partially consumed.
Preferably, removing the first adjustment layer 131 on the side wall of first pattern layer 120, dry etching using dry etch process
Technique has anisotropy, can be etched to avoid the first adjustment layer 131 for being located at 132 lower section of second adjustment layer by transition.
With continued reference to shown in Fig. 5 a and Fig. 5 b, 120 side of the first pattern layer is covered by removing in the first adjustment layer 131
The part of wall, to form first gap 140, the width value of the first gap 140 in a second direction is first figure
The distance values K2 of pattern layer 120 and the second pattern layer 130.Therefore, the spacing of first pattern layer 120 and the second pattern layer 130
Value K2 can be by adjusting the deposition thickness of the first adjustment layer 131 (that is, the first adjustment layer 131 is covered on the first pattern layer
The thickness of the part of 120 side walls in a second direction) it is adjusted, in general, the deposition thickness of the first adjustment layer 131 is got over
Thickness, the width value for being formed by first gap is also bigger, and then adjacent first pattern layer 120 and the second pattern layer 130
Distance values K2 it is also bigger.
Obviously, the distance values K2 of first pattern layer 120 and the second pattern layer 130 is less than adjacent first pattern
The distance values K1 (wherein, distance values K1 is equivalent to the minimum line of photoetching process away from value) of layer 120, if by first pattern layer
120 and second pattern layer 130 pattern transfer into the substrate, when forming isolated groove, be then formed by isolated groove
Width value is also K2 accordingly (in X-direction) in a second direction.That is, being formed by isolated groove 120 in a second direction
Minimum width value is less than the minimum line of photoetching process away from value, to overcome the limitation of photoetching process, makes the active area defined
The distance between it is smaller.
Preferably, in order to save the process, in the present embodiment, after the step S150, further include step S160 and
Step S170, by forming third pattern layer in first pattern layer 120 and the second pattern layer 130 of the substrate 100,
Further to carry out redefinition to the figure of first pattern layer 120 and the second pattern layer 130 using third pattern layer.
Fig. 6 a is top view of the memory when it executes step S160 in present invention implementation one, and Fig. 6 b is shown in Fig. 6 a
The embodiment of the present invention one in memory when it executes step S160 along AA ' and BB ' diagrammatic cross-section in direction.
In step S160, with specific reference to shown in Fig. 6 a and Fig. 6 b, forming multiple third pattern layers 150 in first figure
In pattern layer 120 and the second pattern layer 130, the third pattern layer 150 is in strip structure and along the second direction (X-direction)
Extend so that the third pattern layer 150 in the second direction (X-direction) successively with first pattern layer 120 and institute
The intersection of the second pattern layer 130 is stated, and is exposed in first pattern layer 120 and second pattern layer 130 not with described the
The part of three pattern layers 150 intersection.
With continued reference to shown in Fig. 6 a, first pattern layer 120 is the strip structure that (Y-direction) extends in a first direction,
Second pattern layer 130 is the strip structure extended in the first direction (Y-direction), first pattern layer 120 and institute
The second pattern layer 130 is stated to be sequentially arranged at intervals in second direction (X-direction).The third pattern layer 150 is in second direction (X
Direction) extend strip structure, and multiple third pattern layers 150 along a first direction (Y-direction) arrange, it is therefore, adjacent
There is an opening, wherein the third pattern layer 150 covers first pattern layer 120 and second between third pattern layer 150
It is located at adjacent the in the part intersected in pattern layer 130 with the third pattern layer 150 and first pattern layer 120
Part between three pattern layers 150 be exposed and second pattern layer 130 in be located at adjacent third pattern layer 150
Between part be exposed, that is, portion in the opening of third pattern layer 150 is corresponded in first pattern layer 120
Point be exposed and second pattern layer 130 in the part that corresponds in the opening of third pattern layer 150 be exposed
Out.
Fig. 7 a is top view of the memory when it executes step S170 in present invention implementation one, and Fig. 7 b is shown in Fig. 7 a
The embodiment of the present invention one in memory when it executes step S170 along AA ' and BB ' diagrammatic cross-section in direction.
In step S170, with specific reference to shown in Fig. 7 a and Fig. 7 b, using the third pattern layer as described in mask etching
One pattern layer 120 and second pattern layer 130, to form Second gap 160 in first pattern layer 120 and described second
In pattern layer 130, the Second gap 160 and the first gap 140 are interconnected.
As shown in Figure 7a, it is to be understood that it is formed with Second gap 160 in first pattern layer 120 after etching,
And by the mutually separated multiple pattern sections out of the Second gap 160；And it is formed in second pattern layer 130 after etching
There is Second gap 160, and by the mutually separated multiple pattern sections out of the Second gap 160.By forming Second gap 160 to obtain
To the figure of the first pattern layer 120 redefined and the figure of the second pattern layer 130, make the first pattern layer redefined and
The second pattern layer redefined is in multiple pattern sections, to be formed by multiple active areas subsequent, each is active
The i.e. corresponding pattern section in area.Wherein, the Second gap 160 runs through first pattern in a second direction (in X-direction)
Layer 120 and the second pattern layer 130, to make the Second gap 160 be connected to the first gap 140, and then common definition
The pattern of the subsequent isolated groove that need to be formed is gone out.
Fig. 8 a~Fig. 9 a is top view of the memory when it executes step S180 in present invention implementation one, Fig. 8 b and figure
9b be respectively memory in the embodiment of the present invention one shown in Fig. 8 a and Fig. 9 a when it executes step S180 along AA ' and
The diagrammatic cross-section in the direction BB '.
In step S180, with specific reference to shown in Fig. 8 a and Fig. 8 b, by the figure of first pattern layer 120 and described
The figure of two pattern layers 130 is transferred in the substrate 100 simultaneously, to form one and first sky in the substrate 100
The corresponding first groove 101 of gap 140, and the adjacent first groove 101 is used to define the active area 102 of memory.
In conjunction with shown in Fig. 7 a and Fig. 7 b, in the present embodiment, by forming third pattern layer to the first pattern layer and second
Pattern layer is redefined, and neutralizes the first pattern layer 120 after redefining in the second pattern layer 130 after redefining
It is each formed with Second gap 160.Therefore, the figure of the first pattern layer and the second pattern layer is shifted in the step, i.e. phase
When in the first pattern layer 120 redefined that will be formed with Second gap 160 and being formed with redefining for Second gap 160
The figure of the second pattern layer 130 shifted, exist so as to correspondingly form second groove 101b corresponding with Second gap
In the substrate 100.
Specifically, by the pattern transfer of the figure of the first pattern layer 120 and the second pattern layer 130 into substrate 100
Step includes:
Firstly, being exposure mask with the first pattern layer 120 and the second pattern layer 130, the pattern transfer layer 110 is etched, it will
The figure of the first pattern layer 120 redefined and the second pattern layer 130 redefined while being transferred to the pattern transfer
In layer 110；As described above, in the present embodiment, the pattern transfer layer 110 is laminated construction, and its first transfer layer 111 with
The etching selection ratio of second transfer layer 112 is more than or equal to 5, therefore during the etching pattern transfer layer 110, is located at top layer
The second transfer layer 112 can partially or completely be consumed, and be located at bottom the first transfer layer 111 can be retained and by figure
Change, so that the figure of the first pattern layer 120 and the figure of the second pattern layer 130 to be transferred to the of the pattern transfer layer simultaneously
In one transfer layer 111, to form multiple transfer grooves in the first transfer layer 111；
Then, patterned first transfer layer 111 is recycled to etch the substrate 100 as hard mask, with further
Isolated groove 101 is formed in the substrate 100.It is formed by isolated groove 101 and the first gap and second sky
Gap is corresponding, that is, the isolated groove 101 includes first groove 101a and second groove 101b, the first groove 101a and institute
State that first gap is corresponding and (Y-direction) extends along a first direction, and multiple first groove 101a are in a second direction successively
Arrangement, the second groove 101b is corresponding with Second gap and extends in substrate 100 along second direction, and multiple second
Groove 101b successively arranges in a first direction, so that second groove 101b and first groove 101a be made to intersect and be interconnected.
It is adjacent so as to define the active area 102 of memory jointly by first groove 101a and second groove 101b
The active area 102 is mutually separated by the first groove 101a and the second groove 101b, that is, adjacent active area
102 is mutually separated by isolated groove 101.Multiple active areas 102 are arranged in array, and multiple in same row
The active area 102 is aligned arrangement in said first direction, and multiple active areas 102 in the same row are described second
Arrangement is aligned on direction.
Wherein, the depth of the isolated groove 101 is, for example, 800nm~1600nm, subsequent is formed by storage to control
Transistor isolation degree.In addition, as described above, first groove 101a and the first gap phase in the isolated groove 101
Corresponding, therefore, the width value of first groove 101a in a second direction is equal to first pattern layer 120 and the second pattern layer
130 distance values K2, it is seen then that the width value K2 of the first groove 101a of the isolated groove 101 in a second direction is less than phase
The spacing K1 of adjacent first pattern layer, that is, the width value K2 of the isolated groove 101 in a second direction is less than photoetching work
The minimum line of skill is away from value.
It, can also be to the substrate after etching the substrate 100 to form isolated groove 101 in preferred scheme
100 carry out densification (Densification) technique.Wherein, the reactant gas of the densification technique can be with
Including ozone, carbon monoxide etc.；The densification technique can also use high energy light to be intensified, and high energy light can
Think ultraviolet light (UV) or laser (Laser) etc.；And densification technique can also be including 800 DEG C~1200 DEG C
Hot process annealing (Thermal Process Annealing) treatment process.
It further, further include filling after forming the isolated groove 101 with specific reference to shown in Fig. 9 a and Fig. 9 b
Isolated material is in the isolated groove 101, to form isolation structure 103.Wherein, the relative dielectric constant of the isolated material
Preferably less than it is equal to 3, such as the material of the isolated material is silica, thermocouple is leaked electricity and mitigated for isolated groove
It closes (coupling).In addition, a densification can also be carried out again after forming the isolation structure 103.
Correspondingly, the isolation structure 103 defines the active area (active area) 102, that is, the substrate 100
It is middle that the active area 102 is constituted around the part gone out by the isolation structure 103.In the present embodiment, the first figure for redefining
Pattern layer and the second pattern layer are in the structure of multiple pattern sections, and multiple pattern sections are phase in the first direction and a second direction
The array arrangement being mutually aligned, be in so as to correspondingly making to be formed by multiple active areas also in a first direction with second direction phase
The array arrangement being mutually aligned.
Further, the first direction (Y-direction) and second direction (X-direction) have an acute angle α, so can be into
One step is realized densely arranged between multiple active areas.Wherein, the angle of the acute angle α be 5 °~85 °, such as 10 °,
30 °, 50 ° or 70 ° etc..
Embodiment two
Difference with embodiment one is, in the present embodiment, when overline defines the first pattern layer and the second pattern layer, and institute
The figure of the third pattern layer of formation is different from the figure of the third pattern layer in embodiment one, and then can define and to be different from fact
Apply the arrangement mode of the active area in example one.
Figure 10 is the flow diagram of the forming method of the memory in the embodiment of the present invention two, in conjunction with Fig. 1 and Figure 10 institute
Show, the main distinction of the present embodiment and embodiment one is step S260~step S280.Therefore, the step in the present embodiment
S210~step S250 can refer to embodiment one, and details are not described herein again, below only to step S260~step in the present embodiment
S280 is described in detail.
Figure 11 a is top view of the memory when it executes step S260 in present invention implementation two, and Figure 11 b is Figure 11 a
Shown in memory in the embodiment of the present invention two when it executes step S260 along AA ' and BB ' diagrammatic cross-section in direction.
In step S260, with specific reference to shown in Figure 11 a and 11b, formation third pattern layer 250 is in first pattern layer
120 and second in pattern layer 130, are formed with multirow aperture 250a, the edge aperture 250a described in multirow in the third pattern layer 250
The first direction (Y-direction) arrangement and every a line in multiple aperture 250a along the second direction (side X
To) arrangement, and the aperture 250a of adjacent rows is mutually staggered along the second direction (X-direction), so that in odd-numbered line
The aperture 250a expose part first pattern layer 120, the aperture 250a in even number line exposes part institute
State the second pattern layer 130.
Figure 12 a is top view of the memory when it executes step S270 in present invention implementation two, and Figure 12 b is Figure 12 a
Shown in memory in the embodiment of the present invention two when it executes step S270 along AA ' and BB ' diagrammatic cross-section in direction.
It is mask etching institute with the third pattern layer 250 with specific reference to shown in Figure 12 a and Figure 12 b in step S270
The first pattern layer 120 and second pattern layer 130 are stated, to form Second gap 260 corresponding with the position of opening in institute
It states in the first pattern layer 120 and second pattern layer 130, the Second gap 260 is mutually interconnected with the first gap 140
It is logical.
As embodiment one kind, it is formed with Second gap 260 in first pattern layer 120 after etching, and by institute
State the mutually separated multiple pattern sections out of Second gap 260；And second is formed in second pattern layer 130 after etching
Gap 260, and by the mutually separated multiple pattern sections out of the Second gap 260.To be formed by multiple active areas subsequent
In, the i.e. corresponding pattern section of each active area.Wherein, the Second gap 260 runs through (in X-direction) in a second direction
First pattern layer 120 and the second pattern layer 130, so that the Second gap 260 be enable to connect with the first gap 140
It is logical, and then common definition has gone out the pattern of the subsequent isolated groove that need to be formed.
It continues to refer to figure 1 shown in 2a, in the present embodiment, by forming the third pattern layer different from embodiment one, thus
The figure of adjustable the first pattern layer redefined out and the figure of the second pattern layer redefined out, thus can be into one
Step changes the subsequent pattern for being formed by isolated groove.
Figure 13 a is top view of the memory when it executes step S280 in present invention implementation two, and Figure 13 b is Figure 13 a
Shown in memory in the embodiment of the present invention two when it executes step S280 along AA ' and BB ' diagrammatic cross-section in direction.
In step S280, with specific reference to shown in Figure 13 a and Figure 13 b, by the figure of first pattern layer 120 after etching
The pattern transfer of second pattern layer 130 after shape and etching is into the substrate 100, to be formed simultaneously and first sky
The corresponding first groove 101a and second groove 101c corresponding with the Second gap of gap 140 in the substrate 100,
The first groove 101a and the second groove 101c are interconnected for constituting isolated groove 101 ', and by the isolating trenches
Slot circle 101 ' defines multiple active areas 102 '.
Wherein, multiple active areas 102 ' are arranged in array, and multiple active areas in same row
102 ' in said first direction alignment arrangement and adjacent column in multiple active areas 102 ' along the first direction
It mutually staggers.That is, by redefining out the figure of the first pattern layer and the second pattern layer, and then changing in this implementation benefit
When the pattern of isolated groove 101 ', the arrangement mode of the active area 102 ' can be correspondingly adjusted, to realize multiple active areas
102 ' it is densely arranged.
In addition, after forming the isolated groove 101 ', can further fill isolated material with as embodiment one kind
In the isolated groove 101 ' to form isolation structure.The step is similar with embodiment, and details are not described herein again.
Embodiment three
According to the forming method of memory as described above, the present invention also provides a kind of memories.Figure 12 is the present invention
The top view of memory in embodiment three,
The memory includes a substrate, is formed with multiple first grooves in the substrate, and the first groove is along the
One direction extends and multiple first grooves are successively arranged along second direction, and the adjacent first groove is used for boundary
Make an active area, wherein the width of the first groove in this second direction is between 5nm~30nm.That is, described
The minimum widith of first groove is less than the minimum line of photoetching process away to make in defined active area, adjacent is active
The distance in area is smaller.
That is, usually directly defining the pattern of first groove using photoetching process, in turn in existing preparation process
For defining the active area of memory.However, under the limitation of photoetching process, the broad-ruler of the first groove directly defined
Very little minimum can only reach the minimum line of photoetching process away from value, and cannot achieve the further reduction of width dimensions.Specifically, existing
The minimum line of some photoetching processes is only for example 30nm away from value, however, the case where can not reduce the width dimensions of first groove
Under, the reduction of memory-size will be also restricted out significantly.
However, in memory provided by the invention forming method as described above can be utilized, to prepare broad-ruler
Very little lesser first groove, i.e. the width dimensions small fish 30nm of first groove, such as between 5nm~30nm, be conducive to reality
Reveal the distance between adjacent active regions in memory, and then the size of memory can be reduced significantly.
Further, multiple second grooves are also formed in the substrate of memory, the second groove is along institute
State that second direction extends and multiple second grooves are successively arranged along a first direction, the second groove and described the
One grooves are simultaneously interconnected to constitute isolated groove, define multiple active areas by the isolated groove.That is, utilizing
In multiple active areas that first groove and second groove are defined, multiple active areas are arranged in array, and same
Multiple active areas in one column are aligned arrangement in said first direction, and multiple active areas in the same row are in institute
It states and is aligned arrangement in second direction.
Certainly, the pattern and arrangement mode that can also adjust second groove according to actual needs, are defined with further adjusting
The arrangement mode of active area out.For example, the arrangement mode that multiple second grooves in the substrate can also be in multirow is formed,
Second groove described in middle multirow along the first direction arrange and every a line in multiple second grooves along described
Second direction arrangement.Also, the second groove of adjacent rows is mutually staggered along the second direction and second ditch
Slot extends to the first groove along the second direction, to be interconnected with the first groove to constitute isolated groove,
And multiple active areas are defined by the isolated groove.At this point, being defined according to first groove and second groove more
In a active area, multiple active areas are arranged in array, and multiple active areas in same row are described the
The multiple active areas being aligned in arrangement and adjacent column on one direction are mutually staggered along the first direction.
In conclusion defining first by forming the first pattern layer in the forming method of memory in the present invention
Groove, and the second groove is further defined in the first groove using second groove and the first adjustment layer, it is filled out so as to be aligned
Second adjustment layer is filled in the second groove.In this way, pass through portion under the effect of the exposure mask of the first pattern layer and second adjustment layer
Divide removal the first adjustment layer to form the second pattern layer, and first gap can be formed between the first pattern layer and the second pattern layer,
The width dimensions of the first gap for example (are covered on the first groove equal to the deposition thickness of the first adjustment layer in the first adjustment layer
Part on side wall is perpendicular to the thickness on the first recess sidewall direction), it is clear that the width dimensions of the first gap
Much smaller than the width dimensions of the first groove.To correspondingly may be used when forming first groove corresponding with first gap in the substrate
So that formed first groove is had lesser width size, is advantageously implemented the reduction of memory-size.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (13)
1. a kind of forming method of memory characterized by comprising
One substrate is provided；
Form multiple first pattern layers over the substrate, first pattern layer is in strip structure and prolongs along a first direction
It stretches, multiple first pattern layers are sequentially arranged over the substrate along second direction, and adjacent two described first
One first groove is defined between pattern layer, and is also formed with a figure between the substrate and first pattern layer and is turned
Layer is moved, the pattern transfer layer includes the first transfer layer and the second transfer layer of stacking from the bottom to top；
Form a first adjustment layer over the substrate, the first adjustment layer covers first pattern layer and covers described the
The side wall and bottom wall of one groove, with using covering the part of first recess sidewall and bottom wall in the first adjustment layer in institute
It states and forms second groove extended along the first direction in the first groove；
Alignment one second adjustment layer of filling makes to cover first groove in the first adjustment layer in second groove
The part of side wall exposes；
The part for covering first recess sidewall in the first adjustment layer is removed, is prolonged with forming one along the first direction
The first gap stretched retains between first pattern layer and the second adjustment layer and is located at institute in the first adjustment layer
The part below second adjustment layer is stated, to be constituted one second figure using the second adjustment layer and the remaining the first adjustment layer
Pattern layer, and second pattern layer and first pattern layer define the width of the first gap in this second direction
Boundary is spent, wherein the part that the first pattern layer side wall is covered in the first adjustment layer is removed using dry etch process,
And in etching process, the etch rate to the second adjustment layer is greater than to the etch rate of the first adjustment layer, with
It is partially consumed the part at the top of the second adjustment layer；
The figure of first pattern layer and the figure of second pattern layer are transferred in the substrate simultaneously, with formed with
In the substrate, and the adjacent first groove is for defining memory for the corresponding first groove of the first gap
Active area；Wherein, by the pattern transfer of the figure of first pattern layer and second pattern layer into the substrate
Step includes: execution etching technics, by the pattern transfer of the figure of first pattern layer and second pattern layer to institute
It states in pattern transfer layer, and is further transferred in the substrate to form isolated groove, and the institute of the pattern transfer layer
The etching selection ratio for stating the first transfer layer and second transfer layer is more than or equal to 5, to etch the pattern transfer layer to shape
During at the isolated groove, first pattern layer, the first adjustment layer, the second adjustment layer and described second
Transfer layer is consumed, and first transfer layer is retained and is patterned；And
It after forming the isolation trench, further include filling isolated material in the isolation trench, to form isolation structure,
And after forming the isolation structure, a densification is also carried out.
2. the forming method of memory as described in claim 1, which is characterized in that partially remove the first adjustment layer with
Formed after second pattern layer, and by pattern transfer into the substrate before, further includes:
Multiple third pattern layers are formed in first pattern layer and the second pattern layer, the third pattern layer is in strip structure
And along the second direction extend so that the third pattern layer in this second direction successively with first pattern layer
Intersect with second pattern layer, an opening is constituted between the third pattern layer of adjacent two, is exposed by the opening
The part that do not intersect out with the third pattern layer in first pattern layer and second pattern layer；And
Using the third pattern layer as the first pattern layer described in mask etching and second pattern layer, existed with forming Second gap
In first pattern layer and second pattern layer, the Second gap and the first gap are interconnected.
3. the forming method of memory as claimed in claim 2, which is characterized in that, will after forming the Second gap
The pattern transfer of the figure of first pattern layer after etching and second pattern layer after etching into the substrate, with
It is formed simultaneously and the corresponding first groove of the first gap and second groove corresponding with the Second gap is described
In substrate, the first groove and the second groove are interconnected for constituting isolated groove, and by isolated groove circle
Make multiple active areas；
Wherein, multiple active areas are arranged in array, and multiple active areas in same row are described first
Arrangement is aligned on direction, multiple active areas in the same row are aligned arrangement in this second direction.
4. the forming method of memory as described in claim 1, which is characterized in that partially remove the first adjustment layer with
Formed after second pattern layer, and by pattern transfer into the substrate before, further includes:
Third pattern layer is formed in first pattern layer and the second pattern layer, multirow is formed in the third pattern layer and opens
Hole, aperture described in multirow along the first direction arrange and every a line in multiple apertures along the second party
It is mutually staggered to the aperture of arrangement, and adjacent rows along the second direction, so that the aperture in odd-numbered line is sudden and violent
First pattern layer described in exposed portion, the aperture in even number line expose part second pattern layer；
Using the third pattern layer as the first pattern layer described in mask etching and second pattern layer, to be formed and the aperture
The corresponding Second gap in position is in first pattern layer and second pattern layer, the Second gap and first sky
Gap is interconnected.
5. the forming method of memory as claimed in claim 4, which is characterized in that, will after forming the Second gap
The pattern transfer of the figure of first pattern layer after etching and second pattern layer after etching into the substrate, with
It is formed simultaneously and the corresponding first groove of the first gap and second groove corresponding with the Second gap is described
In substrate, the first groove and the second groove are interconnected for constituting isolated groove, and by isolated groove circle
Make multiple active areas；
Wherein, multiple active areas are arranged in array, and multiple active areas in same row are described first
The multiple active areas being aligned in arrangement and adjacent column on direction are mutually staggered along the first direction.
6. the forming method of memory as described in claim 1, which is characterized in that cover described in the first adjustment layer
The thickness value of the part of one pattern layer side wall in this second direction is less than first groove in this second direction
The half of width value.
7. the forming method of memory as described in claim 1, which is characterized in that the first direction and second direction have
One acute angle.
8. the forming method of memory as claimed in claim 7, which is characterized in that the angle of the acute angle between 5 °~
Between 85 °.
9. the forming method of memory as described in claim 1, which is characterized in that described first turn of the pattern transfer layer
The hardness range of shifting layer and second transfer layer is between 1HV~10HV.
10. the forming method of memory as claimed in claim 9, which is characterized in that the material of first transfer layer is nitrogen
SiClx, the material of second transfer layer are carbon.
11. the forming method of memory as described in claim 1, which is characterized in that the thickness of the first adjustment layer between
Between 5nm~30nm.
12. the forming method of memory as claimed in any one of claims 1 to 11, which is characterized in that forming described first
Before adjustment layer, the figure of multiple first pattern layers is defined using photoetching process, and by adjacent two described
The spacing of first groove that one pattern layer is defined in this second direction is more than or equal to 30nm.
13. the forming method of memory as described in claim 1, which is characterized in that the reaction of the densification technique
Property gas includes ozone or carbon monoxide；The densification technique includes being carried out using the high energy light of ultraviolet light or laser
Intensify, and including 800 DEG C~1200 DEG C of hot process annealing treatment process.
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| CN112802796B (en) * | 2019-11-13 | 2024-07-12 | 长鑫存储技术有限公司 | Shallow trench isolation structure, forming method thereof and mask structure |
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| US7998874B2 (en) * | 2006-03-06 | 2011-08-16 | Samsung Electronics Co., Ltd. | Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same |
| KR100790999B1 (en) * | 2006-10-17 | 2008-01-03 | 삼성전자주식회사 | Method of forming fine patterns of semiconductor device using double patterning process |
| CN101312113B (en) * | 2007-05-23 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Method for forming graph |
| CN101345190B (en) * | 2007-07-10 | 2012-05-23 | 旺宏电子股份有限公司 | Method for forming graphic pattern |
| KR100932334B1 (en) * | 2007-11-29 | 2009-12-16 | 주식회사 하이닉스반도체 | Method for forming hard mask pattern of semiconductor device |
| CN101510503A (en) * | 2008-02-15 | 2009-08-19 | 东京毅力科创株式会社 | Pattern forming method, semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
| US8946078B2 (en) * | 2012-03-22 | 2015-02-03 | United Microelectronics Corp. | Method of forming trench in semiconductor substrate |
| CN103594337B (en) * | 2012-08-14 | 2016-05-25 | 中芯国际集成电路制造(上海)有限公司 | Double-patterning method |
| US20150021513A1 (en) * | 2013-07-17 | 2015-01-22 | Yun-jeong Kim | Cmp slurry composition for polishing an organic layer and method of forming a semiconductor device using the same |
| US9972702B2 (en) * | 2014-05-22 | 2018-05-15 | Taiwan Semiconductor Manufacturing Company | Method for non-resist nanolithography |
-
2017
- 2017-03-30 CN CN201711288985.2A patent/CN108054085B/en not_active Expired - Fee Related
- 2017-03-30 CN CN201710203347.XA patent/CN106960784B/en not_active Expired - Fee Related
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| CN106960784A (en) | 2017-07-18 |
| CN106960784B (en) | 2018-06-01 |
| CN108054085A (en) | 2018-05-18 |
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