CN108053857B - NAND FLASH CG grouping method and CG grouping device - Google Patents
NAND FLASH CG grouping method and CG grouping device Download PDFInfo
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Abstract
The invention provides a CG grouping method and a CG grouping device of NAND FLASH, wherein the method comprises the following steps: determining NAND FLASH a memory block to be operated on and a selected word line; distributing a first preset number of upper and lower word lines adjacent to the selected word line in the selected word line and the memory block into a first number of first word line groups, wherein the number of the word lines in each first word line group is the same; each word line in the first number of first word line groups corresponds to one CG line, and other word lines except the first number of first word line groups in the memory block correspond to the same CG line, and all the selectable high voltages required for operating NAND FLASH can be output by each CG line. The invention can greatly reduce the number of LV shift modules required by controlling NAND FLASH to transmit high voltage, thereby reducing the chip area and the chip cost.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a CG grouping method of NAND FLASH and a CG grouping device of NAND FLASH.
Background
In circuit design, generally, global routing is adopted to lay out voltages corresponding to all WLs (word lines) onto WLDRV (word line driver) of each BLK (BLOCK), different BLKs are selected by addresses, and voltages are distributed to corresponding WLs, and the number of the routing for distributing the voltages is named CG lines, and the number of CG lines is the same as the number of WLs in each BLK.
In the prior art, when NAND FLASH is subjected to various read/write/erase operations, various High Voltages (HV) need to be applied to the WLs, and when different HVs are selected under different operations, the voltages corresponding to each WL are likely to be different, that is, each CG line needs to cover all selectable High voltages.
When HV is selected for transmission, a high voltage conversion circuit (Level shift) is required to control GATE voltage of the transmission transistor. If a simple corresponding CG line covers all selectable high voltages, if x high voltages exist, and a BLK has m WLs, then m CG lines exist, in addition, in the design of NAND FLASH, for the convenience of decoding, an odd-even corresponding design is adopted in the decoding of a BLK address, namely an odd number of BLKs corresponds to one set of CG lines, and an even number of BLKs corresponds to one set of lines, so that m x 2 high voltage conversion circuits are needed in total. For example, if a BLK has 64 WLs in total and five high voltages need to be applied to the WLs, the prior art requires 64 × 5 × 2 — 640 voltage conversion circuits in total. In the circuit layout, because the voltage conversion circuit is composed of high-voltage tubes, a large number of voltage conversion circuits occupy a large area, so that the whole chip area in the prior art is large, and the cost is high.
Disclosure of Invention
In view of the above problems, an object of the embodiments of the present invention is to provide a CG grouping method of NAND FLASH and a CG grouping apparatus of NAND FLASH, so as to solve the problems of the prior art that each CG line needs to cover all selectable high voltages, resulting in large overall chip area and high cost.
In order to solve the above problem, an embodiment of the present invention discloses a CG grouping method of NAND FLASH, including the following steps:
determining a memory block to be operated on and a selected word line in the NAND FLASH;
distributing the selected word line and an upper and lower first preset number of word lines adjacent to the selected word line in the memory block into a first number of first word line groups, wherein the number of the word lines in each first word line group is the same;
configuring each word line in the first number of first word line groups to correspond to a CG line, and configuring other word lines in the memory block except the first number of first word line groups to correspond to the same CG line, wherein each CG line can output all selectable high voltages required for operating the NAND FLASH.
Optionally, the first number and the number of word lines in the first word line group are determined according to the following formula:
(n-1)*m>＝2*r
wherein n is the first number, m is the number of word lines in the first word line group, and r is the first preset number.
Optionally, the CG grouping method of NAND FLASH further comprises:
the first number and the number of word lines in the first word line group are adjusted to minimize the number of voltage conversion circuits required for the memory block.
Optionally, the configuring each word line in the first number of first word line groups to correspond to a CG line, and configuring the other word lines in the memory block except for the first number of first word line groups to correspond to the same CG line, where each CG line may output all selectable high voltages required for operating the NAND FLASH, includes:
all selectable high voltages required to operate the NAND FLASH can be output by each CG line, one for each CG line.
In order to solve the above problem, an embodiment of the present invention further discloses an NAND FLASH CG grouping apparatus, including:
a determining module for determining a memory block to be operated in NAND FLASH and a selected word line;
the distribution module is used for distributing the selected word line and the upper and lower first preset number of word lines adjacent to the selected word line in the memory block to a first number of first word line groups, wherein the number of the word lines in each first word line group is the same;
and a configuration module, configured to configure each word line in the first number of first word line groups to correspond to a CG line, and configure other word lines in the memory block except for the first number of first word line groups to correspond to the same CG line, where each CG line may output all selectable high voltages required for operating the NAND FLASH.
Optionally, the first number and the number of word lines in the first word line group are determined according to the following formula:
(n-1)*m>＝2*r
wherein n is the first number, m is the number of word lines in the first word line group, and r is the first preset number.
Optionally, the CG grouping device of NAND FLASH further comprises:
and the adjusting module is used for adjusting the first number and the number of the word lines in the first word line group so as to minimize the number of the voltage conversion circuits required by the storage block.
Optionally, the configuration module includes:
and a high voltage configuration unit, configured to enable each CG line to output all selectable high voltages required for operating the NAND FLASH, one by one.
The embodiment of the invention has the following advantages: when NAND FLASH is operated, because only the upper and lower word lines adjacent to the selected word line need to be applied with special high voltage, and the other word lines only need to be applied with the same voltage according to the operation type (such as read operation, write operation, erase operation), the invention firstly determines NAND FLASH the memory block to be operated and the selected word line, and then distributes the selected word line and the upper and lower first preset number of word lines adjacent to the selected word line in the memory block to the first number of first word line groups, sets the number of word lines in each first word line group to be the same, configures each word line in the first number of first word line groups to correspond to a CG line, and configures the other word lines except the first number of first word line groups in the memory block to correspond to the same CG line, and each CG line can output all selectable high voltages required for NAND FLASH to operate. In this way, the first word line group with the first number, including the selected word line and the upper and lower first preset number of word lines adjacent to the selected word line in the memory block, is used as the special word line group, so that each CG line corresponding to the special word line group can output all selectable high voltages required for operating NAND FLASH, and the other word lines in the memory block are used as the common word line group, so that the same CG line corresponding to the common word line group can output all selectable high voltages required for operating NAND FLASH, thereby greatly reducing the number of voltage conversion circuits required by the memory block, effectively reducing the whole chip area and reducing the cost.
Drawings
Fig. 1 is a flowchart illustrating the steps of an NAND FLASH CG grouping method embodiment of the present invention;
fig. 2 is a flowchart illustrating the steps of an NAND FLASH CG grouping method according to an embodiment of the present invention;
fig. 3 is a block diagram of an embodiment of a CG grouping apparatus at NAND FLASH according to the present invention;
fig. 4 is a block diagram of a CG grouping apparatus according to NAND FLASH of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, a flowchart illustrating steps of an NAND FLASH CG grouping method according to an embodiment of the present invention is shown, which may specifically include the following steps:
in step S10, the memory block to be operated on and the selected word line in NAND FLASH are determined.
In step S10, the operation command NAND FLASH may determine a memory block to be operated in NAND FLASH and a selected word line, where the selected word line is a word line in the memory block to be operated. Specifically, the operation type may be any one of a read operation, a write operation, and an erase operation.
In step S20, the selected word line and the first preset number of upper and lower word lines adjacent to the selected word line in the memory block are allocated to the first number of first word line groups, and the number of word lines in each first word line group is the same.
In particular, the first predetermined number may be determined through a plurality of experiments.
Alternatively, in one embodiment of the present invention, the first number and the number of word lines in the first word line group may be determined according to the following formula:
(n-1)*m>＝2*r
wherein n is a first number, m is the number of word lines in the first word line group, and r is a first preset number.
For example, if r is 8, there are 64 word lines in the memory block, when n is 2, since (2-1) m > is 16, at this time, the selected word line and the upper and lower 8 word lines adjacent to the selected word line in the memory block are in 2 first word line groups, and the number of word lines in each first word line group is greater than or equal to 16; when n is 3, m is 8 because (3-1) m is 16, and at this time, the selected word line and the upper and lower 8 word lines adjacent to the selected word line in the memory block are in 3 first word line groups, and the number of the word lines in each first word line group is greater than or equal to 8; when n is 4, m is 6 because (4-1) m is 16, and at this time, the selected word line and the upper and lower 8 word lines adjacent to the selected word line in the memory block are in 4 first word line groups, and the number of the word lines in each first word line group is greater than or equal to 6; when n is 5, since (5-1) m is 16, m is 4, and at this time, the selected word line and the upper and lower 8 word lines adjacent to the selected word line in the memory block are in 5 first word line groups, and the number of the word lines in each first word line group is greater than or equal to 4.
In step S30, each word line in the first number of first word line groups is configured to correspond to a CG line, and the word lines except the first number of first word line groups in the memory block are configured to correspond to the same CG line, and each CG line can output all selectable high voltages required for operation of NAND FLASH.
For example, assuming that all the selectable high voltages required for operating NAND FLASH are 5 kinds, 5 kinds of selectable high voltages can be output for each CG line (including the CG line corresponding to each word line in the first number of first word line groups and the same CG line corresponding to other word lines in the memory block except for the first number of first word line groups).
Alternatively, referring to fig. 2, in an embodiment of the present invention, the step S30 configuring each word line in the first number of first word line groups to correspond to a CG line, and configuring other word lines in the memory block except for the first number of first word line groups to correspond to the same CG line, and each CG line may output all selectable high voltages required for operating NAND FLASH, and may include the following steps:
step S31, each CG line may output all selectable high voltages required for operation NAND FLASH, one for one, to each CG line.
Specifically, step S31 may output all selectable high voltages required for operating NAND FLASH by configuring each CG line to each CG line one by one through a second number of high voltage selection circuits.
Wherein the number of the second number is determined by the ratio of the total number of the word lines in the memory block to be operated and the number of the CG lines corresponding to the first word line group (equal to the number of the word lines in the first word line group).
For example, if there are 64 word lines in the memory block, when the number of word lines in each first word line group is equal to 16, the number of CG lines corresponding to the first word line group is 16, and the second number is 64/16-4; when the number of the word lines in each first word line group is equal to 8, the number of the CG lines corresponding to the first word line group is 8, and the second number is 64/8 ═ 8; when the number of the word lines in each first word line group is equal to 6, the number of the CG lines corresponding to the first word line group is 6, and the second number is 64/6 ≈ 11; when the number of word lines in each first word line group is set to be equal to 4, the number of CG lines corresponding to the first word line group is 4, and the second number is 64/4-16.
Specifically, each high-voltage selection circuit may include two high-voltage switch tubes, and each high-voltage switch tube needs a high-voltage conversion circuit to control the gate voltage so as to conduct the corresponding high-voltage switch tube. When the high-voltage switch tubes are switched on, the CG lines corresponding to each word line in the first number of first word line groups can output high voltage; the other high-voltage switch tube in the two high-voltage switch tubes is connected with the same CG line corresponding to other word lines except the first number of first word line groups, and when the high-voltage switch tubes are conducted, the same CG line corresponding to other word lines except the first number of first word line groups can output high voltage.
Optionally, referring to fig. 2, in an embodiment of the present invention, the CG grouping method of NAND FLASH may further include:
in step S40, the first number and the number of word lines in the first word line group are adjusted to minimize the number of voltage converting circuits required for the memory block.
For example, if r is 8, there are 64 word lines in the memory block, n is 2/3/4/5, m is 16/8/6/16, and the second number is 4/8/11/16, all the selectable high voltages required for operating NAND FLASH are 5 types, and the decoding of BLK addresses adopts odd-even correspondence design, that is, odd number BLK corresponds to one set of CG traces, and even number BLK corresponds to one set of traces.
For the case where n is 2, m is 16, and the second number is 4, each CG line corresponding to the first number of first word line groups requires 2 × 16 × 5 × 2 — 320 voltage converting circuits, the same CG line corresponding to the other word lines except the first number of first word line groups requires 2 × 5 — 10 voltage converting circuits, the second number of high voltage selecting circuits requires 4 × 2 — 16 voltage converting circuits, and the memory block requires 346 voltage converting circuits in total. For the case where n is 3, m is 8, and the second number is 8, each CG line corresponding to the first number of first word line groups requires 3 × 8 × 5 × 2 to 240 voltage converting circuits, the same CG line corresponding to the other word lines except the first number of first word line groups requires 2 × 5 to 10 voltage converting circuits, the second number of high voltage selecting circuits requires 8 × 2 to 32 voltage converting circuits, and the memory block requires 282 voltage converting circuits in total. For the case where n is 4, m is 6, and the second number is 11, each CG line corresponding to the first number of first word line groups requires 4 × 6 × 5 × 2 to 240 voltage converting circuits, the same CG line corresponding to the other word lines except the first number of first word line groups requires 2 × 5 to 10 voltage converting circuits, the second number of high voltage selecting circuits requires 11 × 2 to 44 voltage converting circuits, and the memory block requires 294 voltage converting circuits in total. For the case where n is 5, m is 16, and the second number is 16, each CG line corresponding to the first number of first word line groups requires 5 × 16 × 5 × 2 to 800 voltage converting circuits, the same CG line corresponding to the other word lines except the first number of first word line groups requires 2 × 5 to 10 voltage converting circuits, the second number of high voltage selecting circuits requires 16 × 2 to 64 voltage converting circuits, and the memory block requires 874 voltage converting circuits in total. As can be seen from the above, when n is 3, m is 8, and the second number is 8, the number of voltage conversion circuits required for the memory block is the minimum.
The method of the embodiment of the invention has the following advantages: when NAND FLASH is operated, because special high voltage is generally applied only to the upper and lower word lines adjacent to the selected word line, and the other word lines only need to apply the same voltage according to the type of operation, the invention firstly determines NAND FLASH the memory block to be operated and the selected word line, and then allocates the upper and lower first preset number of word lines adjacent to the selected word line in the selected word line and the memory block to the first number of word line groups, sets the number of word lines in each first word line group to be the same, configures each word line in the first number of first word line groups to correspond to a CG line, configures other CG lines except the first number of first word line groups in the memory block to correspond to the same CG line, and each CG line can output all selectable high voltages required for NAND FLASH operation. In this way, the first word line group with the first number, including the selected word line and the upper and lower first preset number of word lines adjacent to the selected word line in the memory block, is used as the special word line group, so that each CG line corresponding to the special word line group can output all selectable high voltages required for operating NAND FLASH, and the other word lines in the memory block are used as the common word line group, so that the same CG line corresponding to the common word line group can output all selectable high voltages required for operating NAND FLASH, thereby greatly reducing the number of voltage conversion circuits required by the memory block, effectively reducing the whole chip area and reducing the cost.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Referring to fig. 3, a block diagram of a CG grouping apparatus of NAND FLASH in accordance with an embodiment of the present invention is shown, which may specifically include the following modules:
a determination module 10 for determining NAND FLASH a memory block to be operated on and a selected word line.
The allocating module 20 is configured to allocate the selected word line and the upper and lower first preset number of word lines in the memory block, which are adjacent to the selected word line, to a first number of first word line groups, where the number of word lines in each first word line group is the same.
Alternatively, the first number and the number of word lines in the first word line group may be determined according to the following formula:
(n-1)*m>＝2*r
wherein n is a first number, m is the number of word lines in the first word line group, and r is a first preset number.
And a configuration module 30, configured to configure each word line in the first number of first word line groups to correspond to a CG line, and configure other word lines in the memory block except the first number of first word line groups to correspond to the same CG line, where each CG line may output all selectable high voltages required for operating NAND FLASH.
Optionally, referring to fig. 4, in a specific embodiment of the present invention, the configuration module 30 may include:
and a high voltage configuration unit 301, configured to enable each CG line to output all selectable high voltages required for operating NAND FLASH, one by one.
Specifically, the high voltage configuration unit 301 may include a second number of high voltage selection circuits, and the high voltage configuration unit 301 may configure each CG line to output all selectable high voltages required for operating the pair NAND FLASH through the second number of high voltage selection circuits, one by one.
Optionally, referring to fig. 4, in an embodiment of the present invention, the CG grouping apparatus of NAND FLASH may further include:
and an adjusting module 40, configured to adjust the first number and the number of word lines in the first word line group, so as to minimize the number of voltage converting circuits required by the memory block.
The device of the embodiment of the invention has the following advantages: when NAND FLASH is operated, because special high voltage is generally applied only to the upper and lower word lines adjacent to the selected word line, and the other word lines only need to apply the same voltage according to the type of operation, the invention firstly determines NAND FLASH the memory block to be operated and the selected word line, and then allocates the upper and lower first preset number of word lines adjacent to the selected word line in the selected word line and the memory block to the first number of word line groups, sets the number of word lines in each first word line group to be the same, configures each word line in the first number of first word line groups to correspond to a CG line, configures other CG lines except the first number of first word line groups in the memory block to correspond to the same CG line, and each CG line can output all selectable high voltages required for NAND FLASH operation. In this way, the first word line group with the first number, including the selected word line and the upper and lower first preset number of word lines adjacent to the selected word line in the memory block, is used as the special word line group, so that each CG line corresponding to the special word line group can output all selectable high voltages required for operating NAND FLASH, and the other word lines in the memory block are used as the common word line group, so that the same CG line corresponding to the common word line group can output all selectable high voltages required for operating NAND FLASH, thereby greatly reducing the number of voltage conversion circuits required by the memory block, effectively reducing the whole chip area and reducing the cost.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The NAND FLASH CG grouping method and NAND FLASH CG grouping device provided by the present invention are described in detail above, and specific examples are applied herein to illustrate the principles and embodiments of the present invention, and the above description of the embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A CG grouping method of NAND FLASH, comprising the steps of:
determining a memory block to be operated on and a selected word line in the NAND FLASH;
distributing a first preset number of word lines adjacent to the selected word line in the selected word line and the memory block to a first number of first word line groups, wherein the number of the word lines in each first word line group is the same;
configuring each word line in the first number of first word line groups to correspond to a CG line, and configuring other word lines in the memory block except the first number of first word line groups to correspond to the same CG line, wherein each CG line can output all selectable high voltages required for operating the NAND FLASH.
2. The method of claim 1, wherein the first number and the number of wordlines in the first wordline group are determined according to the following equation:
(n-1)*m>=2*r
wherein n is the first number, m is the number of word lines in the first word line group, and r is the first preset number.
3. The method of claim 1 or 2, further comprising:
the first number and the number of word lines in the first word line group are adjusted to minimize the number of voltage conversion circuits required for the memory block.
4. The method of claim 1, wherein configuring each word line in the first number of first word line groups to correspond to a CG line, and configuring the word lines in the memory block except the first number of first word line groups to correspond to the same CG line, each CG line outputting all selectable high voltages required for operating NAND FLASH comprises:
all selectable high voltages required to operate the NAND FLASH can be output by each CG line, one for each CG line.
5. An NAND FLASH CG grouping apparatus, comprising:
a determining module for determining a memory block to be operated in NAND FLASH and a selected word line;
the distribution module is used for distributing the selected word line and the first preset number of upper and lower word lines adjacent to the selected word line in the memory block to a first number of first word line groups, wherein the number of the word lines in each first word line group is the same;
and a configuration module, configured to configure each word line in the first number of first word line groups to correspond to a CG line, and configure other word lines in the memory block except for the first number of first word line groups to correspond to the same CG line, where each CG line may output all selectable high voltages required for operating the NAND FLASH.
6. The apparatus of claim 5, wherein the first number and the number of word lines in the first word line group are determined according to the following equation:
(n-1)*m>=2*r
wherein n is the first number, m is the number of word lines in the first word line group, and r is the first preset number.
7. The apparatus of claim 5 or 6, further comprising:
and the adjusting module is used for adjusting the first number and the number of the word lines in the first word line group so as to minimize the number of the voltage conversion circuits required by the storage block.
8. The apparatus of claim 5, wherein the configuration module comprises:
and a high voltage configuration unit, configured to enable each CG line to output all selectable high voltages required for operating the NAND FLASH, one by one.
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| CN101802925A (en) * | 2007-09-14 | 2010-08-11 | 桑迪士克股份有限公司 | Control gate line architecture |
| CN105830165A (en) * | 2013-12-17 | 2016-08-03 | 桑迪士克科技有限责任公司 | Optimizing pass voltage and initial program voltage based on performance of non-volatile memory |
| CN106205705A (en) * | 2015-04-29 | 2016-12-07 | 旺宏电子股份有限公司 | A kind of operational approach of NAND gate array |
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