CN108039371A - LDMOS transistor and its manufacture method - Google Patents
LDMOS transistor and its manufacture method Download PDFInfo
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- CN108039371A CN108039371A CN201711245171.0A CN201711245171A CN108039371A CN 108039371 A CN108039371 A CN 108039371A CN 201711245171 A CN201711245171 A CN 201711245171A CN 108039371 A CN108039371 A CN 108039371A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
This disclosure relates to lateral diffusion metal oxide semiconductor (LDMOS) transistor and its manufacture method.One of embodiment provides a kind of ldmos transistor, it includes：Substrate, in the substrate formed with channel region, source area, drain region and the drift region between channel region and drain region；And dielectric layer, it is placed at least a portion of drift region, and directly contacted with the main surface of substrate, wherein the dielectric layer carries electric charge so that forming corresponding induction region in drift region under the dielectric layer, the induction region has the conduction type opposite with drift region.
Description
Technical field
This disclosure relates to semiconductor applications, more particularly to lateral diffusion metal oxide semiconductor (Laterally
Diffused Metal Oxide Semiconductor, are abbreviated as LDMOS) transistor.
Background technology
The critical performance parameters of ldmos transistor mainly have two：Breakdown voltage (breakdown voltage) and conducting
Resistance (on-state resistance).In ldmos transistor field, the breakdown voltage of higher is pursued always and lower is led
Be powered resistance.
Therefore there is the demand for new technology.
The content of the invention
One purpose of the disclosure is to provide a kind of structure of new ldmos transistor and corresponding manufacture method.
According to the first aspect of the disclosure, there is provided a kind of ldmos transistor, it includes：Substrate, in the substrate formed with
Channel region, source area, drain region and the drift region between channel region and drain region；And dielectric layer, it is placed on drift region
At least a portion on, and directly contacted with the main surface of substrate, wherein the dielectric layer with electric charge so that in institute
State and corresponding induction region is formed in the drift region under dielectric layer, the induction region has the conductive-type opposite with drift region
Type.
According to the second aspect of the disclosure, there is provided a kind of method for manufacturing ldmos transistor, it includes：Substrate is provided,
Formed with channel region, source area, drain region and the drift region between channel region and drain region in the substrate；And with
Dielectric layer is formed on the corresponding substrate of at least a portion of drift region, the main surface of the dielectric layer and substrate directly connects
Touch, wherein the dielectric layer carries electric charge so that forming corresponding induction region in drift region under the dielectric layer,
The induction region has the conduction type opposite with drift region.
By referring to the drawings to the present invention exemplary embodiment detailed description, further feature of the invention and its
Advantage will become more apparent from.
Brief description of the drawings
The attached drawing of a part for constitution instruction describes embodiment of the disclosure, and is used to solve together with the description
Release the principle of the disclosure.
Referring to the drawings, according to following detailed description, the disclosure can be more clearly understood, wherein：
Fig. 1 shows the basic structure of the ldmos transistor of the prior art.
Fig. 2A -2D show the section of the various exemplary constructions of the ldmos transistor according to disclosure exemplary embodiment
Figure.
Fig. 3 shows the flow chart of the ldmos transistor manufacture method according to disclosure exemplary embodiment.
Fig. 4 A-4C are respectively illustrated is manufacturing the one of ldmos transistor according to one exemplary embodiment of the disclosure
Device schematic cross-section at the exemplary each step of method.
Note that in embodiments described below, same reference numeral is used in conjunction between different attached drawings sometimes
Come the part for representing same section or there is identical function, and omit its repeat specification.In the present specification, using similar mark
Number and letter represent similar terms, therefore, once be defined in a certain Xiang Yi attached drawing, then in subsequent attached drawing be not required pair
It is further discussed.
In order to make it easy to understand, position, size and scope of each structure shown in attached drawing etc. etc. does not indicate that reality sometimes
Position, size and scope etc..Therefore, disclosed invention is not limited to position, size and scope disclosed in attached drawing etc. etc..
Embodiment
It is described in detail the various exemplary embodiments of the disclosure below with reference to accompanying drawings.It should be noted that：Unless in addition have
Body illustrates that the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
The description only actually at least one exemplary embodiment is illustrative to be never used as to the disclosure below
And its application or any restrictions that use.That is, semiconductor device and its manufacture method herein is with exemplary
Mode is shown, to illustrate the different embodiments of the structures and methods in the disclosure.It will be understood by those skilled in the art, however, that
They are merely illustrative the exemplary approach of the invention that can be used for implementing, rather than the mode of limit.In addition, attached drawing need not be by
Ratio is drawn, some features may be exaggerated to show the details of specific component.
It may be not discussed in detail for technology, method and apparatus known to person of ordinary skill in the relevant, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part for specification.
In shown here and discussion all examples, any occurrence should be construed as merely exemplary, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
Fig. 1 shows the basic structure of the ldmos transistor of the prior art, here, coming by taking N-type ldmos transistor as an example
Illustrate.
According to RESURF (REduced SURface Field, reduce surface field) principle, traditional ldmos transistor exists
Drain side includes drift region (such as N-type trap 102 in Fig. 1) and LOCOS (the local oxidation of wherein formed
Silicon, local oxidation of silicon) or STI (shallow trench isolation, shallow trench isolation) structure (such as in Fig. 1
LOCOS/STI 103), so that breakdown voltage be greatly improved, and ensure feasible conducting resistance.When in grid 108 and source
When applying enough forward voltages between pole 106, the transistor turns are square into channel region 109 under the gate, at this time electronics
The direction of arrow that (i.e. majority carrier) is shown along in Fig. 1 flows to drain electrode (drain region 104 as shown in Figure 1) from source electrode.This
There is the demand that continuous improvement breakdown voltage reduces conducting resistance at the same time in field, therefore there is also various technologies to change
Into the structure of the conventional LDMOS transistor.
And present inventor has found by research, some dielectric substances (such as high dielectric constant material is (also referred to as
High-g value)) it can be fettered wherein or accumulated charge due to the property (such as defect, dangling bonds) of its own.When draining
As being formed on the substrate surface of drift region during dielectric material layer, there is electric charge due to wherein accumulating, the electric charge of the accumulation will
Electrical opposite charge attraction in substrate is to the dielectric layer/substrate interface (i.e. substrate main surface), so that on drift region
Portion forms the region (also referred herein as " induction region ") of a films of opposite conductivity.The region of the films of opposite conductivity can influence
The electric field distribution of drift region, so that conducting resistance can be reduced while improving breakdown voltage.
In view of the studies above, present inventor proposes a kind of new LDMOS transistor structure, wherein not having to
LOCOS or sti structure are formed in drain-drift region, but is formed in the substrate main surface of at least a portion drift region and carries phase
Answer the dielectric layer of electric charge so that the dielectric layer senses the region formed with drift region films of opposite conductivity in drift region.
Therefore, the induction region, drift region and together form with the region of drift region films of opposite conductivity below drift region
Double RESURF (double RESURF) structure, it improves breakdown voltage and conducting resistance at the same time.Further, since the new construction
Drain-drift region in there is no LOCOS or STI, therefore the carrier flow path (i.e. current path) between source electrode and drain electrode
Shorten, This further reduces conducting resistance.
Specifically, according to the disclosure on one side, it is proposed that a kind of ldmos transistor, it includes：Substrate, in substrate
In formed with channel region, source area, drain region and the drift region between channel region and drain region；And dielectric layer, place
Directly contacted at least a portion of drift region, and with the main surface of substrate, wherein the dielectric layer carry electric charge so that
Obtain and corresponding induction region is formed in the drift region under the dielectric layer, the induction region has opposite with drift region lead
Electric type.
The technology of the disclosure is elaborated below in conjunction with attached drawing.
Fig. 2A -2D show schematically cutting for the various structures of the ldmos transistor according to disclosure exemplary embodiment
Face figure.It note that and illustrated herein by taking N-type ldmos transistor as an example, but those skilled in the art can manage
Solution, the present invention are also fully applicable for p-type ldmos transistor, are only inverted with by the conduction type of each doped region, make dielectric layer
With positive charge.
As shown in Figure 2 A, which includes P type substrate 201.The substrate 201 can be by being suitable for LDMOS crystal
Any semi-conducting material (Si, SiC, SiGe etc.) of pipe is made.In other embodiments, substrate 201 can also be
The various compound substrates such as silicon-on-insulator (SOI), silicon germanium on insulator.P type substrate mean in substrate be used for form transistor
The semiconductor portion (for example, semiconductor layer on insulator) of active area is that p-type is adulterated.Those skilled in the art understand substrate
It is not any way limited, but can be made choice according to practical application.In addition to the component shown in figure, in substrate 201
Can also be formed with other components, for example, the other components formed in early stage or post-processing steps.
In the substrate 201 formed with channel region 209, source area 206, drain region 204 and channel region 209 with drain electrode
Drift region 202 between area 204.Form gate structure on 209 corresponding substrate of channel region, i.e., gate dielectric layer 207 and
Gate electrode 208 thereon.Source area 206, drain region 204 and gate electrode 208 have contact hole and follow-up metal connecting line
Extraction is gone, as S, D and G in Fig. 2A are illustrated, so that convenient apply voltage.Those skilled in the art understand, channel region
209 just form real raceway groove in transistor turns (when such as to applying suitable voltage between grid G and source S).One
In a little embodiments, channel region 209 is exactly a part for P type substrate 201 in fact, this section substrate is not carried out any other
The processing of doping etc., for no other reason than that being used as raceway groove when device works just is known as channel region.Channel region 209 is in fig. 2
A shape also simply signal, is not meant to that raceway groove will become so during device work.In other embodiments, channel region
209 can carry out the processing such as being lightly doped and be formed to this part of P type substrate 201 as needed.In addition, as shown in Figure 2 A, drift
Move area 202 to be formed by N-type trap, the drain region 204 of extraction electrode is the heavily doped region (N+ areas) being formed in the N-type trap 202.This
Field technology personnel also understand that the structure such as position of drift region 202 and drain region 204 is not limited to this.
The ldmos transistor further includes the dielectric layer 210 in a part for drift region 202.210 quilt of dielectric layer
It is formed in the main surface of substrate 201, and is directly contacted with the main surface of substrate 201.Herein, the main surface of substrate means
Two vertical with the thickness direction major surfaces of the substrate (for example, Silicon Wafer).As shown in Figure 2 A, dielectric layer 210 carries
Negative electrical charge, so as to lure the hole in drift region 202 so that form corresponding induction region 211, the induction region thereunder
211 alternatively referred to as sense P-type layer.The sensing P-type layer 211 and P type substrate 201 clip N-type drift region 202, so as to be formed
Double RESURF structures, which improve the breakdown voltage and conducting resistance of the transistor.In addition, by comparing Fig. 2A and Fig. 1
In electronics flow path (as shown by the arrow) as can be seen that due to not having in the drain-drift region of the new construction
LOCOS or STI, therefore the carrier flow path (i.e. current path) between source electrode and drain electrode shortens, this is further reduced
Conducting resistance.
In some embodiments, the doping concentration of drift region 202 can be 1e11~1e17cm-3.In some embodiment party
In formula, the width along channel direction (horizontal direction i.e. in figure) of dielectric layer 210 can be in 0.1 to 1000 microns of scope
It is interior.In some embodiments, which can be formed by any negatively charged high-g value, which can
With selected from least one of following：HfO、HfSiO、HfTaO、HfTiO、HfZrO、Al2O3、ZrO2、HfO2-Al2O3Deng.Can be with
The dielectric layer 210 is formed by chemical vapor deposition (CVD), physical vapour deposition (PVD) (PVD) or other suitable technologies.Ability
Field technique personnel understand, the material and forming method not limited to this of dielectric layer of the invention, but can also include ability
Any other suitable material and production technology known to domain, only dielectric layer to be formed with corresponding electric charge (negative electrical charge or
Positive charge).Preferably, the thickness of the dielectric layer 210 is in the range of 10 to 500 nanometers.
As it was previously stated, the conduction type in each region in Fig. 2A is inverted, dielectric layer 210 is carried positive charge, just become
Into the p-type LDMOS transistor structure of the application present invention.That is, in a kind of p-type LDMOS crystal according to the present invention
In pipe structure, substrate 201 is changed into N-type substrate, and drift region 202 is p-type trap, and source area 206 and drain region 204 are P+ regions, electricity
The electric charge that dielectric layer 210 carries is positive charge, and the conduction type for the induction region 211 being correspondingly formed is N-type.Other structures or work
Skill parameter can refer to the above description to N-type ldmos transistor.
As the replacement of the structure of Fig. 2A, as shown in Figure 2 B, gate structure 207,208 can be with dielectric layer 210
At least a portion.In some embodiments, gate dielectric layer 207 is formed by silica, and gate electrode 208 is by more
Crystal silicon is formed, but those skilled in the art understand, gate structure not limited to this of the invention, but any can be applied to
The gate structure of ldmos transistor is all suitable for, such as gate dielectric layer 207 can be high-k material layer, and gate electrode 208
It can be metal gate.In the structure shown in Fig. 2 B, since gate electrode 208 covers at least one of dielectric layer 210,
Therefore the grid voltage applied thereon can influence the electric field under the dielectric layer of covering part, may increase Portions of layer
The positive charge in induction region under 210, thereby assists in the breakdown voltage for further increasing the transistor and reduces its conducting
Resistance.
In addition, as shown in Figure 2 B, a p-type heavily doped region (P+ areas) 205 can also be formed in P type substrate 201, so as to
Come to apply potential to substrate in follow-up extraction electrode (" B " shown in figure).In many cases, the B electrodes and source electrode (S poles)
Short circuit is together.
As it was previously stated, in the structure shown in Fig. 2A, substrate 201 is P type substrate, and channel region is by one of P type substrate 201
Divide and formed, drift region and drain region are formed by the N-type trap 202 in P type substrate.But those skilled in the art are understood that, this
Invention not limited to this.The technology of the present invention can be adapted for any other LDMOS transistor structure, as long as former according to the present invention
Manage the modification that adaptability is carried out to its structure.
For example, as shown in Figure 2 C, in another structure of N-type ldmos transistor according to the present invention, substrate 201
For P type substrate, but the active area of ldmos transistor is formed in the N-type trap 212 in the P type substrate 201, wherein floating
Move area to be formed by a part for N-type trap 212, drain region 204 is the N-type heavily doped region that is formed in the N-type trap 212, channel region 209
Formed by the part that the PXing Ti areas 213 formed are adulterated in the N-type trap 212, source area 206 is also formed in the PXing Ti areas 213
In.The structure of Fig. 2 C may be particularly well adapted for use in complimentary transistor circuit (that is, will form N-type at the same time in same substrate 201
Ldmos transistor and p-type ldmos transistor), because for ease of each ldmos transistor is respectively formed in respective well region.
Described in when being as previously mentioned Fig. 2 B, in the case where LDMOS is N-type transistor, it can apply bigger than grid voltage
Drain voltage, i.e., grid (G)-drain electrode (D) voltage is negative voltage, so that the potential of the drift region of the lower section of dielectric layer 210
Higher than the potential of the grid of the top of dielectric layer 210, electric field from bottom to top is produced, so that the sensing under adding dielectric layer
Positive charge in region 211, thereby assists in the breakdown voltage for further increasing the transistor and reduces its conducting resistance.
Similarly, same structure can also be applied to p-type ldmos transistor.In the case where LDMOS is P-type transistor,
The grid voltage bigger than drain voltage can be applied, i.e. gate-drain voltages are positive voltage, so that the drift below dielectric layer
The potential in area is moved less than the potential of the grid above dielectric layer, electric field from top to bottom is produced, so as to add dielectric layer
Under induction region in negative electrical charge, thereby assist in further increase the transistor breakdown voltage and reduce its electric conduction
Resistance.
In addition, in some embodiments, the replacement in addition to gate electrode or as gate electrode can be in electricity
Extra electrode is set on dielectric layer, for applying as described above to induction region in combination or individually with gate electrode
Favourable electric field, so as to further increase the breakdown voltage of the transistor and reduce its conducting resistance.It is in addition, preferred real at some
Apply in mode, multiple extra electrodes can be set on the dielectric layer, so that by controlling the plurality of additional electrode and optional
Gate electrode application voltage, non-uniform induction region can be produced under dielectric layer, is thus formed in drift region
Electric field evenly, obtains the breakdown voltage of higher.
For example, as shown in Figure 2 D, in addition to gate electrode 208, extra electrode is provided with also on dielectric layer 210
V, can be applied independently control voltage to electrode V.It will be understood by those skilled in the art that electrode V can with more than one,
But it can be arranged as required to multiple.Alternately, the gate electrode 208 in Fig. 2 D can not dielectric layer 210, i.e.,
Extra one or more electrode V are only set on dielectric layer 210.
Fig. 3 shows the flow chart of the ldmos transistor manufacture method 300 according to disclosure exemplary embodiment.Above
Corresponding feature is readily applicable to reference to the described contents of Fig. 2A -2D.
Specifically, as shown in figure 3, at step 310, there is provided substrate, formed with channel region, source electrode in the substrate
Area, drain region and the drift region between channel region and drain region.
As it was previously stated, structure and formation process of substrate and these active areas etc. are unrestricted, but ability can be used
LDMOS transistor structure known to domain and technique.Above have been combined Fig. 2A -2D and describe Partial Feature, details are not described herein.
At step 320, dielectric layer, the dielectric are formed on substrate corresponding with least a portion of drift region
Layer is directly contacted with the main surface of substrate, wherein the dielectric layer with electric charge so that drift under the dielectric layer
Corresponding induction region is formed in area, the induction region has the conduction type opposite with drift region.
In some embodiments, which is formed by high dielectric constant material, then forms the step of dielectric layer
Suddenly include：Deposit high dielectric constant material layer on substrate, then by photoetching and etching processing by high dielectric constant material layer
It is patterned so as to be only remained on substrate corresponding with least a portion of drift region, so as to form the dielectric layer.
In some embodiments, which can be formed by least one of following：HfO、
HfSiO、HfTaO、HfTiO、HfZrO、Al2O3、ZrO2、HfO2-Al2O3。
In some embodiments, the thickness of dielectric layer can be in the range of 10 to 500 nanometers.
In some embodiments, the width along channel direction of dielectric layer can be in 0.1 to 1000 microns of scope
It is interior.
Alternatively, at step 330, after formation of the dielectric layer substrate main surface and dielectric layer at least one
Gate structure is formed on part.
For example, first depositing one layer of gate dielectric material and one layer of gate electrode material in substrate, then pass through light
Carve with etching processing to be patterned, so as to form the gate structure of an at least part for dielectric layer.
The present invention in order to more complete and comprehensive is understood, below by by taking the N-type LDMOS transistor structure shown by Fig. 2 B as an example
A specific example of the ldmos transistor manufacture method according to one exemplary embodiment of the disclosure is described in detail.It please note
Meaning, this example are not intended to be construed as limiting the invention.For example, the present invention is not limited in the LDMOS shown by Fig. 2 B
The concrete structure of transistor, but all ldmos transistors for having same requirements or design consideration are all suitable for.Above in conjunction with figure
The described contents of 2A-2D and Fig. 3 are readily applicable to corresponding feature.
Fig. 4 A-4C respectively illustrate the device schematic cross-section at the exemplary each step of this method.
At Fig. 4 A, each active of the transistor is formd in P type substrate 201 for example, by modes such as ion implantings
Area, such as source area 206, drain region 204, the N-type trap 202 for being mainly used as drift region, underlayer electrode draw-out area 205.
Then, at Fig. 4 B, a high dielectric constant material layer is deposited by techniques such as CVD or PVD on the substrate 201,
Then by photoetching and etching processing by the high dielectric constant material pattern layers, so as to be only remained in drift region 202 extremely
On few a part of corresponding substrate, so as to form the dielectric layer 210 in figure.Since the dielectric layer 210 carries negative electrical charge, because
This forms corresponding induction region 211 in drift region 202 under it.The high dielectric constant material for example can be：HfO、
HfSiO、HfTaO、HfTiO、HfZrO、Al2O3、ZrO2、HfO2-Al2O3Deng.
Then, at Fig. 4 C, deposited by techniques such as CVD or PVD on substrate 201 one layer of gate dielectric material and
One layer of gate electrode material, then patterns the two by photoetching and etching processing, is situated between so as to form covering electricity
The gate dielectric layer 207 and gate electrode 208 of a part for matter layer 210.
It will be understood by those skilled in the art that in addition to technique and structure as shown in Fig. 4 A-4C, the disclosure further includes shape
Other any techniques and structure necessary into ldmos transistor.
Word "front", "rear", " top ", " bottom " in specification and claim, " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word so used
Language is interchangeable in appropriate circumstances so that embodiment of the disclosure described herein, for example, can with this institute
Those of description show or other are orientated in other different orientations and operate.
As used in this, word " exemplary " means " being used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other implementations in any implementation of this exemplary description
Preferable or favourable.Moreover, the disclosure is from above-mentioned technical field, background technology, the content of the invention or embodiment
Given in the theory that is any stated or being implied that goes out limited.
As used in this, word " substantially " mean comprising by design or manufacture the defects of, device or element appearance
Any small change caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other actual Considerations being likely to be present in actual implementation with perfect or preferable situation
Between difference.
In addition, just to the purpose of reference, can with the similar terms such as " first " used herein, " second ", and
And thus it is not intended to limit.For example, unless clearly indicated by the context, be otherwise related to structure or element word " first ", "
Two " do not imply order or sequence with other such digital words.
It should also be understood that one word of "comprises/comprising" is as used herein, illustrate that there are pointed feature, entirety, step
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or the one or more of the other feature of increase, entirety, step, behaviour
Work, unit and/or component and/or combinations thereof.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering obtain object all modes
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembling ", and/or " order " object etc..
Foregoing description can indicate to be " connected " or " coupling " element together or node or feature.As used herein
, unless otherwise expressly noted, " connection " means an element/node/feature with another element/node/feature in electricity
Above, it is directly connected mechanically, in logic or in other ways (or direct communication).Similarly, unless otherwise expressly noted,
" coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine
On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may be not direct
Connection is also such.That is, " coupling " is intended to encompass element or the direct of further feature links and link indirectly, including profit
With the connection of one or more intermediary elements.
It should be appreciated by those skilled in the art that the border between aforesaid operations is merely illustrative.Multiple operations
Single operation can be combined into, single operation can be distributed in additional operation, and operate can at least portion in time
Divide and overlappingly perform.Moreover, alternative embodiment can include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are changed, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
In addition, embodiment of the present disclosure can also include the example below：
1st, a kind of ldmos transistor, it is characterised in that including：
Substrate, in the substrate formed with channel region, source area, drain region and the drift between channel region and drain region
Area；And
Dielectric layer, is placed at least a portion of drift region, and is directly contacted with the main surface of substrate,
Wherein described dielectric layer carries electric charge so that forming corresponding sensing in drift region under the dielectric layer
Region, the induction region have the conduction type opposite with drift region.
2nd, the ldmos transistor according to 1, it is characterised in that the dielectric layer is formed by high dielectric constant material.
3rd, the ldmos transistor according to 2, it is characterised in that the high dielectric constant material in following extremely
Few one kind：HfO、HfSiO、HfTaO、HfTiO、HfZrO、Al2O3、ZrO2、HfO2-Al2O3。
4th, the ldmos transistor according to 1, it is characterised in that the thickness of the dielectric layer is at 10 to 500 nanometers
In the range of.
5th, the ldmos transistor according to 1, it is characterised in that the dielectric layer exists along the width of channel direction
In the range of 0.1 to 1000 microns.
6th, the ldmos transistor according to 1, it is characterised in that the conduction type of the drift region is N-type, and is adulterated
Concentration is 1e11~1e17cm-3。
7th, the ldmos transistor according to 1, it is characterised in that source area, drain region and the conduction type of drift region are
N-type, the electric charge that dielectric layer carries are negative electrical charge, and the conduction type of induction region is p-type.
8th, the ldmos transistor according to 1, it is characterised in that source area, drain region and the conduction type of drift region are
P-type, the electric charge that dielectric layer carries are positive charge, and the conduction type of induction region is N-type.
9th, the ldmos transistor according to 1, it is characterised in that the gate structure above substrate is further included, it is described
At least a portion of gate structure dielectric layer.
10th, the ldmos transistor according to 1, it is characterised in that substrate is P type substrate, and channel region is by P type substrate
A part is formed, and drift region and drain region are formed by the N-type trap in P type substrate.
11st, the ldmos transistor according to 1, it is characterised in that substrate is P type substrate, the ldmos transistor
Active area is both formed in the N-type trap in P type substrate, wherein channel region by the N-type trap ZhongPXing Ti areas a part of shape
Into source area is formed in the PXing Ti areas.
12nd, a kind of method for manufacturing ldmos transistor, it is characterised in that including：
Substrate is provided, formed with channel region, source area, drain region and between channel region and drain region in the substrate
Drift region；And
Dielectric layer, the master of the dielectric layer and substrate are formed on substrate corresponding with least a portion of drift region
Surface directly contacts,
Wherein described dielectric layer carries electric charge so that forming corresponding sensing in drift region under the dielectric layer
Region, the induction region have the conduction type opposite with drift region.
13rd, the method according to 12, it is characterised in that described the step of forming dielectric layer includes：Sink on substrate
Product high dielectric constant material layer, then by photoetching and etching processing by high dielectric constant material pattern layers so that only retaining
On substrate corresponding with least a portion of drift region, so as to form dielectric layer.
14th, the method according to 13, it is characterised in that the high dielectric constant material layer is by least one of following
Formed：HfO、HfSiO、HfTaO、HfTiO、HfZrO、Al2O3、ZrO2、HfO2-Al2O3。
15th, the method according to 12, it is characterised in that scope of the thickness of the dielectric layer at 10 to 500 nanometers
It is interior.
16th, the method according to 12, it is characterised in that the dielectric layer is arrived along the width of channel direction 0.1
In the range of 1000 microns.
17th, the method according to 12, it is characterised in that the conduction type of the drift region is N-type, and doping concentration is
1e11~1e17cm-3。
18th, the method according to 12, it is characterised in that source area, drain region and the conduction type of drift region are N-type,
The electric charge that dielectric layer carries is negative electrical charge, and the conduction type of induction region is p-type.
19th, the method according to 12, it is characterised in that source area, drain region and the conduction type of drift region are p-type,
The electric charge that dielectric layer carries is positive charge, and the conduction type of induction region is N-type.
20th, the method according to 12, it is characterised in that be additionally included in the main surface of substrate after formation of the dielectric layer
Gate structure is formed with least a portion of dielectric layer.
21st, the method according to 12, it is characterised in that substrate is P type substrate, channel region by P type substrate a part
Formed, drift region and drain region are formed by the N-type trap in P type substrate.
22nd, the method according to 12, it is characterised in that substrate is P type substrate, the active area of the ldmos transistor
It is both formed in the N-type trap in P type substrate, wherein channel region is formed by the part in the N-type trap ZhongPXing Ti areas, source electrode
Area is formed in the PXing Ti areas.
Although some specific embodiments of the disclosure are described in detail by example, the skill of this area
Art personnel it should be understood that above example merely to illustrate, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out to embodiment without departing from the scope and spirit of the disclosure.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
- A kind of 1. ldmos transistor, it is characterised in that including：Substrate, in the substrate formed with channel region, source area, drain region and the drift region between channel region and drain region；With AndDielectric layer, is placed at least a portion of drift region, and is directly contacted with the main surface of substrate,Wherein described dielectric layer carries electric charge so that forming corresponding induction region in drift region under the dielectric layer, The induction region has the conduction type opposite with drift region.
- 2. ldmos transistor according to claim 1, it is characterised in that the dielectric layer is by high dielectric constant material Formed.
- 3. ldmos transistor according to claim 2, it is characterised in that the high dielectric constant material is in as follows At least one：HfO、HfSiO、HfTaO、HfTiO、HfZrO、Al2O3、ZrO2、HfO2-Al2O3。
- 4. ldmos transistor according to claim 1, it is characterised in that the thickness of the dielectric layer is received 10 to 500 In the range of rice.
- 5. ldmos transistor according to claim 1, it is characterised in that the width along channel direction of the dielectric layer Degree is in the range of 0.1 to 1000 microns.
- 6. ldmos transistor according to claim 1, it is characterised in that the conduction type of the drift region is N-type, and Doping concentration is 1e11~1e17cm-3。
- 7. ldmos transistor according to claim 1, it is characterised in that source area, drain region and the conductive-type of drift region Type is N-type, and the electric charge that dielectric layer carries is negative electrical charge, and the conduction type of induction region is p-type.
- 8. ldmos transistor according to claim 1, it is characterised in that source area, drain region and the conductive-type of drift region Type is p-type, and the electric charge that dielectric layer carries is positive charge, and the conduction type of induction region is N-type.
- 9. ldmos transistor according to claim 1, it is characterised in that the gate structure above substrate is further included, At least a portion of the gate structure dielectric layer.
- 10. ldmos transistor according to claim 1, it is characterised in that substrate is P type substrate, and channel region is served as a contrast by p-type The part formation at bottom, drift region and drain region are formed by the N-type trap in P type substrate.
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