CN108039324B - Packaging module and forming method thereof - Google Patents

Packaging module and forming method thereof Download PDF

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Publication number
CN108039324B
CN108039324B CN201711097151.3A CN201711097151A CN108039324B CN 108039324 B CN108039324 B CN 108039324B CN 201711097151 A CN201711097151 A CN 201711097151A CN 108039324 B CN108039324 B CN 108039324B
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chip
conductive substrate
layer
hole
forming
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CN201711097151.3A
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CN108039324A (en
Inventor
廖小景
侯召政
王军鹤
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Huawei Digital Power Technologies Co Ltd
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Xian Huawei Technologies Co Ltd
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Priority to CN201711097151.3A priority Critical patent/CN108039324B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The embodiment of the application discloses a packaging module and a forming method thereof, wherein the method comprises the following steps: fixing the first conductive substrate and the second conductive substrate by using the first fixing layer to form a laminated structure; forming a first through hole at a position of the second conductive substrate corresponding to the first preset region, and forming a second through hole at a position corresponding to the second preset region; forming a third through hole at a position of the first conductive substrate corresponding to the first preset area; removing the part of the first fixing layer positioned between the first through hole and the third through hole to form a first cavity, and removing the part of the first fixing layer positioned in the second through hole; the first chip is fixed in the first cavity, and the second chip is fixed in the second through hole, so that chips with different thicknesses are installed through the first cavity and the second through hole with different depths, and the problem that the conventional packaging module does not support embedding of multiple chips with different thicknesses is solved. And the forming method can make the packaging module balanced up and down, and avoid the warping phenomenon.

Description

Packaging module and forming method thereof
Technical Field
The present application relates to the field of packaging technologies, and in particular, to a package module and a method for forming the same.
Background
With the development of electronic products, the size of a package module is smaller and higher, and therefore, the technology for embedding a chip into a substrate and realizing interconnection is more and more rapidly developed. However, in the process of embedding a plurality of chips into a package module at the same time, because different height differences may exist among the plurality of chips, the package module has blind holes with different depths, and when the thickness of the chip is large (for example, greater than 80 μm), the blind hole copper plating filling operation cannot be realized due to the limit of the process capability, so that the current package module does not support the embedding of the plurality of chips with different thicknesses.
Disclosure of Invention
In order to solve the above technical problem, the embodiments of the present application provide the following technical solutions:
In a first aspect, an embodiment of the present application provides a method for forming a package module, including:
Fixing a first conductive substrate and a second conductive substrate by using a first fixing layer to form a laminated structure in which the first conductive substrate, the first fixing layer and the second conductive substrate are laminated in sequence, wherein the first fixing layer is an insulating fixing layer;
forming a first through hole at a position of the second conductive substrate corresponding to the first preset region, and forming a second through hole at a position corresponding to the second preset region;
forming a third through hole at a position of the first conductive substrate corresponding to the first preset area;
Removing a part of the first fixing layer, which is positioned between the first through hole and the third through hole, to form a first chamber, and removing a part of the first fixing layer, which is positioned in the second through hole;
Forming a first supporting layer on one side of the first conductive substrate, which is far away from the second conductive substrate;
Fixing a first chip in the first chamber and fixing a second chip in the second through hole, wherein the thickness of the first chip is larger than that of the second chip, and the first chip and the second chip are electrically insulated;
removing the first support layer;
Forming a first protective layer on one side of the first conductive substrate, which is far away from the second conductive substrate, and one side of the second conductive substrate, which is far away from the first conductive substrate;
And forming a plurality of connecting holes in the first protective layer, filling the connecting holes, and forming a plurality of connecting structures, wherein the connecting structures are used for being electrically connected with the first chip or the second chip.
According to the packaging module forming method provided by the embodiment of the application, the first conductive substrate, the first fixing layer and the second conductive substrate are firstly formed into the laminated structure, and then the first cavity and the second through hole with different depths are formed in the laminated structure, so that chips with different thicknesses can be conveniently installed, and the problem that the conventional packaging module does not support embedding of multiple chips with different thicknesses is solved.
Moreover, in the method for forming the encapsulation module provided by the embodiment of the application, when the first conductive substrate deviates from the second conductive substrate and the second conductive substrate deviates from the first conductive substrate, a first protection layer is formed on one side of the first conductive substrate, because the first cavity penetrates through the laminated structure, the difference between the thickness of the first protection layer on one side of the first conductive substrate deviating from the second conductive substrate and the thickness of the first protection layer on one side of the second conductive substrate deviating from the first conductive substrate is not large, so that the encapsulation module can be balanced up and down, and the warping phenomenon is avoided.
In one implementation, the removal process of the first fixed layer removal part is laser removal.
In one implementation, the first support layer is a film layer, such as a frame sealing film.
in one implementation, the first support layer 81 is made of a material that is resistant to high temperatures, such as at least 200 ℃.
in one implementation, when the second chip includes a plurality of chip units electrically insulated from each other, the method further includes, before removing a portion of the first fixing layer located between the first through hole and the third through hole, forming a first chamber, and removing a portion of the first fixing layer located within the second through hole:
and forming a plurality of fourth through holes in a third preset area in the first conductive substrate, wherein the projection of the fourth through holes on the second chip is positioned in an area between adjacent chip units, so that the area of the first conductive substrate below the second chip is divided into a plurality of mutually insulated conductive blocks, and therefore when each chip unit in the second chip is electrically connected with the conductive block below the chip unit, the mutual insulation among the chip units can still be ensured.
in one implementation, the method further includes, before fixing the second chip in the second via: and forming a first conductive connecting layer on the lower surface of the second through hole so as to reduce the contact resistance between the second chip and the first conductive substrate by using the first conductive connecting layer, improve the electrical connection performance between the second chip and the first conductive substrate, and improve the heat dissipation performance of the packaging module.
in one implementation, the first conductive connection layer is a metal glue layer.
in one implementation, when the second chip includes a plurality of chip units electrically insulated from each other, the first conductive connection layer includes a plurality of first conductive connection regions insulated from each other, and the first conductive connection regions are in one-to-one correspondence with the chip units and electrically connected to the corresponding chip units.
In one implementation, before forming the first support layer on the side of the first conductive substrate facing away from the second conductive substrate, the method further includes: forming a fifth through hole in the second conductive substrate at a position corresponding to a fourth preset area; removing the part of the first fixing layer, which is positioned in the fifth through hole; the method further comprises the following steps of after forming a first supporting layer on one side of the first conductive substrate, which faces away from the second conductive substrate: and fixing a third chip in the fifth through hole, wherein the thickness of the third chip is not more than the height of the fifth through hole so as to support the embedding of more chips.
in one implementation, the second chip is mounted upright and the third chip is mounted upside down; or, the second chip is reversely mounted, and the third chip is normally mounted, so that when the front surface of the second chip and the back surface of the third chip in the packaging module are electrically connected, a current through-flow path between the second chip and the third chip is reduced, and the heat loss of the packaging module is reduced.
In one implementation, the method further includes, before fixing a third chip in the fifth through hole: and forming a second conductive connecting layer on the lower surface of the fifth through hole so as to reduce the contact resistance between the third chip and the first conductive substrate by using the second conductive connecting layer, improve the electrical connection performance between the third chip and the first conductive substrate, and improve the heat dissipation performance of the packaging module.
In one implementation, the second conductive connection layer is a metal glue layer.
in a second aspect, an embodiment of the present application provides a package module, including:
the laminated structure comprises a first conductive substrate, a first fixed layer and a second conductive substrate which are sequentially laminated, wherein the first fixed layer is an insulating fixed layer;
A first chamber penetrating the laminated structure at a first predetermined region;
A second through hole penetrating the second conductive substrate and the first fixing layer in a second preset area;
A first chip fixed in the first chamber;
a second chip fixed to the second through hole, the first chip having a thickness greater than that of the second chip, and the first chip and the second chip being electrically insulated;
The first protective layer is positioned on one side, away from the second conductive substrate, of the first conductive substrate and on one side, away from the first conductive substrate, of the second conductive substrate, and a plurality of connecting holes are formed in the first protective layer;
and the connecting structure is used for being electrically connected with the first chip or the second chip.
the encapsulation module that this application embodiment provided, including the laminated structure that first electrically conductive base plate, first fixed bed and second electrically conductive base plate range upon range of in proper order, and be formed with the first cavity and the second through-hole of the different degree of depth in this laminated structure to install the chip of different thickness, the thickness of nimble accurate selection each chip, thereby solve the problem that present encapsulation module does not support the embedding of the many chips of different thickness.
Moreover, in the encapsulation module that this application embodiment provided, first conductive substrate deviates from the thickness of second conductive substrate one side with first protective layer is located second conductive substrate deviates from first conductive substrate one side is formed with first protective layer to can effectively protect the chip, be applied to ultra-thin chip's scene. And because the first cavity penetrates through the laminated structure, the difference between the thickness of the first protective layer on the side, away from the second conductive substrate, of the first conductive substrate and the thickness of the first protective layer on the side, away from the first conductive substrate, of the second conductive substrate is not large, so that the packaging module is balanced up and down, and the warping phenomenon is avoided.
In addition, compared with the prior art in which each chip is packaged separately and packaged together on a circuit board, in the package module provided by the embodiment of the present application, each chip is packaged in a mixed manner, so that the area and the volume of the package module can be reduced, and the development of miniaturization of the package module is facilitated.
in one implementation, when the second chip includes a plurality of chip units electrically insulated from each other, the package module further includes: the third preset area penetrates through a plurality of fourth through holes of the first conductive substrate, and the projection of the fourth through holes on the second chip is located in an area between adjacent chip units, so that the area of the first conductive substrate below the second chip is divided into a plurality of mutually insulated conductive blocks, and therefore when each chip unit in the second chip is electrically connected with the conductive block below the chip unit, the mutual insulation among the chip units can still be ensured.
In one implementation, the method further comprises: the first conductive connecting layer is positioned between the second chip and the first conductive substrate, so that the first conductive connecting layer is utilized to reduce the contact resistance between the second chip and the first conductive substrate, improve the electrical connection performance between the second chip and the first conductive substrate, and improve the heat dissipation performance of the packaging module.
In one implementation, when the second chip includes a plurality of chip units electrically insulated from each other, the first conductive connection layer includes a plurality of first conductive connection regions insulated from each other, and the first conductive connection regions are in one-to-one correspondence with the chip units and electrically connected to the corresponding chip units.
in one implementation, the method further comprises: a fifth through hole penetrating through the second conductive substrate in a fourth preset area; and the third chip is positioned in the fifth through hole so as to support the embedding of more chips.
In one implementation, the method further comprises: and the second conductive connecting layer is positioned between the third chip and the second conductive substrate, so that the contact resistance between the third chip and the first conductive substrate is reduced by utilizing the second conductive connecting layer, the electric connection performance between the third chip and the first conductive substrate is improved, and the heat radiation performance of the packaging module is improved.
In one implementation, the second conductive connection layer is a metal glue layer.
in one implementation, the second chip is mounted upright and the third chip is mounted upside down; or, the second chip is reversely mounted, and the third chip is normally mounted, so that when the front surface of the second chip and the back surface of the third chip in the packaging module are electrically connected, a current through-flow path between the second chip and the third chip is reduced, and the heat loss of the packaging module is reduced.
drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
fig. 1 is a flow chart of a method for forming a package module according to an embodiment of the present application;
Fig. 2-15 are schematic structural diagrams illustrating structures formed in steps of a method for forming a package module according to an embodiment of the present application;
fig. 16 is a flow chart of a method of forming a packaged module according to another embodiment of the present application;
Fig. 17-31 are schematic structural diagrams illustrating structures formed at various steps in a method for forming a package module according to another embodiment of the present application;
Fig. 32 is a schematic structural diagram of a package module according to yet another embodiment of the present application;
Fig. 33 is a schematic structural diagram of a package module according to still another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
in the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.
As described in the background section, in the process of embedding a plurality of chips into a package module at the same time, because different height differences may exist among the plurality of chips, blind holes with different depths exist in the package module, when the thickness of the chip is large (for example, greater than 80 μm), the blind hole copper plating filling operation cannot be realized due to the limit of the process capability, and therefore, the current package module does not support the embedding of the plurality of chips with different thicknesses.
Moreover, when the plurality of chips are packaged by the resin layer in the subsequent process, the plurality of chips are all positioned above the copper carrier plate, so that the amount of resin positioned above the copper carrier plate is larger than the amount of resin positioned below the copper carrier plate, the overall structure of the packaging module is unbalanced from top to bottom, and warping is generated due to unbalanced vertical stress of the copper carrier plate in the curing process of the resin layer.
in addition, in the process of simultaneously embedding a plurality of chips into a package module, the chips are usually mounted on a copper carrier by using metal paste, wherein the placing directions of the chips can only be fixed in the same direction, so that the front surface of the chip is provided with a plurality of pins, the length of the wire for current flowing between different chips is too long, the resistance is increased accordingly, and the heat loss of the package module is large.
In view of this, an embodiment of the present application provides a method for forming a package module, as shown in fig. 1, the method includes:
S1: as shown in fig. 2, a first conductive substrate 1 and a second conductive substrate 2 are fixed by a first fixing layer 3, and a stacked structure in which the first conductive substrate 1, the first fixing layer 3, and the second conductive substrate 2 are stacked in this order is formed, in which the first fixing layer 3 is an insulating fixing layer.
Specifically, in an embodiment of the present application, the first conductive substrate 1 is a metal substrate, and may be a copper substrate, so as to ensure the supporting strength and the conductive performance of the first conductive substrate 1; the second conductive substrate 2 is a metal substrate, and may be a copper substrate, so as to ensure the support strength and the conductive performance of the second conductive substrate 2. The first fixing layer 3 is a resin layer or other insulating adhesive layer, which is not limited in this application, as the case may be.
on the basis of the above-described embodiment, in an embodiment of the present application, a laminated structure in which a first conductive substrate 1 and a second conductive substrate 2 are fixed by a first fixing layer 3 and the first conductive substrate 1, the first fixing layer 3, and the second conductive substrate 2 are laminated in this order is formed, including: the first conductive substrate 1 and the second conductive substrate 2 are laminated together by the first fixing layer 3, forming a laminated structure in which the first conductive substrate 1, the first fixing layer 3, and the second conductive substrate 2 are laminated in this order.
S2: as shown in fig. 3, a first through hole 4 is formed at a position of the second conductive substrate 2 corresponding to the first predetermined area, and a second through hole 5 is formed at a position corresponding to the second predetermined area, so as to divide the second conductive substrate 2 into at least two second substrate units. Specifically, in an embodiment of the present application, the first preset area is used for subsequently mounting a thick chip, and the second preset area is used for subsequently mounting a thin chip.
optionally, in an embodiment of the present application, the first through hole 4 and the second through hole 5 are formed at the same time, so as to simplify the process steps of the method for forming the package module; the forming process of the first through hole 4 and the second through hole 5 is wet etching, but the forming process is not limited in this application, and is determined as the case may be.
s3: as shown in fig. 4, a third through hole 6 is formed at a position of the first conductive substrate 1 corresponding to the first predetermined region, so as to divide the first conductive substrate 1 into at least two first substrate units.
S4: as shown in fig. 5, a portion of the first fixing layer 3 between the first through hole 4 and the third through hole 6 is removed to form a first chamber 7, and a portion of the first fixing layer 3 within the second through hole 5 is removed. Optionally, the removing process of the removed portion of the first fixing layer 3 is laser removal, but this is not limited in this application, and is determined as the case may be.
S5: as shown in fig. 6, a first supporting layer 81 is formed on a side of the first conductive substrate 1 facing away from the second conductive substrate 2.
In an embodiment of the present application, the first supporting layer 81 is a film layer, such as a frame sealing film layer, but the present application does not limit this, as long as the supporting strength of the first supporting layer 81 can fix the plurality of first substrate units in the first conductive substrate 1 and support the thick chip to be mounted subsequently. It should be noted that, on the basis of the above embodiments, the first supporting layer 81 is made of a high temperature resistant material, such as a material capable of withstanding at least 200 ℃, since the subsequent forming process of the package module may involve high temperature operation. However, the present application is not limited thereto, as the case may be.
s6: as shown in fig. 7, a first chip 8 is fixed in the first chamber 7, and a second chip 9 is fixed in the second through hole 5, wherein the thickness of the first chip 8 is greater than that of the second chip 9, and the first chip 8 and the second chip 9 are electrically insulated.
it should be noted that, in an optional embodiment of the present application, the thickness of the first chip 8 is not greater than the height of the first cavity 7, and the thickness of the second chip 9 is not greater than the height of the second through hole 5, so that the surface of the first chip 8 and the surface of the second chip 9 facing away from the first conductive substrate 1 are not higher than the surface of the second conductive substrate 2 facing away from the first conductive substrate 1, the first chip 8 is completely embedded in the first cavity 7, and the second chip 9 is completely embedded in the second through hole 5.
Specifically, in an embodiment of the present application, the first chip 8 is mounted in the first cavity 7 by a die bonder, and the second chip 9 is mounted in the second through hole 5, but the present application is not limited thereto, as the case may be.
it should be noted that, in the embodiment of the present application, the first chip 8 may be installed in a forward manner, that is, the front surface of the first chip 8 is installed away from the first conductive substrate 1, or may be installed in a reverse manner, that is, the front surface of the first chip 8 is installed toward the first conductive substrate 1. Similarly, the second chip 9 may also be mounted in a forward manner, that is, the front surface of the second chip 9 is installed away from the first conductive substrate 1, or may be mounted in a reverse manner, that is, the front surface of the second chip 9 is installed toward the first conductive substrate 1, which is not limited in this application, and is specifically determined according to the situation.
it should be noted that, in the embodiment of the present application, the first chip 8 and the second chip 9 may be mounted in the same manner or different manners, depending on the circumstances.
on the basis of any of the above embodiments, in an embodiment of the present application, when the second chip 9 includes a plurality of chip units electrically insulated from each other, as shown in fig. 8, the method further includes, before removing a portion of the first fixing layer 3 located between the first through hole 4 and the third through hole 6, forming the first chamber 7, and removing a portion of the first fixing layer 3 located in the second through hole 5: a plurality of fourth through holes 10 are formed in the first conductive substrate 1 at positions corresponding to the third preset region, and the projection of the fourth through holes 10 on the second chip 9 is located in a region between adjacent chip units, so that the region of the first conductive substrate 1 below the second chip 9 is divided into a plurality of conductive blocks insulated from each other, and therefore when each chip unit in the second chip 9 is electrically connected with the conductive block below the chip unit, the chip units can still be insulated from each other.
since the electrical connection performance between the second chip 9 and the first conductive substrate 1 needs to be improved, on the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 9, the method further includes, before fixing the second chip 9 in the second through hole 5: forming a first conductive connection layer 11 on the lower surface of the second through hole 5, optionally, the first conductive connection layer 11 is a metal glue layer, so that the first conductive connection layer 11 is utilized to reduce the contact resistance between the second chip 9 and the first conductive substrate 1, improve the electrical connection performance between the second chip 9 and the first conductive substrate 1, and improve the heat dissipation performance of the package module. However, the present application is not limited thereto, as the case may be.
it should be noted that, in the above embodiment, when the second chip 9 includes a plurality of chip units electrically insulated from each other, as shown in fig. 10, the first conductive connection layer 11 includes a plurality of first conductive connection regions 111 insulated from each other, and the first conductive connection regions 111 correspond to the chip units one by one and are electrically connected to the corresponding chip units.
s7: as shown in fig. 11, the first support layer 81 is removed.
S8: as shown in fig. 11, a first protective layer 12 is formed on a side of the first conductive substrate 1 away from the second conductive substrate 2 and a side of the second conductive substrate 2 away from the first conductive substrate 1.
Specifically, in an embodiment of the present application, the forming of the first protective layer 12 on the side of the first conductive substrate 1 away from the second conductive substrate 2 and the side of the second conductive substrate 2 away from the first conductive substrate 1, where the first protective layer 12 is a resin layer, includes:
The resin layer is filled in each through hole and gap of the first conductive substrate 1 and the second conductive substrate 2, the first conductive substrate 1 deviates from the second conductive substrate 2 side and the second conductive substrate 2 deviates from the first conductive substrate 1 side to form a resin layer, the resin layer completely covers the first conductive substrate 1 deviates from the second conductive substrate 2 side and the second conductive substrate 2 deviates from the first conductive substrate 1 side surface.
S9: as shown in fig. 12 to 14, a plurality of connection holes 13 are formed in the first protective layer 12, and the connection holes 13 are filled to form a plurality of connection structures 15, and the connection structures 15 are used for electrically connecting with the first chip 8 or the second chip 9.
in one embodiment of the present application, as shown in fig. 12, forming a plurality of connection holes 13 in the first protective layer 12 includes: a plurality of blind holes for electrically connecting to each chip unit included in the first chip 8, the second chip 9, or the second chip 9 are drilled in the first conductive substrate 1 and the second conductive substrate 2 by laser. However, this is not limited in this application, and in other embodiments of this application, a plurality of connection holes 13 may be formed in the first protection layer 12 in other manners, as the case may be. In addition, in the forming method of the packaging module provided by the embodiment of the application, blind holes with different depths do not exist, so that the serious recess phenomenon can not occur.
On the basis of any of the above embodiments, in an embodiment of the present application, filling the connection holes 13, forming a plurality of connection structures 15 includes forming an electrical connection layer 14 (as shown in fig. 13) in the connection holes 13 in an electroplating manner on a surface of the first conductive substrate 1 facing away from the second conductive substrate 2 and on a side of the second conductive substrate 2 facing away from the first conductive substrate 1, and partially removing the electrical connection layer 14 to form a plurality of connection structures 15 (as shown in fig. 14), where the connection structures 15 are used to be electrically connected to each chip unit in the first chip 8 or the second chip 9, and the connection structures 15 electrically connecting different chips or different chip units are insulated from each other. Optionally, a wet etching process is used to partially remove the electrical connection layer 14, but this is not limited in this application, as the case may be.
Specifically, on the basis of the above embodiments, in an embodiment of the present application, the material of the connection structure 15 is copper, so as to reduce the contact resistance between the connection structure 15 and the chip (or the chip unit) electrically connected thereto, and improve the heat dissipation performance of the package module.
It should be noted that, in the above embodiment, the thickness of the connection structure 15 is proportional to the input or output current intensity of each chip unit in the first chip 8, the second chip 9, or the second chip 9, and this application is not particularly limited thereto, as long as the connection structure 15 is ensured to flow through the input or output current intensity of each chip unit in the first chip 8, the second chip 9, or the second chip 9.
on the basis of any one of the above embodiments, in an embodiment of the present application, the method further includes:
S10: as shown in fig. 15, a solder mask 16 is formed on a side of the connecting structure 15 facing away from the stacked structure, the solder mask 16 includes a plurality of recessed areas 17, wherein the recessed areas 17 are used for soldering an external circuit (such as a PCB) or an external electrical component (such as a circuit or an inductor), and the portion of the solder mask 16 excluding the recessed areas 17 is used for preventing the soldered external circuit or external electrical component from extending to a non-soldered area to cause a short circuit.
According to the method for forming the packaging module, the first conductive substrate 1, the first fixing layer 3 and the second conductive substrate 2 are firstly formed in a laminated structure, and then the first cavity 7 and the second through hole 5 with different depths are formed in the laminated structure, so that chips with different thicknesses can be conveniently mounted, and the problem that the conventional packaging module does not support embedding of multiple chips with different thicknesses is solved.
moreover, in the method for forming the encapsulation module provided by the embodiment of the present application, when the first conductive substrate 1 deviates from the second conductive substrate 2 and the second conductive substrate 2 deviates from the first conductive substrate 1 to form the first protection layer 12, because the first chamber 7 runs through the laminated structure, the difference between the thickness of the first protection layer 12 on the side where the first conductive substrate 1 deviates from the second conductive substrate 2 and the thickness of the first protection layer 12 on the side where the second conductive substrate 2 deviates from the first conductive substrate 1 is not large, so that the encapsulation module is balanced up and down, and the warpage phenomenon is avoided.
It should be noted that, the method for forming the package module provided in the above embodiments of the present application is described by taking embedding two chips (one thick chip and one thin chip) as an example, in other embodiments of the present application, the package module may further embed more chips, such as at least two thick chips and at least one thin chip, or at least one thick chip and at least two thin chips, which is not limited in this application, as the case may be. The following describes a method for forming a package module provided in the embodiments of the present application, taking the package module embedding a thick chip (a first chip) and two thin chips (a second chip and a third chip) as an example.
It should be noted that only different parts of this embodiment from the above embodiments are described below, and detailed descriptions of the same parts are omitted.
As shown in fig. 16, a method for forming a package module provided in an embodiment of the present application includes:
S11: as shown in fig. 17, a first conductive substrate 1 and a second conductive substrate 2 are fixed by a first fixing layer 3, and a laminated structure in which the first conductive substrate 1, the first fixing layer 3, and the second conductive substrate 2 are laminated in this order is formed, in which the first fixing layer 3 is an insulating fixing layer.
S12: as shown in fig. 18, a first through hole 4 is formed at a position of the second conductive substrate 2 corresponding to the first predetermined region, a second through hole 5 is formed at a position corresponding to the second predetermined region, and a fifth through hole 18 is formed at a position corresponding to the fourth predetermined region, so as to divide the second conductive substrate 2 into at least two second substrate units. Specifically, in an embodiment of the present application, the first preset area is used for subsequently mounting a thick chip, the second preset area is used for subsequently mounting a thin chip, such as a second chip, and the fourth preset area is also used for subsequently mounting a thin chip, such as a third chip.
S13: as shown in fig. 19, a third through hole 6 is formed at a position of the first conductive substrate 1 corresponding to the first predetermined region, so as to divide the first conductive substrate 1 into at least two first substrate units.
s14: as shown in fig. 20, a portion of the first fixing layer 3 between the first through hole 4 and the third through hole 6 is removed to form a first chamber 7, and a portion of the first fixing layer 3 within the second through hole 5 and the fifth through hole 18 is removed. Optionally, the removing process of the removed portion of the first fixing layer 3 is laser removal, but this is not limited in this application, and is determined as the case may be.
s15: as shown in fig. 21, a first supporting layer 81 is formed on the side of the first conductive substrate 1 away from the second conductive substrate 2.
S16: as shown in fig. 22, a first chip 8 is fixed in the first chamber 7, a second chip 9 is fixed in the second through hole 5, and a third chip 19 is fixed in the fifth through hole 18, wherein the thickness of the first chip 8 is larger than the thickness of the second chip 9 and the thickness of the third chip 19, and any two chips among the first chip 8, the second chip 9, and the third chip 19 are electrically insulated.
Optionally, in this embodiment of the application, the thickness of the third chip 19 is not greater than the height of the fifth through hole 18, so that the surface of the third chip 19 on the side facing away from the first conductive substrate 1 is not higher than the surface of the second conductive substrate 2 on the side facing away from the first conductive substrate 1, and the third chip 19 is embedded in the fifth through hole 18.
It should be noted that, in the embodiment of the present application, the first chip 8 may be installed in a forward manner, that is, the front surface of the first chip 8 is installed away from the first conductive substrate 1, or may be installed in a reverse manner, that is, the front surface of the first chip 8 is installed toward the first conductive substrate 1. Similarly, the second chip 9 may be mounted in a forward manner, that is, the front surface of the second chip 9 is mounted away from the first conductive substrate 1, or mounted in a reverse manner, that is, the front surface of the second chip 9 is mounted toward the first conductive substrate 1; the third chip 19 may also be installed in a forward manner, that is, the front surface of the third chip 19 is installed away from the first conductive substrate 1, or installed in a reverse manner, that is, the front surface of the third chip 19 is installed toward the first conductive substrate 1, which is not limited in this application, as the case may be.
It should be further noted that, when the front surface of the second chip 9 and the back surface of the third chip 19 in the package module are electrically connected, optionally, in a specific embodiment of the present application, the second chip 9 is installed in a front direction, and the third chip 19 is installed in a reverse direction; in another embodiment of the present application, the second chip 9 is reversely mounted, and the third chip 19 is normally mounted, so as to reduce the current flow path between the second chip 9 and the third chip 19, and reduce the heat loss of the package module. However, the present application is not limited thereto, as the case may be.
on the basis of any of the above embodiments, in an embodiment of the present application, when the second chip 9 includes a plurality of chip units electrically insulated from each other, as shown in fig. 23, the method further includes, before removing a portion of the first fixing layer 3 located between the first through hole 4 and the third through hole 6, forming the first chamber 7, and removing a portion of the first fixing layer 3 located within the second through hole 5 and the fifth through hole 18: a plurality of fourth through holes 10 are formed in the first conductive substrate 1 at positions corresponding to the third preset region, and the projection of the fourth through holes 10 on the second chip 9 is located in a region between adjacent chip units, so that the region of the first conductive substrate 1 below the second chip 9 is divided into a plurality of conductive blocks insulated from each other, and therefore when each chip unit in the second chip 9 is electrically connected with the conductive block below the chip unit, the chip units can still be insulated from each other.
It should be noted that when the package module is used for assembling an electronic device, both sides of the package module may be electrically connected to a circuit board or an electrical component, so in an alternative embodiment of the present application, the method further comprises: as shown in fig. 24, a sixth through hole 20 is formed at a position of the second conductive substrate 2 corresponding to a fifth predetermined area, and a seventh through hole 21 is formed at a position of the first conductive substrate 1 corresponding to the fifth predetermined area. Accordingly, in this embodiment, as shown in fig. 25, the method further includes removing a portion of the first fixing layer 3 between the sixth through hole 20 and the seventh through hole 21 to form a second chamber 22 when removing a portion of the first fixing layer 3 between the first through hole 4 and the third through hole 6 to form a first chamber 7 and removing a portion of the first fixing layer 3 within the second through hole 5 and the fifth through hole 18.
It should be noted that, since the electrical connection performance between the second chip 9 and the first conductive substrate 1 needs to be improved, on the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 26, before the second chip 9 is fixed in the second through hole 5, the method further includes: forming a first conductive connection layer 11 on the lower surface of the second through hole 5, optionally, the first conductive connection layer 11 is a metal glue layer, so that the first conductive connection layer 11 is utilized to reduce the contact resistance between the second chip 9 and the first conductive substrate 1, improve the electrical connection performance between the second chip 9 and the first conductive substrate 1, and improve the heat dissipation performance of the package module. However, the present application is not limited thereto, as the case may be.
It should be noted that, in the above embodiment, when the second chip 9 includes a plurality of chip units electrically insulated from each other, the first conductive connection layer 11 includes a plurality of first conductive connection regions 111 insulated from each other, and the first conductive connection regions 111 and the chip units are in one-to-one correspondence and electrically connected to the corresponding chip units.
Similarly, as shown in fig. 26, the method for forming a package module according to the embodiment of the present application further includes, before fixing the third chip 19 in the fifth through hole 18: a second conductive connection layer 23 is formed on the lower surface of the fifth through hole 18, optionally, the second conductive connection layer 23 is a metal glue layer, so that the second conductive connection layer 23 is utilized to reduce the contact resistance between the third chip 19 and the first conductive substrate 1, improve the electrical connection performance between the third chip 19 and the first conductive substrate 1, and improve the heat dissipation performance of the package module. However, the present application is not limited thereto, as the case may be.
It should be noted that, in an alternative embodiment of the present application, the first conductive connection layer 11 and the second conductive connection layer 23 are formed simultaneously, so as to simplify the process steps of the package module and reduce the manufacturing cost of the package module.
It should be further noted that the method for forming the package module provided in the embodiment of the present application can adapt to the thickness difference between the multiple chips by the thicknesses of the first conductive substrate, the second conductive substrate, the first conductive connection layer, and the second conductive connection layer, so as to implement embedding of the multiple chips with different thicknesses.
S17: as shown in fig. 27, the first support layer 81 is removed.
S18: as shown in fig. 27, a first protective layer 12 is formed on the side of the first conductive substrate 1 away from the second conductive substrate 2 and the side of the second conductive substrate 2 away from the first conductive substrate 1.
S19: as shown in fig. 28, a plurality of connection holes 13 are formed in the first protective layer 12, as shown in fig. 29 and 30, and the connection holes 13 are filled to form a plurality of connection structures 15, and the connection structures 15 are used to electrically connect with the first chip 8, the second chip 9, or the third chip 19.
Specifically, filling the connection hole 13 to form a plurality of connection structures 15 includes: forming an electrical connection layer 14 in the plurality of connection holes 13, on the surface of the first conductive substrate 1 away from the second conductive substrate 2, and on the side of the second conductive substrate 2 away from the first conductive substrate 1 by electroplating (as shown in fig. 29), and partially removing the electrical connection layer 14 to form a plurality of connection structures 15 (as shown in fig. 30), where the connection structures 15 are used to be electrically connected with each chip unit in the first chip 8 or the third chip 19 or the second chip 9, and the connection structures 15 electrically connected with different chips or different chip units are insulated from each other. Optionally, a wet etching process is used to partially remove the electrical connection layer 14, but this is not limited in this application, as the case may be.
S20: as shown in fig. 31, a solder mask 16 is formed on a side of the connecting structure 15 facing away from the stacked structure, the solder mask 16 includes a plurality of recessed areas 17, wherein the recessed areas 17 are used for soldering an external circuit (such as a PCB) or an external electrical component (such as a circuit or an inductor), and the portion of the solder mask 16 excluding the recessed areas 17 is used for preventing the soldered external circuit or external electrical component from extending to a non-soldered area to cause a short circuit.
according to the method for forming the packaging module, the first conductive substrate 1, the first fixing layer 3 and the second conductive substrate 2 are firstly formed in a laminated structure, and then the first cavity 7 and the second through hole 5 with different depths are formed in the laminated structure, so that chips with different thicknesses can be conveniently mounted, and the problem that the conventional packaging module does not support embedding of multiple chips with different thicknesses is solved.
Moreover, in the method for forming the encapsulation module provided by the embodiment of the present application, when the first conductive substrate 1 deviates from the second conductive substrate 2 and the second conductive substrate 2 deviates from the first conductive substrate 1 to form the first protection layer 12, because the first chamber 7 runs through the laminated structure, the difference between the thickness of the first protection layer 12 on the side where the first conductive substrate 1 deviates from the second conductive substrate 2 and the thickness of the first protection layer 12 on the side where the second conductive substrate 2 deviates from the first conductive substrate 1 is not large, so that the encapsulation module is balanced up and down, and the warpage phenomenon is avoided.
In addition, the forming method of the packaging module provided by the embodiment of the application supports the forward installation, the reverse installation and/or the mixed installation of a plurality of chips, so that when the packaging module is applied to the electrical connection of the front surface of one chip and the reverse surface of another chip, the forward installation of one chip and the reverse installation of the other chip can be realized, the current through-flow path between the two chips is reduced, and the heat loss of the packaging module is reduced.
Correspondingly, an embodiment of the present application further provides a package module, as shown in fig. 14, where the package module includes:
The multilayer structure comprises a first conductive substrate 1, a first fixed layer 3 and a second conductive substrate 2 which are sequentially laminated, wherein the first fixed layer 3 is an insulating fixed layer;
A first chamber 7 which penetrates the laminated structure in a first predetermined area;
a second through hole 5 penetrating the second conductive substrate 2 and the first fixed layer 3 in a second predetermined region;
A first chip 8 fixed to the first chamber 7;
a second chip 9 fixed to the second through hole 5, wherein the thickness of the first chip 8 is greater than that of the second chip 9, and the first chip 8 and the second chip 9 are electrically insulated;
the first protective layer 12 is positioned on one side of the first conductive substrate 1, which is far away from the second conductive substrate 2, and one side of the second conductive substrate 2, which is far away from the first conductive substrate 1, and the first protective layer 12 is provided with a plurality of connecting holes 13;
And a connection structure 15 filling the connection hole 13, wherein the connection structure 15 is used for electrically connecting with the first chip 8 or the second chip 9.
On the basis of the above embodiment, in an optional embodiment of the present application, the thickness of the first chip 8 is not greater than the height of the first cavity 7, and the thickness of the second chip 9 is not greater than the height of the second through hole 5, so that the surface of the first chip 8 and the surface of the second chip 9 facing away from the first conductive substrate 1 are not higher than the surface of the second conductive substrate 2 facing away from the first conductive substrate 1, the first chip 8 is completely embedded in the first cavity 7, and the second chip 9 is completely embedded in the second through hole 5.
It should be noted that, in the embodiment of the present application, the first chip 8 may be installed in a forward manner, that is, the front surface of the first chip 8 is installed away from the first conductive substrate 1, or may be installed in a reverse manner, that is, the front surface of the first chip 8 is installed toward the first conductive substrate 1. Similarly, the second chip 9 may also be mounted in a forward manner, that is, the front surface of the second chip 9 is installed away from the first conductive substrate 1, or may be mounted in a reverse manner, that is, the front surface of the second chip 9 is installed toward the first conductive substrate 1, which is not limited in this application, and is specifically determined according to the situation.
It should be noted that, in the embodiment of the present application, the first chip 8 and the second chip 9 may be mounted in the same manner or different manners, depending on the circumstances.
The encapsulation module that this application embodiment provided includes the laminated structure that first conductive substrate 1, first fixed layer 3 and second conductive substrate 2 range upon range of in proper order, and is formed with the first cavity 7 and the second through-hole 5 of the different degree of depth in this laminated structure to the chip of different thickness is installed in the convenience, thereby solves the problem that present encapsulation module does not support the embedding of the many chips of different thickness.
Moreover, in the encapsulation module provided by the embodiment of the application, since the first cavity 7 penetrates through the laminated structure, the first protection layer 12 is located at the thickness of the first conductive substrate 1 deviating from the second conductive substrate 2 side and the thickness of the first protection layer 12 is located at the second conductive substrate 2 deviating from the first conductive substrate 1 side, so that the difference between the thicknesses is not large, the encapsulation module is balanced vertically, and the warping phenomenon is avoided.
On the basis of the above-described embodiments, in one embodiment of the present application, when the second chip includes a plurality of chip units electrically insulated from each other, the package module further includes: a plurality of fourth through holes penetrate through the first conductive substrate in a third preset area, and projections of the fourth through holes on the second chip are located in areas between adjacent chip units, so that the area of the first conductive substrate 1 below the second chip 9 is divided into a plurality of conductive blocks which are insulated from each other, and therefore when each chip unit in the second chip 9 is electrically connected with the conductive block below the chip unit, the chip units can still be ensured to be insulated from each other.
since the electrical connection performance between the second chip 9 and the first conductive substrate 1 needs to be improved, on the basis of any one of the above embodiments, in an embodiment of the present application, the package module further includes: the first conductive connecting layer 11 is located between the second chip and the first conductive substrate, so that the first conductive connecting layer 11 is utilized to reduce the contact resistance between the second chip 9 and the first conductive substrate 1, improve the electrical connection performance between the second chip 9 and the first conductive substrate 1, and improve the heat dissipation performance of the packaging module. However, the present application is not limited thereto, as the case may be.
On the basis of the above embodiments, in an embodiment of the present application, when the second chip 9 includes a plurality of chip units electrically insulated from each other, the first conductive connection layer 11 includes a plurality of first conductive connection regions 111 insulated from each other, and the first conductive connection regions 111 correspond to the chip units one to one and are electrically connected to the corresponding chip units.
it should be noted that, the package module provided in the above embodiments of the present application is exemplified by embedding two chips (one thick chip and one thin chip), and in other embodiments of the present application, the package module may further embed more chips, such as at least two thick chips and at least one thin chip, or at least one thick chip and at least two thin chips, which is not limited in this application, as the case may be. The following describes a package module provided in an embodiment of the present application, taking the package module embedding a thick chip (a first chip) and two thin chips (a second chip and a third chip) as an example.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 30, when the package module embeds one thick chip (first chip) and two thin chips (second chip and third chip), the package module further includes: a fifth via 18 penetrating the second conductive substrate in a fourth predetermined area; a third chip 19 located in the fifth through hole 18.
It should be noted that, in the embodiment of the present application, the third chip 19 may be installed in a forward manner, that is, the front surface of the third chip 19 is installed away from the first conductive substrate 1, or installed in a reverse manner, that is, the front surface of the third chip 19 is installed toward the first conductive substrate 1, which is not limited in this application, and is determined as the case may be.
It should be further noted that, when the front surface of the second chip 9 and the back surface of the third chip 19 in the package module are electrically connected, optionally, in a specific embodiment of the present application, the second chip 9 is installed in a front direction, and the third chip 19 is installed in a reverse direction; in another embodiment of the present application, the second chip 9 is reversely mounted, and the third chip 19 is normally mounted, so as to reduce the current flow path between the second chip 9 and the third chip 19, and reduce the heat loss of the package module. However, the present application is not limited thereto, as the case may be.
Since the electrical connection performance between the second chip 9 and the first conductive substrate 1 needs to be improved, on the basis of any of the above embodiments, in an embodiment of the present application, the method further includes: a second conductive connection layer 23 located between the third chip and the second conductive substrate, optionally, the second conductive connection layer 23 is a metal glue layer, so that the second conductive connection layer 23 is utilized to reduce the contact resistance between the third chip 19 and the first conductive substrate 1, improve the electrical connection performance between the third chip 19 and the first conductive substrate 1, and simultaneously, the thermal conductivity of copper is as high as that of the first conductive substrate 1
400w/mK, thereby improving the heat dissipation performance of the packaging module. However, the present application is not limited thereto, as the case may be.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 15 and 31, the package module further includes: the solder mask 16 is located on a side of the connecting structure 15 facing away from the stacked structure, the solder mask 16 includes a plurality of recessed areas 17, wherein the recessed areas 17 are used for soldering an external circuit (such as a PCB) or an external electrical component (such as a circuit or an inductor), and the portion of the solder mask 16 excluding the recessed areas 17 is used for preventing a short circuit caused when the soldered external circuit or external electrical component extends to a non-soldering area. As shown in fig. 32, fig. 32 is a schematic structural diagram illustrating the electrical connection of the inductor 24 over the package module according to the embodiment of the present application.
It should be further noted that, on the basis of any of the above embodiments, in an embodiment of the present application, when the package module is used for assembling an electronic device, both sides of the package module may be electrically connected to a circuit board or an electrical component, so that in an alternative embodiment of the present application, as shown in fig. 31, the package module further includes: and a second chamber 22 penetrating the stacked structure in a fifth predetermined region, and a communication structure located in the second chamber 22 and electrically connecting components located above the package module and below the package module.
On the basis of any of the above embodiments, in an embodiment of the present application, the first chip is a control chip, and the second chip and the third chip are MOS transistors, but the present application does not limit this, which is determined as the case may be.
It should be noted that, on the basis of any of the above-mentioned embodiments, in one embodiment of the present application, as shown in fig. 33, the connection structures include a first connection structure 151 located in the connection hole on the side of the second conductive substrate 2 facing away from the first conductive substrate 1, a second connection structure 152 located on the side of the second conductive substrate 2 facing away from the first conductive substrate 1, a third connection structure 153 located in the connection hole on the side of the first conductive substrate 1 facing away from the second conductive substrate 2, and a fourth connection structure 154 located on the side of the first conductive substrate 1 facing away from the second conductive substrate 2, wherein the second connection structure 152 is a circuit layer located on a side of the second conductive substrate 2 away from the first conductive substrate 1, the fourth connection structure 154 is a circuit layer located on a side of the first conductive substrate 1 away from the second conductive substrate 2.
specifically, in an embodiment of the present application, the first chip 8 is reversely mounted, the second chip 9 is reversely mounted, the third chip 19 is normally mounted, and the second chip 9 is interconnected through the first conductive connection layer 11, the first conductive substrate 1, the third connection structure 153, and the fourth connection structure 154; the third chip 19 is interconnected through the second conductive connection layer 23, the first conductive substrate 1, the third connection structure 153 and the fourth connection structure 154; the second chip 9 is interconnected through the first connection structure 151, the second connection structure 152 and the third chip 19; the first chip 8 is interconnected by a third connection structure 153, a fourth connection structure 154, a communication structure located in the second chamber 22, the second connection structure 152, the first connection structure 151, and a thin chip (e.g., the second chip 9 or the third chip 19).
To sum up, the encapsulation module that this application embodiment provided includes the laminated structure that first conductive substrate 1, first fixed layer 3 and second conductive substrate 2 range upon range of in proper order, and is formed with the first cavity 7 and the second through-hole 5 of the different degree of depth in this laminated structure to install the chip of different thickness, the thickness of nimble accurate selection each chip, thereby solve the problem that present encapsulation module does not support the embedding of the many chips of different thickness.
Moreover, in the encapsulation module provided by the embodiment of the application, the first conductive substrate 1 deviates from the thickness of one side of the second conductive substrate 2 and the first protection layer 12 is located on one side of the second conductive substrate 2 deviating from the first conductive substrate 1, the first protection layer 12 is formed, so that the chip can be effectively protected, and the encapsulation module is applied to the scene of an ultrathin chip. And because the first chamber 7 penetrates through the laminated structure, the difference between the thickness of the first protective layer 12 on the side of the first conductive substrate 1 departing from the second conductive substrate 2 and the thickness of the first protective layer 12 on the side of the second conductive substrate 2 departing from the first conductive substrate 1 is not large, so that the packaging module is balanced up and down, and the warping phenomenon is avoided.
In addition, the packaging module provided by the embodiment of the application supports forward installation, reverse installation and/or mixed installation of a plurality of chips, so that when the packaging module is applied to electrically connecting the front surface of one chip and the back surface of another chip, the chip can be forward installed and the other chip can be reverse installed, the current through-flow path between the two chips is reduced, and the heat loss of the packaging module is reduced.
in addition, compared with the prior art in which each chip is packaged separately and packaged together on a circuit board, in the package module provided by the embodiment of the present application, each chip is packaged in a mixed manner, so that the area and the volume of the package module can be reduced, and the development of miniaturization of the package module is facilitated.
in the description, each part is described in a progressive manner, each part is emphasized to be different from other parts, and the same and similar parts among the parts are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (16)

1. A method of forming a packaged module, comprising:
Fixing a first conductive substrate and a second conductive substrate by using a first fixing layer to form a laminated structure in which the first conductive substrate, the first fixing layer and the second conductive substrate are laminated in sequence, wherein the first fixing layer is an insulating fixing layer;
forming a first through hole at a position of the second conductive substrate corresponding to the first preset region, and forming a second through hole at a position corresponding to the second preset region;
forming a third through hole at a position of the first conductive substrate corresponding to the first preset area;
Removing a part of the first fixing layer, which is positioned between the first through hole and the third through hole, to form a first chamber, and removing a part of the first fixing layer, which is positioned in the second through hole;
Forming a first supporting layer on one side of the first conductive substrate, which is far away from the second conductive substrate;
Fixing a first chip in the first chamber and fixing a second chip in the second through hole, wherein the thickness of the first chip is larger than that of the second chip, and the first chip and the second chip are electrically insulated;
Removing the first support layer;
Forming a first protective layer on one side of the first conductive substrate, which is far away from the second conductive substrate, and one side of the second conductive substrate, which is far away from the first conductive substrate;
And forming a plurality of connecting holes in the first protective layer, filling the connecting holes, and forming a plurality of connecting structures, wherein the connecting structures are used for being electrically connected with the first chip or the second chip.
2. The method of forming as claimed in claim 1, wherein when the second chip includes a plurality of chip units electrically insulated from each other, the method further includes, before removing a portion of the first fixing layer between the first via hole and the third via hole, forming a first chamber, and removing a portion of the first fixing layer within the second via hole:
And forming a plurality of fourth through holes in a third preset area in the first conductive substrate, wherein the projection of the fourth through holes on the second chip is positioned in an area between adjacent chip units.
3. The method of claim 1 or 2, further comprising, prior to securing the second chip within the second via:
And forming a first conductive connecting layer on the lower surface of the second through hole.
4. The method of claim 3, wherein the first conductive connection layer is a metal glue layer.
5. the method of claim 3, wherein when the second chip includes a plurality of chip units electrically insulated from each other, the first conductive connection layer includes a plurality of first conductive connection regions insulated from each other, the first conductive connection regions and the chip units are in one-to-one correspondence and electrically connected to their corresponding chip units.
6. The method of forming as claimed in claim 1, further comprising, prior to forming a first support layer on a side of the first conductive substrate facing away from the second conductive substrate:
forming a fifth through hole in the second conductive substrate at a position corresponding to a fourth preset area;
removing the part of the first fixing layer, which is positioned in the fifth through hole;
The method further comprises the following steps of after forming a first supporting layer on one side of the first conductive substrate, which faces away from the second conductive substrate:
And fixing a third chip in the fifth through hole, wherein the thickness of the third chip is not more than the height of the fifth through hole.
7. The method of forming as claimed in claim 6, wherein the second chip is mounted face up and the third chip is mounted face down; or, the second chip is reversely mounted, and the third chip is normally mounted.
8. The method of forming as claimed in claim 6, further comprising, prior to securing a third chip within the fifth via:
And forming a second conductive connecting layer on the lower surface of the fifth through hole.
9. The method of claim 8, wherein the second conductive connection layer is a metal glue layer.
10. a packaged module, comprising:
the laminated structure comprises a first conductive substrate, a first fixed layer and a second conductive substrate which are sequentially laminated, wherein the first fixed layer is an insulating fixed layer;
a first chamber penetrating the laminated structure at a first predetermined region;
A second through hole penetrating the second conductive substrate and the first fixing layer in a second preset area;
a first chip fixed in the first chamber;
A second chip fixed to the second through hole, the first chip having a thickness greater than that of the second chip, and the first chip and the second chip being electrically insulated;
the first protective layer is positioned on one side, away from the second conductive substrate, of the first conductive substrate and on one side, away from the first conductive substrate, of the second conductive substrate, and a plurality of connecting holes are formed in the first protective layer;
And the connecting structure is used for being electrically connected with the first chip or the second chip.
11. The packaged module of claim 10, wherein when the second chip comprises a plurality of chip units electrically insulated from each other, the packaged module further comprises:
and a plurality of fourth through holes penetrating through the first conductive substrate in a third preset area, wherein the projection of the fourth through holes on the second chip is positioned in an area between adjacent chip units.
12. The packaged module of claim 10, further comprising:
A first conductive connection layer between the second chip and the first conductive substrate.
13. the package module according to claim 12, wherein when the second chip includes a plurality of chip units electrically insulated from each other, the first conductive connection layer includes a plurality of first conductive connection regions insulated from each other, the first conductive connection regions are in one-to-one correspondence with the chip units and electrically connected to the corresponding chip units.
14. The packaged module of claim 10, further comprising:
A fifth through hole penetrating through the second conductive substrate in a fourth preset area;
And the third chip is positioned in the fifth through hole.
15. the packaged module of claim 14, further comprising:
A second conductive connection layer between the third chip and the first conductive substrate.
16. The packaged module of claim 14, wherein the second chip is mounted face up and the third chip is mounted face down; or, the second chip is reversely mounted, and the third chip is normally mounted.
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