CN108037345A - Signal processing method, device, storage medium and processor - Google Patents
Signal processing method, device, storage medium and processor Download PDFInfo
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- CN108037345A CN108037345A CN201710895617.8A CN201710895617A CN108037345A CN 108037345 A CN108037345 A CN 108037345A CN 201710895617 A CN201710895617 A CN 201710895617A CN 108037345 A CN108037345 A CN 108037345A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R19/10—Measuring sum, difference or ratio
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Abstract
The invention discloses a kind of signal processing method, device, storage medium and processor.This method includes：In objective circuit, peak signal and direct current signal in common-mode signal are detected, wherein, peak signal is used for the peak value for indicating common-mode signal, and direct current signal is used to indicate the DC component in common-mode signal；Quantification treatment is carried out to peak signal and direct current signal, obtains quantized result, wherein, the difference between numerical value corresponding with peak signal and numerical value corresponding with direct current signal in quantized result, for characterizing the degree of jitter of common-mode signal；In the case where quantized result meets goal condition, the corresponding duty cycle of quantized result is determined as to the target duty ratio of objective circuit.By the present invention, the effect for improving signal processing efficiency is reached.
Description
Technical field
The present invention relates to circuit field, in particular to a kind of signal processing method, device, storage medium and processing
Device.
Background technology
At present, in high-speed interconnected circuit, the quality of transmitter output signal determines that communication equipment can reach most
High-speed.High-speed interconnected circuit generally requires the low amplitude of oscillation output of difference, impedance matching etc. to improve signal because long distance transmission
Quality and the electromagnetic interference that reduces (Electro Magnetic Interference, referred to as EMI).Export the duty of signal
Than being a key factor for weighing differential signal quality.Duty cycle imbalance can all have quality of output signals and EMI very big
Influence.
Duty cycle imbalance can probably be distinguished into two kinds of situations, the first situation is as shown in Figure 1.Wherein, Fig. 1 is according to phase
A kind of schematic diagram of duty cycle imbalance in the technology of pass.The differential pair signal anode and negative terminal are symmetrical, but the high level of anode
(low level of negative terminal) wants narrower than the low level (high level of negative terminal) of anode.Because full symmetric, the differential pair common mode
Export or stable, but be reflected on difference output, the width of low and high level is different, therefore recovers signal in receiving terminal
When, relatively narrow high level influences whether the nargin of signal sampling, adds the difficulty of signal recovery.This Duty Cycle Distortion one
As be that to have partial circuit be single-ended signal to chip internal, the duty cycle that former single-ended signal is maintained when single-ended transfer difference is lost
Genuine characteristic.As long as lost so keeping chip internal clock data largely to eliminate this duty cycle for fully differential
Adjust.
The second situation is as shown in Figure 2.Wherein, Fig. 2 is the signal of another duty cycle imbalance in correlation technique
Figure.No matter in the chip signal portion or is being output to outside piece, and the driving force of its rise and fall all necessarily can not be completely the same.When
There are some regions heavier loads in chip, when either load when level conversion or outside output driving piece, even if non-
Often careful design can also produce situation as shown in Figure 2 when process deviation.Even if buffer circuit energy hereafter will be upper
The driving force for rising trailing edge is transferred to unanimously, and differential signal can also become state as shown in Figure 3, and the shake of its common-mode signal has
It may become much larger.Wherein, Fig. 3 is the schematic diagram of another duty cycle imbalance in correlation technique.
Therefore, although the differential signal duty cycle of Fig. 2 and Fig. 3 is intact, but its common-mode signal has shake, Er Qieshang
Rise the process declined and be possible to asymmetric, such differential signal, which can produce, following has Railway Project：
(1) when common-mode signal is transmitted on the transmission line, electromagnetic interference can be produced, can not be cancelled；
(2) asymmetry on rise and fall edge, causes signal to be deteriorated the antijamming capability of common-mode noise, thus in receiving terminal
Signal quality be deteriorated；
(3) shake of common mode is also influenced whether on the power supply of output stage, increases the intersymbol interference (Inter- of output stage
Symbol Interference, referred to as ISI) shake.The problem of thus presence signal treatment effeciency is low.
For the problem of signal processing efficiency is low in the prior art, effective solution is not yet proposed at present.
The content of the invention
It is a primary object of the present invention to provide a kind of signal processing method, device, storage medium and processor, with least
Solve the problems, such as that signal processing efficiency is low.
To achieve these goals, according to an aspect of the invention, there is provided a kind of signal processing method.This method bag
Include：In objective circuit, peak signal and direct current signal in common-mode signal are detected, wherein, peak signal is used to indicate common mode
The peak value of signal, direct current signal are used to indicate the DC component in common-mode signal；Peak signal and direct current signal are quantified
Processing, obtains quantized result, wherein, numerical value corresponding with peak signal and numerical value corresponding with direct current signal in quantized result
Between difference, for characterizing the degree of jitter of common-mode signal；In the case where quantized result meets goal condition, will quantify to tie
The corresponding duty cycle of fruit is determined as the target duty ratio of objective circuit.
Alternatively, detecting the peak signal in common-mode signal and direct current signal includes：Under the first control word, detection first
The first peak signal and the first direct current signal in common-mode signal, wherein, the first control word is used to control the first common-mode signal
Degree of jitter, peak signal include the first peak signal, and the first peak signal is used for the first peak value for indicating the first common-mode signal,
Direct current signal includes the first direct current signal, and the first direct current signal is used to indicate the first DC component in the first common-mode signal；It is right
Peak signal and direct current signal carry out quantification treatment, and obtaining quantized result includes：To the first peak signal and the first direct current signal
Quantification treatment is carried out, obtains the first quantized result, wherein, quantized result includes the first quantized result.
Alternatively, detect the peak signal in common-mode signal and direct current signal further includes：Under the second control word, mesh is detected
The second peak signal and the second direct current signal in the second common-mode signal of circuit are marked, wherein, the second control word is used to control the
The degree of jitter of two common-mode signals, peak signal include the second peak signal, and the first peak signal is used to indicate the second common mode letter
Number the second peak value, direct current signal includes the second direct current signal, and the second direct current signal is used to indicate the in the second common-mode signal
Two DC components；Quantification treatment is carried out to peak signal and direct current signal, obtaining quantized result includes：To the second peak signal and
Second direct current signal carries out quantification treatment, obtains the second quantized result, wherein, quantized result includes the second quantized result；Measuring
In the case that change result meets goal condition, the corresponding duty cycle of quantized result is determined as the target duty of objective circuit than bag
Include：The Target quantization of goal condition is determined for compliance with from the first quantized result and the second quantized result as a result, and by Target quantization
As a result corresponding duty cycle is determined as the target duty ratio of objective circuit, wherein, it is corresponding with peak signal in Target quantization result
Numerical value and numerical value corresponding with direct current signal between difference it is minimum.
Alternatively, detecting the first peak signal in the first common-mode signal of objective circuit and the first direct current signal includes：
The first peak signal in first common-mode signal is detected by the first detection circuit, the first common mode is detected by the second detection circuit
The first direct current signal in signal, wherein, the second detection circuit is different with the first detection circuit；Detect objective circuit second is common
The second peak signal and the second direct current signal in mould signal include：Detected by the first detection circuit in the second common-mode signal
Second peak signal, the second direct current signal in the second common-mode signal is detected by the second detection circuit.
Alternatively, quantification treatment is carried out to the first peak signal and the first direct current signal, obtaining the first quantized result includes：
First peak signal and the first direct current signal are inputted to analog to digital conversion circuit, obtain the first quantized result；Second peak value is believed
Number and the second direct current signal carry out quantification treatment, obtaining the second quantized result includes：Second peak signal and the second direct current are believed
Number to analog to digital conversion circuit input, obtain the second quantized result.
Alternatively, detection objective circuit the first common-mode signal in the first peak signal and the first direct current signal it
Before, this method further includes：The first duty cycle inside objective chip is scanned, wherein, the output stage and objective circuit of objective chip
It is connected；The control word that objective circuit is corrected by the first duty cycle inside objective chip is the first control word；In detection mesh
Before marking the second peak signal and the second direct current signal in the second common-mode signal of circuit, method further includes：Scan target core
The second duty cycle inside piece；The control word that objective circuit is corrected by the second duty cycle inside objective chip is the second control
Word.
Alternatively, it is the first control word bag by the control word of the first duty cycle amendment objective circuit inside objective chip
Include：By the first duty cycle inside objective chip, the number of the first in running order field-effect tube in adjustment objective circuit
To measure as the first quantity, the quantity for adjusting the second in running order field-effect tube is the second quantity, wherein, the of the first quantity
Second field-effect tube of one field-effect tube and the second quantity makes control word be the first control word；Pass through second inside objective chip
The control word that duty cycle corrects objective circuit includes for the second control word：Pass through the second duty cycle inside objective chip, adjustment
The quantity of the first in running order field-effect tube is the 3rd quantity in objective circuit, adjusts in running order second
The quantity of effect pipe is the 4th quantity, wherein, the first field-effect tube of the 3rd quantity and the second field-effect tube of the 4th quantity make
Control word is the second control word.
Alternatively, detecting the first peak signal in the first common-mode signal of objective circuit and the first direct current signal includes：
The first peak signal and the first average value signal in the first common-mode signal of objective circuit are detected, wherein, the first direct current signal
Including the first average value signal, the first average value signal is used for the average value for indicating the first common-mode signal.
Alternatively, objective circuit includes the circuit of high speed transmitter.
To achieve these goals, according to another aspect of the present invention, a kind of signal processing apparatus is additionally provided.The device
Including：Detection unit, in objective circuit, detecting peak signal and direct current signal in common-mode signal, wherein, peak value letter
Number it is used to indicate the peak value of common-mode signal, direct current signal is used to indicate the DC component in common-mode signal；Processing unit, for pair
Peak signal and direct current signal carry out quantification treatment, obtain quantized result, wherein, it is corresponding with peak signal in quantized result
Difference between numerical value and numerical value corresponding with direct current signal, for characterizing the degree of jitter of common-mode signal；Determination unit, is used for
In the case where quantized result meets goal condition, the corresponding duty cycle of quantized result is determined as to the target duty of objective circuit
Than.
To achieve these goals, according to another aspect of the present invention, a kind of storage medium is additionally provided.The storage medium
Program including storage, wherein, equipment is performed at the signal of the embodiment of the present invention where controlling storage medium when program is run
Reason method.
To achieve these goals, according to another aspect of the present invention, a kind of processor is additionally provided.The processor is used for
Operation program, wherein, the signal processing method of execution embodiment of the present invention when program is run.
By the present invention, in objective circuit, peak signal and direct current signal in common-mode signal are detected, wherein, peak value
Signal is used for the peak value for indicating common-mode signal, and direct current signal is used to indicate the DC component in common-mode signal；To peak signal and
Direct current signal carries out quantification treatment, obtains quantized result, wherein, numerical value corresponding with peak signal in quantized result and with it is straight
The difference between the corresponding numerical value of signal is flowed, for characterizing the degree of jitter of common-mode signal；Meet goal condition in quantized result
In the case of, the corresponding duty cycle of quantized result is determined as to the target duty ratio of objective circuit.Due to being believed by detecting common mode
Number direct current signal and peak signal, by the amplitude of output common mode signal jitter, to select optimal quantized result, determine most
Excellent output duty cycle, solve the problems, such as that signal processing efficiency is low, and then improves the effect of signal processing efficiency.
Brief description of the drawings
The attached drawing for forming the part of the application is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its explanation is used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is a kind of schematic diagram of duty cycle imbalance in correlation technique；
Fig. 2 is the schematic diagram of another duty cycle imbalance in correlation technique；
Fig. 3 is the schematic diagram of another duty cycle imbalance in correlation technique；
Fig. 4 is a kind of flow chart of signal processing method according to embodiments of the present invention；
Fig. 5 is a kind of circuit diagram of elimination duty cycle imbalance according to embodiments of the present invention；
Fig. 6 is another circuit diagram for eliminating duty cycle imbalance according to embodiments of the present invention；
Fig. 7 is a kind of circuit diagram of duty cycle processing according to embodiments of the present invention；
Fig. 8 is showing for the relation between a kind of common-mode signal according to embodiments of the present invention, direct current signal and peak signal
It is intended to；And
Fig. 9 is a kind of schematic diagram of signal processing apparatus according to embodiments of the present invention.
Embodiment
It should be noted that in the case where there is no conflict, the feature in embodiment and embodiment in the application can phase
Mutually combination.Below with reference to the accompanying drawings and the present invention will be described in detail in conjunction with the embodiments.
In order to make those skilled in the art more fully understand application scheme, below in conjunction with the embodiment of the present application
Attached drawing, is clearly and completely described the technical solution in the embodiment of the present application, it is clear that described embodiment is only
The embodiment of the application part, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
Member's all other embodiments obtained without making creative work, should all belong to the model of the application protection
Enclose.
It should be noted that term " first " in the description and claims of this application and above-mentioned attached drawing, "
Two " etc. be for distinguishing similar object, without for describing specific order or precedence.It should be appreciated that so use
Data can exchange in the appropriate case, so as to embodiments herein described herein.In addition, term " comprising " and " tool
Have " and their any deformation, it is intended that cover it is non-exclusive include, for example, containing series of steps or unit
Process, method, system, product or equipment are not necessarily limited to those steps clearly listed or unit, but may include without clear
It is listing to Chu or for the intrinsic other steps of these processes, method, product or equipment or unit.
Embodiment 1
An embodiment of the present invention provides a kind of signal processing method.
Fig. 4 is a kind of flow chart of signal processing method according to embodiments of the present invention.As shown in figure 4, this method includes
Following steps：
Step S402, in objective circuit, detects peak signal and direct current signal in common-mode signal.
In the technical solution that the application above-mentioned steps S402 is provided, in objective circuit, the peak in common-mode signal is detected
Value signal and direct current signal, wherein, peak signal is used for the peak value for indicating common-mode signal, and direct current signal is used to indicate common-mode signal
In DC component.
In this embodiment, objective circuit is the circuit of duty cycle to be modified, common-mode signal namely common mode electrical level.In target
In circuit, peak signal and direct current signal in common-mode signal are detected, two common mode detection electricity can be added in scanning output stage
Road, wherein, a common mode detection circuit can be peak detection circuit, for detecting the peak signal in common-mode signal, that is,
The maximal jitter amplitude of common mode electrical level is detected, wherein, peak signal is used for the peak value for indicating common-mode signal；Another common mode detects
Circuit can be DC detection circuit, can obtain the direct current signal of common-mode signal by a capacitive filter, direct current letter
Number it is used to indicate DC component in common-mode signal, can is the average value of common-mode signal.
Alternatively, the common mode detection resistance of the common mode detection circuit of the embodiment is controlled by switch, can so calibrated
After completion, selection closes this common mode detection circuit to save power consumption, can also turn on for a long time to detect common mode situation.
Step S404, carries out quantification treatment to peak signal and direct current signal, obtains quantized result.
In the technical solution that the application above-mentioned steps S404 is provided, peak signal and direct current signal are carried out at quantization
Reason, obtains quantized result, wherein, numerical value corresponding with peak signal and numerical value corresponding with direct current signal in quantized result it
Between difference, for characterizing the degree of jitter of common-mode signal.
After the peak signal in detecting common-mode signal and direct current signal, peak signal and direct current signal are quantified
Processing, obtains quantized result.Alternatively, peak signal and the corresponding voltage signal of direct current signal are sent into an analog-to-digital conversion electricity
In road (Analog-to-Digital Converter, referred to as ADC), pass through i.e. recognizable voltage signal inside digit chip
The size of amplitude simultaneously stores its corresponding amplitude, obtains quantized result, corresponding with peak signal in the quantized result
Numerical value and numerical value corresponding with direct current signal between difference, for characterizing the degree of jitter of common-mode signal, so as to detect defeated
Go out the amplitude size of common mode electrical level shake.Common-mode signal shake it is bigger in the case of, numerical value corresponding with peak signal and with
Difference between the corresponding numerical value of direct current signal is bigger；It is corresponding with peak signal in the case where common-mode signal shake is smaller
Numerical value and numerical value corresponding with direct current signal between difference with regard to smaller.
Step S406, in the case where quantized result meets goal condition, the corresponding duty cycle of quantized result is determined as
The target duty ratio of objective circuit.
In the technical solution that the application above-mentioned steps S406 is provided, in the case where quantized result meets goal condition,
The corresponding duty cycle of quantized result is determined as to the target duty ratio of objective circuit.
Quantification treatment is being carried out to peak signal and direct current signal, after obtaining quantized result, is meeting mesh in quantized result
In the case of mark condition, the corresponding duty cycle of quantized result is determined as to the target duty ratio of objective circuit.Alternatively, due to
In the case that common-mode signal shake is smaller, the difference between numerical value corresponding with peak signal and numerical value corresponding with direct current signal
With regard to smaller, the difference between the numerical value corresponding with peak signal and numerical value corresponding with direct current signal in quantized result is minimum
In the case of, duty cycle corresponding with quantized result is determined as to the target duty ratio of objective circuit, that is, the target duty ratio
For optimal output duty cycle.The duty cycle that chip internal can be scanned by digital circuit corrects the control word of circuit, passes through
Digital circuit records and compares the output of ADC as a result, therefrom selecting optimal duty cycle as a result, and being configured and being applied to duty
Than correcting circuit, so that the output duty cycle effect being optimal.
It should be noted that the signal processing method of the embodiment and output duty cycle need not be monitored in real time, in chip
Before normal work, in chip course of normal operation or in the gap of chip normal work, can start detection, can be with
Influence to normal chip operations is reduced according to the demand of system as much as possible.
The embodiment detects peak signal and direct current signal in common-mode signal in objective circuit, wherein, peak signal
For indicating the peak value of common-mode signal, direct current signal is used to indicate the DC component in common-mode signal；To peak signal and direct current
Signal carries out quantification treatment, obtains quantized result, wherein, numerical value corresponding with peak signal in quantized result and believe with direct current
Difference between number corresponding numerical value, for characterizing the degree of jitter of common-mode signal；Meet the feelings of goal condition in quantized result
Under condition, the corresponding duty cycle of quantized result is determined as to the target duty ratio of objective circuit.Due to by detecting common-mode signal
Direct current signal and peak signal, by the amplitude of output common mode signal jitter, to select optimal quantized result, determine optimal
Output duty cycle, solve the problems, such as that signal processing efficiency is low, and then improves the effect of signal processing efficiency.
As an alternative embodiment, step S402, detects the peak signal and direct current signal bag in common-mode signal
Include：Under the first control word, the first peak signal and the first direct current signal in the first common-mode signal are detected, wherein, the first control
Word processed is used for the degree of jitter for controlling the first common-mode signal, and peak signal includes the first peak signal, and the first peak signal is used for
Indicate the first peak value of the first common-mode signal, direct current signal includes the first direct current signal, and the first direct current signal is used to indicate first
The first DC component in common-mode signal；Step S404, quantification treatment is carried out to peak signal and direct current signal, obtains quantifying knot
Fruit includes：Quantification treatment is carried out to the first peak signal and the first direct current signal, obtains the first quantized result, wherein, quantify knot
Fruit includes the first quantized result.
In this embodiment, control word can serve to indicate that the degree of jitter of common-mode signal, believe peak signal and direct current
The control word of difference minimum between number corresponding numerical value is to represent that the degree of jitter of common-mode signal is minimum.The embodiment passes through number
The duty cycle of word circuit sweeps chip internal corrects the control word of circuit, can by adjusting the P-channel metal oxygen in circuit
Compound semiconductor field (Positive Channel Metal Oxide Semiconductor, referred to as PMOS) and N
NMOS N-channel MOS N field-effect tube (Negative Channel Metal Oxide Semiconductor, referred to as
For NMOS) quantity using reach correct circuit control word as the first control word.Under the first control word, output the first common mode letter
Number, the first peak signal and the first direct current signal in first common-mode signal are detected, can be by being added in scanning output stage
Peak detection circuit detect the first common-mode signal in the first peak signal, that is, detection the first common-mode signal maximum tremble
Dynamic amplitude, wherein, the first peak signal is used for the peak value for indicating the first common-mode signal；It can also lead in DC detection circuit
Cross a capacitive filter and obtain the first direct current signal of the first common-mode signal, which is used to indicate the first common mode
The first DC component in signal, can be the average value of the first common-mode signal.
After the first peak signal in detecting the first common-mode signal and the first direct current signal, to the first peak signal and
First direct current signal carries out quantification treatment, the first quantized result is obtained, to judge whether output common mode characteristic is optimal.
As an alternative embodiment, step S402, peak signal in common-mode signal and direct current signal are detected also
Including：Under the second control word, the second peak signal and the second direct current signal in the second common-mode signal of objective circuit are detected,
Wherein, the second control word is used for the degree of jitter for controlling the second common-mode signal, and peak signal includes the second peak signal, first peak
Value signal is used for the second peak value for indicating the second common-mode signal, and direct current signal includes the second direct current signal, and the second direct current signal is used
In indicating the second DC component in the second common-mode signal；Step S404, quantification treatment is carried out to peak signal and direct current signal,
Obtaining quantized result includes：Quantification treatment is carried out to the second peak signal and the second direct current signal, obtains the second quantized result, its
In, quantized result includes the second quantized result；Step S406, in the case where quantized result meets goal condition, will quantify to tie
The target duty ratio that the corresponding duty cycle of fruit is determined as objective circuit includes：From the first quantized result and the second quantized result really
Surely the Target quantization of goal condition is met as a result, and the corresponding duty cycle of Target quantization result to be determined as to the target of objective circuit
Duty cycle, wherein, the difference in Target quantization result between numerical value corresponding with peak signal and numerical value corresponding with direct current signal
Value is minimum.
The embodiment corrects the control word of circuit by the duty cycle of digital circuit scanning chip internal, can pass through tune
The quantity of PMOS field-effect tube and NMOS field-effect tube in whole circuit corrects the control word of circuit to reach as the second control word.
Under the second control word, the second common-mode signal is exported, detects the second peak signal and the second direct current in second common-mode signal
Signal, can by the second peak signal in detecting the second common-mode signal in peak detection circuit that scanning output stage adds,
That is, the maximal jitter amplitude of the second common-mode signal of detection, wherein, the second peak signal is used for the peak for indicating the second common-mode signal
Value；The second direct current signal of the second common-mode signal can also be obtained by a capacitive filter in DC detection circuit, should
Second direct current signal is used to indicate the second DC component in the second common-mode signal, can be the average value of the second common-mode signal.
After the second peak signal in detecting the second common-mode signal and the second direct current signal, to the second peak signal and
Second direct current signal carries out quantification treatment, the second quantized result is obtained, to judge whether output common mode characteristic is optimal.
Alternatively, the Target quantization of goal condition is determined for compliance with from the first quantized result and the second quantized result as a result,
That is, the corresponding numerical value of peak signal and number corresponding with direct current signal are determined from the first quantized result and the second quantized result
The Target quantization of difference minimum between value is as a result, between the corresponding numerical value of the peak signal and numerical value corresponding with direct current signal
Difference minimum corresponding to common-mode signal output common mode characteristic it is optimal, which is determined
For the target duty ratio of objective circuit, that is, being the optimal duty cycle of objective circuit, and then configured and repaiied applied to duty cycle
Positive circuit, so that the output duty cycle effect being optimal.
As an alternative embodiment, the first peak signal and the in the first common-mode signal of detection objective circuit
One direct current signal includes：The first peak signal in first common-mode signal is detected by the first detection circuit, passes through the second detection
The first direct current signal in the first common-mode signal of electric circuit inspection, wherein, the second detection circuit is different with the first detection circuit；Detection
The second peak signal and the second direct current signal in second common-mode signal of objective circuit include：Detected by the first detection circuit
The second peak signal in second common-mode signal, the second direct current detected by the second detection circuit in the second common-mode signal are believed
Number.
In this embodiment, the first detection circuit can be common mode detection circuit, that is, be peak detection circuit, the peak
It is worth detection circuit and accesses the first common-mode signal.The first peak signal and the first direct current signal in the first common-mode signal is detected
When, the first peak signal in the first common-mode signal is detected by the first detection circuit, that is, the first common-mode signal of detection is most
Big jitter amplitude；Second detection circuit of the embodiment is also common mode detection circuit, can be DC detection circuit, which examines
Slowdown monitoring circuit can access the first common-mode signal by capacitive filter, obtain the direct current signal of the first common-mode signal.
The embodiment can also detect the second peak signal in the second common-mode signal by the first detection circuit, that is,
Detect the maximal jitter amplitude of the second common-mode signal；Second detection circuit of the embodiment can also be accessed by capacitive filter
Second common-mode signal, obtains the direct current signal of the second common-mode signal.
First detection circuit of the embodiment and the detection resistance of the second detection circuit can be controlled by switch, can be with
After calibration is complete, selection closes this detection circuit to save power consumption, can also turn on for a long time to detect common mode situation.
As an alternative embodiment, carrying out quantification treatment to the first peak signal and the first direct current signal, obtain
First quantized result includes：First peak signal and the first direct current signal are inputted to analog to digital conversion circuit, obtain the first quantization
As a result；Quantification treatment is carried out to the second peak signal and the second direct current signal, obtaining the second quantized result includes：By the second peak value
Signal and the second direct current signal are inputted to analog to digital conversion circuit, obtain the second quantized result.
The embodiment is carrying out quantification treatment to the first peak signal and the first direct current signal, obtains the first quantized result
When, it can be completed by analog to digital conversion circuit ADC.By the first peak signal and the first direct current signal in the first common-mode signal
Input, first peak signal voltage signal corresponding with first direct current signal can be turned to modulus to analog to digital conversion circuit
Circuit input is changed, can identify the size of voltage signal amplitude inside digit chip, and its respective magnitudes is stored；Right
Second peak signal and the second direct current signal carry out quantification treatment, can be by the second common-mode signal when obtaining the second quantized result
In the second peak signal and the second direct current signal to analog to digital conversion circuit input, can by second peak signal and this second
The corresponding voltage signal of direct current signal is inputted to analog to digital conversion circuit, and the big of voltage signal amplitude can be identified inside digit chip
It is small, and its respective magnitudes is stored.
As an alternative embodiment, detection objective circuit the first common-mode signal in the first peak signal and
Before first direct current signal, this method further includes：Scan objective chip inside the first duty cycle, wherein, objective chip it is defeated
Go out level with objective circuit to be connected；The control word that objective circuit is corrected by the first duty cycle inside objective chip is the first control
Word processed；Before the second peak signal and the second direct current signal in the second common-mode signal of detection objective circuit, this method is also
Including：Scan the second duty cycle inside objective chip；Objective circuit is corrected by the second duty cycle inside objective chip
Control word is the second control word.
In this embodiment, the control word of the duty cycle amendment circuit of chip internal is scanned by digital circuit.Detecting
Before the first peak signal and the first direct current signal in first common-mode signal of objective circuit, target is scanned by digital circuit
First duty cycle of chip internal, the output stage of the objective chip can be connected with objective circuit.In scanning objective chip
After first duty cycle in portion, the control word that objective circuit is corrected by the first duty cycle inside objective chip is the first control
Word, first control word are used for the jitter amplitude for controlling the first common-mode signal；In the second common-mode signal of detection objective circuit
The second peak signal and the second direct current signal before, pass through digital circuit scan objective chip inside the second duty cycle.
After scanning the second duty cycle inside objective chip, the control of objective circuit is corrected by the second duty cycle inside objective chip
Word processed is the second control word, which is used for the jitter amplitude for controlling the second common-mode signal.
Alternatively, the embodiment by digital circuit scan chip internal duty cycle correct circuit control word when,
It can go regularly to configure the rise and fall driving force of all chip output stages by the result of emulation or a small amount of chip testing,
The time on rise and fall edge can also be adjusted by adjusting the switch intensity of output stage, or the duty of adjustment prime output
Than by adjusting the quantity of PMOS or NMOS to introduce unbalanced duty cycle, and then offsetting the duty cycle imbalance of output.
As an alternative embodiment, the control of objective circuit is corrected by the first duty cycle inside objective chip
Word includes for the first control word：By the first duty cycle inside objective chip, adjust in running order in objective circuit
The quantity of first field-effect tube is the first quantity, and the quantity for adjusting the second in running order field-effect tube is the second quantity,
Wherein, the first field-effect tube of the first quantity and the second field-effect tube of the second quantity make control word be the first control word；Pass through
The control word that the second duty cycle inside objective chip corrects objective circuit includes for the second control word：Inside objective chip
The second duty cycle, the quantity for adjusting in running order the first field-effect tube in objective circuit is the 3rd quantity, at adjustment
In the quantity of the second field-effect tube of working status be the 4th quantity, wherein, the first field-effect tube of the 3rd quantity and the 4th number
Second field-effect tube of amount makes control word be the second control word.
In this embodiment, objective circuit includes the first field-effect tube and the second field-effect tube, which can
Think PMOS field-effect tube, the second field-effect tube can be NMOS field-effect tube.The first duty inside by objective chip
When control word than correcting objective circuit is the first control word, mesh can be adjusted by the first duty cycle inside objective chip
The quantity for marking the first field-effect tube in running order in circuit is the first quantity, adjusts second in running order effect
Should the quantity of pipe be the second quantity so that the control word of objective circuit is modified to the first control word；Passing through objective chip
When the control word that the second internal duty cycle corrects objective circuit is the second control word, second inside objective chip can be passed through
Duty cycle, the quantity for adjusting the first field-effect tube in running order in objective circuit is the 3rd quantity, and adjustment is in work
The quantity of second field-effect tube of state is the 4th quantity, so that the control word of objective circuit is modified to the 4th control word.
Alternatively, which corrects the control word of circuit by the above method, under different control words, detects common mode
Peak signal and direct current signal in signal, carry out quantification treatment to peak signal and direct current signal, obtain quantized result, will
To different control words under corresponding quantized result be compared, therefrom select optimal quantized result, that is, selection output
Change the quantized result of the difference minimum in result between numerical value corresponding with peak signal and numerical value corresponding with direct current signal, will
Duty cycle configuration corresponding with optimal quantized result is applied to duty cycle and corrects in circuit, so that the output duty being optimal
Than effect, signal processing efficiency is improved.
As an alternative embodiment, the first peak signal and the in the first common-mode signal of detection objective circuit
One direct current signal includes：The first peak signal and the first average value signal in the first common-mode signal of objective circuit are detected, its
In, the first direct current signal includes the first average value signal, and the first average value signal is used for the average value for indicating the first common-mode signal.
In this embodiment, direct current signal can be the average value of common-mode signal, thus the first direct current signal can be the
The average value of one common-mode signal, the average value for the second common-mode signal that the second direct current signal can be.In detection objective circuit
During the first peak signal and the first direct current signal in the first common-mode signal, in the first common-mode signal that objective circuit can be detected
The first peak signal and the first average value signal, first average value signal be used for indicate the first common-mode signal average value.
Alternatively, the second peak signal in the second common-mode signal for detecting objective circuit and during the second direct current signal,
The second peak signal and the second average value signal in the second common-mode signal of objective circuit, second average value letter can be detected
Number be used for indicate the second common-mode signal average value, with realize compare output common mode peak value and the method automatic circuit of average
Duty ratio characteristics.
As an alternative embodiment, objective circuit includes the circuit of high speed transmitter.
In this embodiment, objective circuit can be the circuit of high speed transmitter, can be high speed interconnection circuit.It is optional
Ground, the rise and fall driving force or prime duty cycle of scanning output stage, while detect the width of output common mode electric signal shake
Spend to judge whether output common mode characteristic is optimal, so as to reach optimal output duty cycle, so that high speed transmitter signal matter
Measure improvement.
Detected using duty cycle provided in an embodiment of the present invention and correct circuit, detection output duty cycle in real time can be reached
Energy.Under different chip technology deviations, it also can go to be modified for different duty ratio characteristics, be accounted for what is be optimal
Sky compares effect.The scheme that the embodiment is provided is opened in the short time or for a long time, is adding original circuit design
In the middle, almost also without any harmful effect.
It should be noted that step shown in the flowchart of the accompanying drawings can be in such as a group of computer-executable instructions
Performed in computer system, although also, show logical order in flow charts, in some cases, can be with not
The order being same as herein performs shown or described step.
Embodiment 2
Technical scheme is illustrated with reference to preferred embodiment.
In this embodiment, in order to eliminate the phenomenon of the imbalance of the duty cycle in circuit, emulation or a small amount of core can be passed through
The result of built-in testing goes regularly to configure the rise and fall driving force of all chip output stages.
Fig. 5 is a kind of circuit diagram of elimination duty cycle imbalance according to embodiments of the present invention.As shown in figure 5, pass through
The switch intensity of output stage is adjusted to adjust the time on rise and fall edge, or the duty cycle that adjustment prime exports, wherein, including
PMOS field-effect tube P1 ... Pn, NMOS field-effect tube N1 ... Nn, wherein, n can be used to indicate that corresponding field-effect tube
Number, and be the integer more than 1, Pn is used to represent n-th of PMOS field-effect tube, and Nn is used to represent n-th of NMOS field-effect tube.
Fig. 6 is another circuit diagram for eliminating duty cycle imbalance according to embodiments of the present invention.It is as shown in fig. 6, logical
The quantity of adjustment PMOS or NMOS is crossed, to introduce unbalanced duty cycle, and then offsets the duty cycle imbalance of output.
Fig. 7 is a kind of circuit diagram of duty cycle processing according to embodiments of the present invention.As shown in fig. 7, the embodiment
Increase by two test points, the average value of a detection common mode electrical level, the peak value of a detection common mode electrical level.Added in output stage
Two common mode detection circuits, the common mode detection resistance of common mode detection circuit are controlled by switch, can be selected after calibration is complete
This detection circuit is closed to save power consumption, can also conduction detection common mode situation for a long time.The common-mode signal in left side accesses a peak
It is worth detection circuit, to detect the peak signal of common-mode signal, that is, the maximal jitter amplitude of detection common mode electrical level, right side is total to
Mould signal obtains its DC component by a capacitive filter.And then peak signal and DC component are passed through into the ADC amounts of progress
Change.
Fig. 8 is showing for the relation between a kind of common-mode signal according to embodiments of the present invention, direct current signal and peak signal
It is intended to.As shown in figure 8, in the case where common-mode signal shake is bigger, between direct current signal and the corresponding numerical value of peak signal
Difference is bigger.Direct current signal and the corresponding voltage signal of peak signal can be sent into an analog to digital conversion circuit, passed through
It can recognize that the size of its signal amplitude inside digit chip, and its corresponding amplitude stored.
By the above method, according to adjustment relation, the duty cycle that chip internal design is scanned by digital circuit corrects electricity
The control word on road, circuit structure including but not limited to as shown in Figure 5 and Figure 6, is recorded by digital circuit and compares the defeated of ADC
Go out as a result, difference minimum control word represents that output common mode shake is minimum, and then therefrom selects optimal as a result, and being configured
Circuit is corrected applied to duty cycle so as to the output duty cycle effect being optimal, so as to reach by comparing output common mode peak value
With the method for average, the purpose of the duty ratio characteristics of automatic circuit, improves the efficiency that duty cycle is handled.
It should be noted that the embodiment and output duty cycle need not be monitored in real time, before chip normal work, core
It in piece course of normal operation, or can start detection in the gap of chip normal work, can be use up according to system requirements
Influence of the possible reduction to normal work.
Circuit is corrected in the duty cycle detection provided using the embodiment of the present invention, can reach detection output duty cycle in real time
The purpose of performance, can go to be modified, to reach most under different chip technology deviations for different duty ratio characteristics
Excellent duty cycle effect.The scheme short time or open for a long time that the embodiment is provided, thus the embodiment is added
Among the original circuit design entered, also almost without any harmful effect.
Embodiment 3
The embodiment of the present invention additionally provides a kind of signal processing processing unit.It should be noted that the signal of the embodiment
Processing unit can be used for the signal processing method for performing the embodiment of the present invention.
Fig. 9 is a kind of schematic diagram of signal processing apparatus according to embodiments of the present invention.As shown in figure 9, the device can be with
Including：Detection unit 10, processing unit 20 and determination unit 30.
Detection unit 10, in objective circuit, detecting peak signal and direct current signal in common-mode signal, wherein,
Peak signal is used for the peak value for indicating common-mode signal, and direct current signal is used to indicate the DC component in common-mode signal.
Processing unit 20, for carrying out quantification treatment to peak signal and direct current signal, obtains quantized result, wherein, amount
Change the difference between numerical value corresponding with peak signal and the numerical value corresponding with direct current signal in result, for characterizing common mode letter
Number degree of jitter.
Determination unit 30, in the case of meeting goal condition in quantized result, by the corresponding duty cycle of quantized result
It is determined as the target duty ratio of objective circuit.
The embodiment in objective circuit, detects peak signal and direct current letter in common-mode signal by detection unit 10
Number, wherein, peak signal is used for the peak value for indicating common-mode signal, and direct current signal is used to indicate the DC component in common-mode signal,
Quantification treatment is carried out to peak signal and direct current signal by processing unit 20, obtains quantized result, wherein, in quantized result
Difference between numerical value corresponding with peak signal and numerical value corresponding with direct current signal, for characterizing the shake journey of common-mode signal
Degree, by determination unit 30 in the case where quantized result meets goal condition, the corresponding duty cycle of quantized result is determined as
The target duty ratio of objective circuit.Due to the direct current signal and peak signal by detecting common-mode signal, to pass through output common mode
The amplitude of signal jitter, selects optimal quantized result, determines optimal output duty cycle, and it is low to solve signal processing efficiency
Problem, and then improve the effect of signal processing efficiency.
Embodiment 4
The embodiment of the present invention additionally provides a kind of storage medium.The storage medium includes the program of storage, wherein, in program
Equipment performs the signal processing method of the embodiment of the present invention where controlling storage medium during operation.
Embodiment 5
The embodiment of the present invention additionally provides a kind of processor.The processor is used for operation program, wherein, program is held when running
The signal processing method of the row embodiment of the present invention.
Obviously, those skilled in the art should be understood that above-mentioned each module of the invention or each step can be with general
Computing device realize that they can be concentrated on single computing device, or be distributed in multiple computing devices and formed
Network on, alternatively, they can be realized with the receivable program code of computing device, it is thus possible to which they are stored
Performed in the storage device by computing device, either they are fabricated to respectively each integrated circuit modules or by they
In multiple modules or step be fabricated to single integrated circuit module to realize.In this way, the present invention be not restricted to it is any specific
Hardware and software combines.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the invention, for the skill of this area
For art personnel, the invention may be variously modified and varied.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should all be included in the protection scope of the present invention.
Claims (12)
- A kind of 1. signal processing method, it is characterised in that including：In objective circuit, peak signal and direct current signal in common-mode signal are detected, wherein, the peak signal is used to indicate The peak value of the common-mode signal, the direct current signal are used to indicate the DC component in the common-mode signal；Quantification treatment is carried out to the peak signal and the direct current signal, obtains quantized result, wherein, in the quantized result Numerical value corresponding with the peak signal and numerical value corresponding with the direct current signal between difference, it is described common for characterizing The degree of jitter of mould signal；In the case where the quantized result meets goal condition, the corresponding duty cycle of the quantized result is determined as the mesh Mark the target duty ratio of circuit.
- 2. according to the method described in claim 1, it is characterized in that,Detecting the peak signal in the common-mode signal and direct current signal includes：Under the first control word, detection the first common mode letter The first peak signal and the first direct current signal in number, wherein, first control word is used to control first common-mode signal Degree of jitter, the peak signal includes first peak signal, and first peak signal is used to indicate described first First peak value of common-mode signal, the direct current signal include first direct current signal, and first direct current signal is used to indicate The first DC component in first common-mode signal；Quantification treatment is carried out to the peak signal and the direct current signal, obtaining the quantized result includes：To described first Peak signal and first direct current signal carry out quantification treatment, obtain the first quantized result, wherein, the quantized result includes First quantized result.
- 3. according to the method described in claim 2, it is characterized in that,Detect the peak signal in the common-mode signal and direct current signal further includes：Under the second control word, the target is detected The second peak signal and the second direct current signal in second common-mode signal of circuit, wherein, second control word is used to control The degree of jitter of second common-mode signal, the peak signal include second peak signal, first peak signal For indicating the second peak value of second common-mode signal, the direct current signal includes second direct current signal, and described second Direct current signal is used to indicate the second DC component in second common-mode signal；Quantification treatment is carried out to the peak signal and the direct current signal, obtaining the quantized result includes：To described second Peak signal and second direct current signal carry out quantification treatment, obtain the second quantized result, wherein, the quantized result includes Second quantized result；In the case where the quantized result meets the goal condition, the corresponding duty cycle of the quantized result is determined as institute Stating the target duty ratio of objective circuit includes：It is determined for compliance with from first quantized result and second quantized result described The corresponding duty cycle of the Target quantization result as a result, and is determined as the mesh of the objective circuit by the Target quantization of goal condition Duty cycle is marked, wherein, numerical value corresponding with the peak signal and corresponding with the direct current signal in the Target quantization result Numerical value between difference it is minimum.
- 4. according to the method described in claim 3, it is characterized in that,Detecting first peak signal in the first common-mode signal of the objective circuit and first direct current signal includes： First peak signal in first common-mode signal is detected by the first detection circuit, is detected by the second detection circuit First direct current signal in first common-mode signal, wherein, second detection circuit and first detection circuit It is different；Detecting second peak signal in the second common-mode signal of the objective circuit and second direct current signal includes： Second peak signal in second common-mode signal is detected by first detection circuit, is detected by described second Second direct current signal in second common-mode signal described in electric circuit inspection.
- 5. according to the method described in claim 4, it is characterized in that,Quantification treatment is carried out to first peak signal and first direct current signal, obtains the first quantized result bag Include：First peak signal and first direct current signal are inputted to analog to digital conversion circuit, described first is obtained and quantifies knot Fruit；Quantification treatment is carried out to second peak signal and second direct current signal, obtains the second quantized result bag Include：Second peak signal and second direct current signal are inputted to analog to digital conversion circuit, described second is obtained and quantifies knot Fruit.
- 6. according to the method described in claim 3, it is characterized in that,First peak signal and first direct current letter in first common-mode signal for detecting the objective circuit Before number, the method further includes：The first duty cycle inside objective chip is scanned, wherein, the output stage of the objective chip It is connected with the objective circuit；The control of the objective circuit is corrected by first duty cycle inside the objective chip Word processed is first control word；Second peak signal and second direct current letter in second common-mode signal for detecting the objective circuit Before number, the method further includes：Scan the second duty cycle inside objective chip；Described in inside the objective chip The control word that second duty cycle corrects the objective circuit is second control word.
- 7. according to the method described in claim 6, it is characterized in that,The control word of the objective circuit is corrected as described the by first duty cycle inside the objective chip One control word includes：By first duty cycle inside the objective chip, adjust and work is in the objective circuit The quantity of first field-effect tube of state is the first quantity, and the quantity of second field-effect tube of the adjustment in the working status is Second quantity, wherein, first field-effect tube of first quantity and second field-effect tube of second quantity It is first control word to make the control word；The control word of the objective circuit is corrected as described the by second duty cycle inside the objective chip Two control words include：By second duty cycle inside the objective chip, adjust in the objective circuit in described The quantity of first field-effect tube of working status is the 3rd quantity, second effect of the adjustment in the working status Should the quantity of pipe be the 4th quantity, wherein, first field-effect tube of the 3rd quantity and the 4th quantity it is described Second field-effect tube makes the control word be second control word.
- 8. method as claimed in any of claims 2 to 7, it is characterised in thatDetect first peak signal in first common-mode signal of the objective circuit and first direct current signal Including：First peak signal and the first average value signal in first common-mode signal of the objective circuit are detected, Wherein, first direct current signal includes first average value signal, and first average value signal is used to indicating described the The average value of one common-mode signal.
- 9. method as claimed in any of claims 1 to 7, it is characterised in that the objective circuit includes sending out at a high speed Send the circuit of machine.
- A kind of 10. signal processing apparatus, it is characterised in that including：Detection unit, in objective circuit, detecting peak signal and direct current signal in common-mode signal, wherein, the peak Value signal is used for the peak value for indicating the common-mode signal, and the direct current signal is used to indicate the direct current point in the common-mode signal Amount；Processing unit, for carrying out quantification treatment to the peak signal and the direct current signal, obtains quantized result, wherein, The difference between numerical value corresponding with the peak signal and numerical value corresponding with the direct current signal in the quantized result, For characterizing the degree of jitter of the common-mode signal；Determination unit, in the case of meeting goal condition in the quantized result, by the corresponding duty of the quantized result Than the target duty ratio for being determined as the objective circuit.
- A kind of 11. storage medium, it is characterised in that the storage medium includes the program of storage, wherein, run in described program When control the storage medium where signal processing method in equipment perform claim requirement 1 to 9 described in any one.
- A kind of 12. processor, it is characterised in that the processor is used for operation program, wherein, right of execution when described program is run Profit requires the signal processing method described in any one in 1 to 9.
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