CN108037345B - Signal processing method, signal processing device, storage medium and processor - Google Patents
Signal processing method, signal processing device, storage medium and processor Download PDFInfo
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Abstract
The invention discloses a signal processing method, a signal processing device, a storage medium and a processor. The method comprises the following steps: in a target circuit, detecting a peak signal and a direct current signal in a common mode signal, wherein the peak signal is used for indicating a peak value of the common mode signal, and the direct current signal is used for indicating a direct current component in the common mode signal; quantizing the peak signal and the direct current signal to obtain a quantization result, wherein a difference value between a numerical value corresponding to the peak signal and a numerical value corresponding to the direct current signal in the quantization result is used for representing the jitter degree of the common mode signal; and under the condition that the quantization result meets the target condition, determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit. The invention achieves the effect of improving the signal processing efficiency.
Description
Technical Field
The present invention relates to the field of circuits, and in particular, to a signal processing method, apparatus, storage medium, and processor.
Background
Currently, in high speed interconnect circuits, the quality of the transmitter output signal determines the maximum rate that can be achieved by the communication device. High speed interconnect circuits generally require differential low swing outputs, impedance matching, etc. for long distance transmission to improve signal quality and reduce electromagnetic Interference (EMI). The duty cycle of the output signal is an important factor in measuring the quality of the differential signal. Duty cycle mismatch can have a large impact on output signal quality as well as EMI.
Duty cycle misalignment can be roughly divided into two cases, the first case being shown in fig. 1. Fig. 1 is a schematic diagram of duty ratio offset according to a related art. The differential pair signal positive and negative terminals are symmetrical, but the high level of the positive terminal (low level of the negative terminal) is narrower than the low level of the positive terminal (high level of the negative terminal). Because of complete symmetry, the differential pair common mode output is still stable, but the widths of high and low levels are different when reflected on the differential output, so when a receiving end recovers signals, the narrow high level can affect the margin of signal sampling, and the difficulty of signal recovery is increased. The duty ratio distortion is generally that a part of circuits in a chip are single-ended signals, and the duty ratio distortion characteristic of the original single-ended signals is maintained when the single-ended signals are converted into differential signals. Such duty cycle mismatch can be largely eliminated as long as the chip internal clock data is kept fully differential.
The second case is shown in fig. 2. Fig. 2 is a schematic diagram of duty ratio offset according to another related art. The driving force of the signal rising and falling cannot be completely consistent whether the signal is in the chip or is output to the outside of the chip. Even very careful design can create the situation shown in fig. 2 at process variations when there are areas within the chip that are heavily loaded, or level shifted, or output driven off-chip loads. Even if the subsequent buffer circuit can adjust the driving capability of the rising and falling edges to be uniform, the differential signal is in the state shown in fig. 3, and the jitter of the common mode signal may become larger. Fig. 3 is a schematic diagram of duty ratio offset according to another related art.
Therefore, although the differential signals of fig. 2 and 3 are still good in duty ratio, the common mode signal has jitter, and the rising and falling processes may be asymmetric, and such differential signals have several problems as follows:
(1) when the common mode signal is transmitted on the transmission line, electromagnetic interference can be generated and cannot be counteracted;
(2) the asymmetry of the rising and falling edges causes the anti-interference capability of signals to common-mode noise to be poor, so the signal quality at a receiving end is poor;
(3) common mode jitter also affects the power supply of the output stage, increasing Inter-Symbol Interference (ISI) jitter of the output stage. There is a problem in that the signal processing efficiency is low.
Aiming at the problem of low signal processing efficiency in the prior art, no effective solution is provided at present.
Disclosure of Invention
It is a primary object of the present invention to provide a signal processing method, apparatus, storage medium and processor to solve at least the problem of low signal processing efficiency.
In order to achieve the above object, according to one aspect of the present invention, there is provided a signal processing method. The method comprises the following steps: in a target circuit, detecting a peak signal and a direct current signal in a common mode signal, wherein the peak signal is used for indicating a peak value of the common mode signal, and the direct current signal is used for indicating a direct current component in the common mode signal; quantizing the peak signal and the direct current signal to obtain a quantization result, wherein a difference value between a numerical value corresponding to the peak signal and a numerical value corresponding to the direct current signal in the quantization result is used for representing the jitter degree of the common mode signal; and under the condition that the quantization result meets the target condition, determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit.
Optionally, detecting the peak signal and the dc signal in the common mode signal comprises: detecting a first peak signal and a first direct current signal in a first common mode signal under a first control word, wherein the first control word is used for controlling the jitter degree of the first common mode signal, the peak signal comprises a first peak signal, the first peak signal is used for indicating a first peak value of the first common mode signal, the direct current signal comprises a first direct current signal, and the first direct current signal is used for indicating a first direct current component in the first common mode signal; quantizing the peak signal and the direct current signal to obtain a quantization result, wherein the quantization result comprises: and quantizing the first peak signal and the first direct current signal to obtain a first quantization result, wherein the quantization result comprises a first quantization result.
Optionally, the detecting the peak signal and the dc signal in the common mode signal further includes: detecting a second peak signal and a second direct current signal in a second common mode signal of the target circuit under a second control word, wherein the second control word is used for controlling the jitter degree of the second common mode signal, the peak signal comprises the second peak signal, the second peak signal is used for indicating a second peak value of the second common mode signal, the direct current signal comprises the second direct current signal, and the second direct current signal is used for indicating a second direct current component in the second common mode signal; quantizing the peak signal and the direct current signal to obtain a quantization result, wherein the quantization result comprises: quantizing the second peak signal and the second direct current signal to obtain a second quantization result, wherein the quantization result comprises a second quantization result; determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit when the quantization result meets the target condition comprises: and determining a target quantization result meeting the target condition from the first quantization result and the second quantization result, and determining a duty ratio corresponding to the target quantization result as a target duty ratio of the target circuit, wherein the difference between a value corresponding to the peak signal and a value corresponding to the direct current signal in the target quantization result is the smallest.
Optionally, detecting the first peak signal and the first dc signal in the first common-mode signal of the target circuit includes: detecting a first peak signal in the first common-mode signal through a first detection circuit, and detecting a first direct current signal in the first common-mode signal through a second detection circuit, wherein the second detection circuit is different from the first detection circuit; detecting a second peak signal and a second dc signal in a second common mode signal of a target circuit includes: a second peak signal in the second common mode signal is detected by the first detection circuit, and a second direct current signal in the second common mode signal is detected by the second detection circuit.
Optionally, the quantizing the first peak signal and the first dc signal to obtain a first quantization result includes: inputting the first peak signal and the first direct current signal to an analog-to-digital conversion circuit to obtain a first quantization result; performing quantization processing on the second peak signal and the second direct current signal to obtain a second quantization result, including: and inputting the second peak signal and the second direct current signal to the analog-to-digital conversion circuit to obtain a second quantization result.
Optionally, before detecting the first peak signal and the first dc signal in the first common-mode signal of the target circuit, the method further includes: scanning a first duty ratio in a target chip, wherein an output stage of the target chip is connected with a target circuit; correcting a control word of a target circuit into a first control word through a first duty ratio in a target chip; before detecting the second peak signal and the second dc signal in the second common mode signal of the target circuit, the method further comprises: scanning a second duty cycle inside the target chip; and correcting the control word of the target circuit into a second control word through a second duty ratio in the target chip.
Optionally, modifying the control word of the target circuit into the first control word by the first duty cycle inside the target chip includes: adjusting the number of first field effect transistors in a working state in a target circuit to be a first number and adjusting the number of second field effect transistors in the working state to be a second number according to a first duty ratio in a target chip, wherein the first field effect transistors in the first number and the second field effect transistors in the second number enable control words to be first control words; modifying the control word of the target circuit to a second control word by a second duty cycle inside the target chip comprises: and adjusting the number of the first field effect transistors in the working state in the target circuit to be a third number and adjusting the number of the second field effect transistors in the working state to be a fourth number according to a second duty ratio in the target chip, wherein the first field effect transistors in the third number and the second field effect transistors in the fourth number enable the control words to be second control words.
Optionally, detecting the first peak signal and the first dc signal in the first common-mode signal of the target circuit includes: a first peak signal and a first average signal in a first common-mode signal of a target circuit are detected, wherein the first direct-current signal comprises a first average signal, and the first average signal is used for indicating an average value of the first common-mode signal.
Optionally, the target circuit comprises a circuit of a high speed transmitter.
In order to achieve the above object, according to another aspect of the present invention, there is also provided a signal processing apparatus. The device includes: the detection unit is used for detecting a peak signal and a direct current signal in the common mode signal in a target circuit, wherein the peak signal is used for indicating the peak value of the common mode signal, and the direct current signal is used for indicating the direct current component in the common mode signal; the processing unit is used for carrying out quantization processing on the peak value signal and the direct current signal to obtain a quantization result, wherein the difference value between a numerical value corresponding to the peak value signal and a numerical value corresponding to the direct current signal in the quantization result is used for representing the jitter degree of the common mode signal; and the determining unit is used for determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit under the condition that the quantization result meets the target condition.
In order to achieve the above object, according to another aspect of the present invention, there is also provided a storage medium. The storage medium includes a stored program, wherein the apparatus in which the storage medium is located is controlled to execute the signal processing method of the embodiment of the present invention when the program is executed.
To achieve the above object, according to another aspect of the present invention, there is also provided a processor. The processor is used for running a program, wherein the program executes the signal processing method of the embodiment of the invention.
According to the invention, in a target circuit, a peak signal and a direct current signal in a common mode signal are detected, wherein the peak signal is used for indicating the peak value of the common mode signal, and the direct current signal is used for indicating the direct current component in the common mode signal; quantizing the peak signal and the direct current signal to obtain a quantization result, wherein a difference value between a numerical value corresponding to the peak signal and a numerical value corresponding to the direct current signal in the quantization result is used for representing the jitter degree of the common mode signal; and under the condition that the quantization result meets the target condition, determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit. Because the optimal quantization result is selected by detecting the direct current signal and the peak value signal of the common mode signal and outputting the jittering amplitude of the common mode signal, the optimal output duty ratio is determined, the problem of low signal processing efficiency is solved, and the effect of improving the signal processing efficiency is further achieved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram of duty cycle misalignment according to a related art;
FIG. 2 is a schematic diagram of duty cycle misalignment according to another related art;
FIG. 3 is a schematic diagram of duty cycle misalignment according to another related art;
FIG. 4 is a flow chart of a method of signal processing according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a circuit for eliminating duty cycle mismatch according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another circuit for eliminating duty cycle imbalance according to an embodiment of the present invention;
FIG. 7 is a circuit schematic of a duty cycle process according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a relationship between a common mode signal, a DC signal and a peak signal according to an embodiment of the present invention; and
fig. 9 is a schematic diagram of a signal processing apparatus according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
The embodiment of the invention provides a signal processing method.
Fig. 4 is a flow chart of a signal processing method according to an embodiment of the present invention. As shown in fig. 4, the method comprises the steps of:
in step S402, in the target circuit, a peak signal and a dc signal in the common mode signal are detected.
In the technical solution provided in the above step S402, in the target circuit, a peak signal and a dc signal in the common mode signal are detected, where the peak signal is used to indicate a peak value of the common mode signal, and the dc signal is used to indicate a dc component in the common mode signal.
In this embodiment, the target circuit is a circuit whose duty ratio is to be corrected, and the common mode signal is also the common mode level. In the target circuit, a peak signal and a direct current signal in the common mode signal are detected, and two common mode detection circuits can be added in a scanning output stage, wherein one common mode detection circuit can be a peak detection circuit and is used for detecting the peak signal in the common mode signal, namely, detecting the maximum jitter amplitude of a common mode level, wherein the peak signal is used for indicating the peak value of the common mode signal; the other common mode detection circuit may be a dc detection circuit, and a dc signal of the common mode signal may be obtained through a capacitive filter, where the dc signal is used to indicate a dc component in the common mode signal, and may be an average value of the common mode signal.
Optionally, the common mode detection resistance of the common mode detection circuit of this embodiment is controlled by a switch, so that after calibration is completed, the common mode detection circuit is selectively turned off to save power consumption, and the common mode condition can also be detected by turning on for a long time.
And step S404, performing quantization processing on the peak value signal and the direct current signal to obtain a quantization result.
In the technical solution provided in the foregoing step S404 of the present application, a quantization process is performed on the peak signal and the dc signal to obtain a quantization result, where a difference between a value corresponding to the peak signal and a value corresponding to the dc signal in the quantization result is used to represent a jitter degree of the common mode signal.
After detecting the peak signal and the direct current signal in the common mode signal, carrying out quantization processing on the peak signal and the direct current signal to obtain a quantization result. Optionally, the voltage signals corresponding to the peak signal and the dc signal are sent to an Analog-to-Digital Converter (ADC), the magnitude of the voltage signal amplitude can be identified through the inside of the Digital chip and the corresponding amplitude is stored, so as to obtain a quantization result, and the difference between the value corresponding to the peak signal and the value corresponding to the dc signal in the quantization result is used to represent the jitter degree of the common mode signal, thereby detecting the amplitude of the output common mode level jitter. The larger the common mode signal jitter is, the larger the difference between the value corresponding to the peak signal and the value corresponding to the dc signal is; the smaller the common mode signal jitter, the smaller the difference between the value corresponding to the peak signal and the value corresponding to the dc signal.
And step S406, under the condition that the quantization result meets the target condition, determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit.
In the technical solution provided in the foregoing step S406 of the present application, when the quantization result meets the target condition, the duty ratio corresponding to the quantization result is determined as the target duty ratio of the target circuit.
After the peak signal and the direct current signal are subjected to quantization processing to obtain a quantization result, under the condition that the quantization result meets a target condition, determining a duty ratio corresponding to the quantization result as a target duty ratio of a target circuit. Alternatively, since the difference between the value corresponding to the peak signal and the value corresponding to the dc signal is smaller in the case where the common mode signal jitter is smaller, the duty ratio corresponding to the quantization result is determined as the target duty ratio of the target circuit, that is, the target duty ratio is the optimal output duty ratio, in the case where the difference between the value corresponding to the peak signal and the value corresponding to the dc signal in the quantization result is the smallest. The digital circuit can scan the control words of the duty ratio correction circuit in the chip, the digital circuit records and compares the output results of the ADC, the optimal duty ratio result is selected from the output results, and the configuration of the optimal duty ratio result is applied to the duty ratio correction circuit, so that the optimal duty ratio output effect is achieved.
It should be noted that the signal processing method of this embodiment does not need to monitor the output duty ratio in real time, and detection can be started before the normal operation of the chip, during the normal operation of the chip, or in the gap during the normal operation of the chip, so that the influence on the normal operation of the chip can be reduced as much as possible according to the requirements of the system.
The embodiment detects a peak signal and a direct current signal in a common mode signal in a target circuit, wherein the peak signal is used for indicating a peak value of the common mode signal, and the direct current signal is used for indicating a direct current component in the common mode signal; quantizing the peak signal and the direct current signal to obtain a quantization result, wherein a difference value between a numerical value corresponding to the peak signal and a numerical value corresponding to the direct current signal in the quantization result is used for representing the jitter degree of the common mode signal; and under the condition that the quantization result meets the target condition, determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit. Because the optimal quantization result is selected by detecting the direct current signal and the peak value signal of the common mode signal and outputting the jittering amplitude of the common mode signal, the optimal output duty ratio is determined, the problem of low signal processing efficiency is solved, and the effect of improving the signal processing efficiency is further achieved.
As an alternative implementation, the step S402 of detecting the peak signal and the dc signal in the common mode signal includes: detecting a first peak signal and a first direct current signal in a first common mode signal under a first control word, wherein the first control word is used for controlling the jitter degree of the first common mode signal, the peak signal comprises a first peak signal, the first peak signal is used for indicating a first peak value of the first common mode signal, the direct current signal comprises a first direct current signal, and the first direct current signal is used for indicating a first direct current component in the first common mode signal; step S404, performing quantization processing on the peak signal and the dc signal, and obtaining a quantization result includes: and quantizing the first peak signal and the first direct current signal to obtain a first quantization result, wherein the quantization result comprises a first quantization result.
In this embodiment, the control word may be used to indicate the jitter degree of the common mode signal, and the control word that minimizes the difference between the corresponding values of the peak signal and the dc signal indicates the jitter degree of the common mode signal is minimized. In this embodiment, the digital circuit scans the duty ratio inside the chip to correct the control word of the circuit, and the number of the P-Channel Metal Oxide Semiconductor field effect transistor (PMOS for short) and the N-Channel Metal Oxide Semiconductor field effect transistor (NMOS for short) in the circuit can be adjusted to make the control word of the correction circuit be the first control word. Under the first control word, outputting a first common mode signal, detecting a first peak signal and a first direct current signal in the first common mode signal, and detecting the first peak signal in the first common mode signal through a peak detection circuit added in a scan output stage, that is, detecting the maximum jitter amplitude of the first common mode signal, wherein the first peak signal is used for indicating the peak value of the first common mode signal; in the dc detection circuit, a first dc signal of the first common-mode signal is obtained through a capacitor filter, and the first dc signal is used to indicate a first dc component in the first common-mode signal, and may be an average value of the first common-mode signal.
After detecting a first peak signal and a first direct current signal in the first common mode signal, performing quantization processing on the first peak signal and the first direct current signal to obtain a first quantization result so as to judge whether the output common mode characteristic is optimal.
As an alternative implementation, step S402, detecting the peak signal and the dc signal in the common-mode signal further includes: detecting a second peak signal and a second direct current signal in a second common mode signal of the target circuit under a second control word, wherein the second control word is used for controlling the jitter degree of the second common mode signal, the peak signal comprises the second peak signal, the second peak signal is used for indicating a second peak value of the second common mode signal, the direct current signal comprises the second direct current signal, and the second direct current signal is used for indicating a second direct current component in the second common mode signal; step S404, performing quantization processing on the peak signal and the dc signal, and obtaining a quantization result includes: quantizing the second peak signal and the second direct current signal to obtain a second quantization result, wherein the quantization result comprises a second quantization result; step S406, determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit when the quantization result meets the target condition includes: and determining a target quantization result meeting the target condition from the first quantization result and the second quantization result, and determining a duty ratio corresponding to the target quantization result as a target duty ratio of the target circuit, wherein the difference between a value corresponding to the peak signal and a value corresponding to the direct current signal in the target quantization result is the smallest.
In the embodiment, the control word of the circuit is corrected by scanning the duty ratio in the chip through the digital circuit, and the control word of the correction circuit can be taken as the second control word by adjusting the number of the PMOS field effect transistors and the NMOS field effect transistors in the circuit. Under the second control word, outputting a second common mode signal, detecting a second peak signal and a second direct current signal in the second common mode signal, and detecting the second peak signal in the second common mode signal through a peak detection circuit added in the scanout stage, that is, detecting the maximum jitter amplitude of the second common mode signal, wherein the second peak signal is used for indicating the peak value of the second common mode signal; in the dc detection circuit, a second dc signal of the second common mode signal is obtained through a capacitive filter, and the second dc signal is used to indicate a second dc component in the second common mode signal, and may be an average value of the second common mode signal.
After detecting a second peak signal and a second direct current signal in the second common mode signal, performing quantization processing on the second peak signal and the second direct current signal to obtain a second quantization result so as to judge whether the output common mode characteristic is optimal.
Optionally, a target quantization result meeting a target condition is determined from the first quantization result and the second quantization result, that is, a target quantization result with a minimum difference between a value corresponding to a peak signal and a value corresponding to the dc signal is determined from the first quantization result and the second quantization result, an output common mode characteristic of a common mode signal corresponding to the minimum difference between the value corresponding to the peak signal and the value corresponding to the dc signal is optimal, a duty ratio corresponding to the target quantization result is determined as a target duty ratio of the target circuit, that is, an optimal duty ratio of the target circuit, and the configuration is applied to the duty ratio correction circuit, so as to achieve an optimal output duty ratio effect.
As an alternative embodiment, detecting the first peak signal and the first dc signal in the first common-mode signal of the target circuit includes: detecting a first peak signal in the first common-mode signal through a first detection circuit, and detecting a first direct current signal in the first common-mode signal through a second detection circuit, wherein the second detection circuit is different from the first detection circuit; detecting a second peak signal and a second dc signal in a second common mode signal of a target circuit includes: a second peak signal in the second common mode signal is detected by the first detection circuit, and a second direct current signal in the second common mode signal is detected by the second detection circuit.
In this embodiment, the first detection circuit may be a common mode detection circuit, that is, a peak detection circuit, which is connected to the first common mode signal. When detecting a first peak signal and a first direct current signal in the first common mode signal, detecting the first peak signal in the first common mode signal through a first detection circuit, that is, detecting the maximum jitter amplitude of the first common mode signal; the second detection circuit of this embodiment is also a common mode detection circuit, which may be a dc detection circuit, and the dc detection circuit may access the first common mode signal through a capacitive filter to obtain a dc signal of the first common mode signal.
The embodiment may further detect a second peak signal in the second common-mode signal through the first detection circuit, that is, detect a maximum jitter amplitude of the second common-mode signal; the second detection circuit of this embodiment may further access the second common mode signal through the capacitive filter to obtain a dc signal of the second common mode signal.
The detection resistors of the first detection circuit and the second detection circuit of the embodiment can be controlled by the switch, the detection circuit can be selectively turned off after the calibration is completed so as to save power consumption, and the detection circuit can be turned on for a long time so as to detect a common mode condition.
As an alternative implementation, performing quantization processing on the first peak signal and the first dc signal to obtain a first quantization result includes: inputting the first peak signal and the first direct current signal to an analog-to-digital conversion circuit to obtain a first quantization result; performing quantization processing on the second peak signal and the second direct current signal to obtain a second quantization result, including: and inputting the second peak signal and the second direct current signal to the analog-to-digital conversion circuit to obtain a second quantization result.
This embodiment may be implemented by the analog-to-digital conversion circuit ADC when the first peak signal and the first dc signal are quantized to obtain the first quantization result. Inputting a first peak signal and a first direct current signal in a first common-mode signal to an analog-to-digital conversion circuit, inputting a voltage signal corresponding to the first peak signal and the first direct current signal to the analog-to-digital conversion circuit, and identifying the amplitude of the voltage signal and storing the corresponding amplitude inside a digital chip; when the second peak signal and the second direct current signal are quantized to obtain a second quantization result, the second peak signal and the second direct current signal in the second common mode signal may be input to the analog-to-digital conversion circuit, a voltage signal corresponding to the second peak signal and the second direct current signal may be input to the analog-to-digital conversion circuit, and the magnitude of the voltage signal amplitude may be identified and stored in the digital chip.
As an optional implementation, before detecting the first peak signal and the first dc signal in the first common-mode signal of the target circuit, the method further includes: scanning a first duty ratio in a target chip, wherein an output stage of the target chip is connected with a target circuit; correcting a control word of a target circuit into a first control word through a first duty ratio in a target chip; before detecting the second peak signal and the second dc signal in the second common mode signal of the target circuit, the method further comprises: scanning a second duty cycle inside the target chip; and correcting the control word of the target circuit into a second control word through a second duty ratio in the target chip.
In this embodiment, the control word of the duty cycle correction circuit inside the chip is scanned by the digital circuit. An output stage of a target circuit may be connected to a target chip by a digital circuit scanning a first duty cycle inside the target chip before detecting a first peak signal and a first direct current signal in a first common mode signal of the target circuit. After scanning a first duty ratio in a target chip, correcting a control word of a target circuit into a first control word through the first duty ratio in the target chip, wherein the first control word is used for controlling the jitter amplitude of a first common mode signal; scanning, by the digital circuit, a second duty cycle inside the target chip before detecting a second peak signal and a second direct current signal in a second common mode signal of the target circuit. And after scanning a second duty ratio in the target chip, correcting the control word of the target circuit into a second control word through the second duty ratio in the target chip, wherein the second control word is used for controlling the jitter amplitude of the second common-mode signal.
Alternatively, when the digital circuit scans the control word of the duty ratio correction circuit inside the chip, the rising and falling driving forces of all the output stages of the chip can be fixedly configured through simulation or the result of a few chip tests, the switching strength of the output stages can be adjusted to adjust the rising and falling edge time, or the duty ratio of the output of the previous stage is adjusted, and the number of the PMOS or NMOS is adjusted to introduce unbalanced duty ratio, so as to offset the duty ratio imbalance of the output.
As an alternative implementation, modifying the control word of the target circuit into the first control word by the first duty cycle inside the target chip includes: adjusting the number of first field effect transistors in a working state in a target circuit to be a first number and adjusting the number of second field effect transistors in the working state to be a second number according to a first duty ratio in a target chip, wherein the first field effect transistors in the first number and the second field effect transistors in the second number enable control words to be first control words; modifying the control word of the target circuit to a second control word by a second duty cycle inside the target chip comprises: and adjusting the number of the first field effect transistors in the working state in the target circuit to be a third number and adjusting the number of the second field effect transistors in the working state to be a fourth number according to a second duty ratio in the target chip, wherein the first field effect transistors in the third number and the second field effect transistors in the fourth number enable the control words to be second control words.
In this embodiment, the target circuit includes a first field effect transistor, which may be a PMOS field effect transistor, and a second field effect transistor, which may be an NMOS field effect transistor. When the control word of the target circuit is corrected to be the first control word through the first duty ratio in the target chip, the number of first field effect transistors in the working state in the target circuit can be adjusted to be the first number through the first duty ratio in the target chip, and the number of second field effect transistors in the working state is adjusted to be the second number, so that the control word of the target circuit is corrected to be the first control word; when the control word of the target circuit is corrected to be the second control word through the second duty ratio in the target chip, the number of the first field effect transistors in the working state in the target circuit can be adjusted to be the third number through the second duty ratio in the target chip, and the number of the second field effect transistors in the working state can be adjusted to be the fourth number, so that the control word of the target circuit is corrected to be the fourth control word.
Optionally, in this embodiment, the control word of the circuit is modified by the above method, the peak signal and the dc signal in the common mode signal are detected under different control words, the peak signal and the dc signal are quantized to obtain quantization results, the obtained quantization results corresponding to different control words are compared, and an optimal quantization result is selected from the quantization results, that is, the quantization result with the smallest difference between the value corresponding to the peak signal and the value corresponding to the dc signal in the quantization results is selected, and the duty ratio configuration corresponding to the optimal quantization result is applied to the duty ratio modification circuit, so that the optimal output duty ratio effect is achieved, and the signal processing efficiency is improved.
As an alternative embodiment, detecting the first peak signal and the first dc signal in the first common-mode signal of the target circuit includes: a first peak signal and a first average signal in a first common-mode signal of a target circuit are detected, wherein the first direct-current signal comprises a first average signal, and the first average signal is used for indicating an average value of the first common-mode signal.
In this embodiment, the dc signal may be an average value of the common mode signal, and thus the first dc signal may be an average value of the first common mode signal, and the second dc signal may be an average value of the second common mode signal. In detecting the first peak signal and the first dc signal in the first common-mode signal of the target circuit, the first peak signal and a first average signal in the first common-mode signal of the target circuit may be detected, the first average signal indicating an average value of the first common-mode signal.
Optionally, when detecting the second peak signal and the second dc signal in the second common mode signal of the target circuit, a second peak signal and a second average signal in the second common mode signal of the target circuit may be detected, and the second average signal is used to indicate an average value of the second common mode signal, so as to implement a method of comparing the output common mode peak and average values to automatically adjust the duty cycle characteristic of the circuit.
As an alternative embodiment, the target circuit comprises the circuitry of a high speed transmitter.
In this embodiment, the target circuit may be a circuit of a high-speed transmitter, and may be a high-speed interconnect circuit. Optionally, the rise-fall driving capability or the preceding-stage duty ratio of the output stage is scanned, and the amplitude of the jitter of the output common-mode electrical signal is detected to determine whether the output common-mode characteristic is optimal, so as to achieve the optimal output duty ratio, and improve the signal quality of the high-speed transmitter.
By adopting the duty ratio detection correction circuit provided by the embodiment of the invention, the real-time detection of the output duty ratio performance can be realized. Under different chip process deviations, correction can be performed according to different duty ratio characteristics so as to achieve the optimal duty ratio effect. The scheme provided by the embodiment can be started in a short time or a long time, and almost has no adverse effect when being added into the original circuit design.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
Example 2
The technical solution of the present invention is illustrated below with reference to preferred embodiments.
In this embodiment, in order to eliminate the phenomenon of duty ratio offset in the circuit, the rising-falling driving force of all the chip output stages can be fixedly configured by simulation or the result of a few chip tests.
Fig. 5 is a schematic diagram of a circuit for eliminating duty cycle mismatch according to an embodiment of the present invention. As shown in fig. 5, the switching strength of the output stage is adjusted to adjust the time of the rising and falling edges, or to adjust the duty ratio of the output of the previous stage, wherein the PMOS fet P1 … … Pn and the NMOS fet N1 … … Nn are included, where N may be an integer greater than 1 and is used to indicate the number of corresponding fets, Pn is used to indicate the nth PMOS fet, and Nn is used to indicate the nth NMOS fet.
Fig. 6 is a schematic diagram of another circuit for eliminating duty cycle imbalance according to an embodiment of the present invention. As shown in fig. 6, the number of PMOS or NMOS is adjusted to introduce unbalanced duty ratio, so as to offset the duty ratio imbalance of the output.
Fig. 7 is a circuit schematic of a duty cycle process according to an embodiment of the present invention. As shown in fig. 7, this embodiment adds two detection points, one to detect the average value of the common mode level and one to detect the peak value of the common mode level. Two common mode detection circuits are added in an output stage, the common mode detection resistance of the common mode detection circuit is controlled by a switch, the detection circuit can be selectively closed after calibration is completed so as to save power consumption, and the common mode condition can be conducted and detected for a long time. The common-mode signal on the left side is connected into a peak value detection circuit to detect the peak value signal of the common-mode signal, namely, the maximum jitter amplitude of the common-mode level is detected, and the common-mode signal on the right side obtains the direct current component of the common-mode signal through a capacitance filter. The peak signal and the dc component are then quantized by the ADC.
Fig. 8 is a diagram illustrating a relationship between a common mode signal, a dc signal, and a peak signal according to an embodiment of the invention. As shown in fig. 8, the larger the common mode signal jitter, the larger the difference between the corresponding values of the dc signal and the peak signal. The voltage signals corresponding to the direct current signal and the peak signal can be sent to an analog-to-digital conversion circuit, the signal amplitude can be identified through the inside of the digital chip, and the corresponding amplitude is stored.
Through the method, according to the adjustment relationship, the control word of the duty ratio correction circuit designed in the chip is scanned through the digital circuit, the method comprises but is not limited to the circuit structure shown in fig. 5 and fig. 6, the output result of the ADC is recorded and compared through the digital circuit, the control word with the minimum difference value indicates that the output common mode jitter is minimum, and then the optimal result is selected from the control word, and the configuration of the control word is applied to the duty ratio correction circuit, so that the optimal output duty ratio effect is achieved, the purpose of automatically adjusting the duty ratio characteristic of the circuit through the method of comparing the output common mode peak value and the average value is achieved, and the duty ratio processing efficiency is improved.
It should be noted that in this embodiment, the output duty ratio does not need to be monitored in real time, detection can be started before the normal operation of the chip, during the normal operation of the chip, or in a gap during the normal operation of the chip, and the influence on the normal operation can be reduced as much as possible according to the system requirements.
The duty ratio detection and correction circuit provided by the embodiment of the invention can achieve the purpose of detecting the performance of the output duty ratio in real time, and can correct different duty ratio characteristics under different chip process deviations so as to achieve the optimal duty ratio effect. The scheme provided by the embodiment can be started for a short time or a long time, so that the embodiment is added into the original circuit design and hardly has any adverse effect.
Example 3
The embodiment of the invention also provides a signal processing device. It should be noted that the signal processing apparatus of this embodiment may be used to execute the signal processing method of the embodiment of the present invention.
Fig. 9 is a schematic diagram of a signal processing apparatus according to an embodiment of the present invention. As shown in fig. 9, the apparatus may include: a detection unit 10, a processing unit 20 and a determination unit 30.
The detection unit 10 is configured to detect a peak signal and a dc signal in the common mode signal in the target circuit, where the peak signal is used to indicate a peak value of the common mode signal, and the dc signal is used to indicate a dc component in the common mode signal.
And the processing unit 20 is configured to perform quantization processing on the peak signal and the dc signal to obtain a quantization result, where a difference between a value corresponding to the peak signal and a value corresponding to the dc signal in the quantization result is used to represent a jitter degree of the common mode signal.
And a determining unit 30, configured to determine, when the quantization result meets the target condition, a duty ratio corresponding to the quantization result as a target duty ratio of the target circuit.
In this embodiment, a peak signal and a dc signal in a common mode signal are detected in a target circuit by a detection unit 10, where the peak signal is used to indicate a peak value of the common mode signal, and the dc signal is used to indicate a dc component in the common mode signal, and the peak signal and the dc signal are quantized by a processing unit 20 to obtain a quantization result, where a difference between a value corresponding to the peak signal and a value corresponding to the dc signal in the quantization result is used to represent a jitter degree of the common mode signal, and a duty ratio corresponding to the quantization result is determined as a target duty ratio of the target circuit by a determination unit 30 when the quantization result meets a target condition. Because the optimal quantization result is selected by detecting the direct current signal and the peak value signal of the common mode signal and outputting the jittering amplitude of the common mode signal, the optimal output duty ratio is determined, the problem of low signal processing efficiency is solved, and the effect of improving the signal processing efficiency is further achieved.
Example 4
The embodiment of the invention also provides a storage medium. The storage medium includes a stored program, wherein the apparatus in which the storage medium is located is controlled to execute the signal processing method of the embodiment of the present invention when the program is executed.
Example 5
The embodiment of the invention also provides a processor. The processor is used for running a program, wherein the program executes the signal processing method of the embodiment of the invention.
It will be apparent to those skilled in the art that the modules or steps of the invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and they may alternatively be implemented by program code that is receivable by the computing devices, and that may be stored in a memory device for execution by the computing devices, or that may be separately fabricated into individual integrated circuit modules, or that may be fabricated from multiple modules or steps within them into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (12)
1. A signal processing method, comprising:
in a target circuit, detecting a peak signal and a direct current signal in a common mode signal, wherein the peak signal is used for indicating a peak value of the common mode signal, and the direct current signal is used for indicating a direct current component in the common mode signal;
quantizing the peak signal and the direct current signal to obtain a quantization result, wherein a difference value between a value corresponding to the peak signal and a value corresponding to the direct current signal in the quantization result is used for representing the jitter degree of the common mode signal;
and under the condition that the quantization result meets a target condition, determining the duty ratio inside a target chip corresponding to the quantization result as the target duty ratio of the target circuit, wherein the duty ratio inside the target chip is used for correcting a control word of the target circuit, and the control word is used for controlling the jitter degree of the common-mode signal.
2. The method of claim 1,
detecting a peak signal and a dc signal in the common mode signal comprises: detecting a first peak signal and a first direct current signal in a first common mode signal under a first control word, wherein the first control word is used for controlling the jitter degree of the first common mode signal, the peak signal comprises the first peak signal, the first peak signal is used for indicating a first peak value of the first common mode signal, the direct current signal comprises the first direct current signal, and the first direct current signal is used for indicating a first direct current component in the first common mode signal;
quantizing the peak signal and the dc signal, and obtaining the quantization result includes: and quantizing the first peak signal and the first direct current signal to obtain a first quantization result, wherein the quantization result comprises the first quantization result.
3. The method of claim 2,
detecting the peak signal and the dc signal in the common mode signal further comprises: detecting a second peak signal and a second direct current signal in a second common mode signal of the target circuit under a second control word, wherein the second control word is used for controlling the jitter degree of the second common mode signal, the peak signal comprises the second peak signal, the second peak signal is used for indicating a second peak value of the second common mode signal, the direct current signal comprises the second direct current signal, and the second direct current signal is used for indicating a second direct current component in the second common mode signal;
quantizing the peak signal and the dc signal, and obtaining the quantization result includes: quantizing the second peak signal and the second direct current signal to obtain a second quantization result, wherein the quantization result comprises the second quantization result;
determining the duty ratio corresponding to the quantization result as the target duty ratio of the target circuit when the quantization result meets the target condition comprises: and determining a target quantization result meeting the target condition from the first quantization result and the second quantization result, and determining a duty ratio corresponding to the target quantization result as a target duty ratio of the target circuit, wherein a difference between a value corresponding to the peak signal and a value corresponding to the dc signal in the target quantization result is the smallest.
4. The method of claim 3,
detecting the first peak signal and the first dc signal in a first common-mode signal of the target circuit comprises: detecting the first peak signal in the first common-mode signal by a first detection circuit, and detecting the first direct-current signal in the first common-mode signal by a second detection circuit, wherein the second detection circuit is different from the first detection circuit;
detecting the second peak signal and the second DC signal in a second common mode signal of the target circuit comprises: detecting, by the first detection circuit, the second peak signal in the second common mode signal, and detecting, by the second detection circuit, the second dc signal in the second common mode signal.
5. The method of claim 4,
performing quantization processing on the first peak signal and the first dc signal to obtain the first quantization result, including: inputting the first peak signal and the first direct current signal to an analog-to-digital conversion circuit to obtain the first quantization result;
quantizing the second peak signal and the second dc signal to obtain the second quantization result, including: and inputting the second peak signal and the second direct current signal to an analog-to-digital conversion circuit to obtain the second quantization result.
6. The method of claim 3,
prior to detecting the first peak signal and the first dc signal in the first common-mode signal of the target circuit, the method further includes: scanning a first duty ratio inside the target chip, wherein an output stage of the target chip is connected with the target circuit; correcting a control word of the target circuit into the first control word through the first duty ratio in the target chip;
prior to detecting the second peak signal and the second dc signal in the second common mode signal of the target circuit, the method further comprises: scanning a second duty cycle inside the target chip; and correcting the control word of the target circuit into the second control word through the second duty ratio in the target chip.
7. The method of claim 6,
modifying the control word of the target circuit to the first control word by the first duty cycle inside the target chip comprises: adjusting the number of first field effect transistors in a working state in the target circuit to a first number and adjusting the number of second field effect transistors in the working state to a second number according to the first duty ratio in the target chip, wherein the first field effect transistors in the first number and the second field effect transistors in the second number enable the control word to be the first control word;
modifying the control word of the target circuit to the second control word by the second duty cycle inside the target chip comprises: and adjusting the number of the first field effect transistors in the working state in the target circuit to be a third number and adjusting the number of the second field effect transistors in the working state to be a fourth number according to the second duty ratio in the target chip, wherein the first field effect transistors in the third number and the second field effect transistors in the fourth number enable the control word to be the second control word.
8. The method according to any one of claims 2 to 7,
detecting the first peak signal and the first direct current signal in the first common-mode signal of the target circuit comprises: detecting the first peak signal and a first average signal in the first common-mode signal of the target circuit, wherein the first direct-current signal includes the first average signal, and the first average signal is used for indicating an average value of the first common-mode signal.
9. The method of any of claims 1-7, wherein the target circuit comprises a circuit of a high speed transmitter.
10. A signal processing apparatus, characterized by comprising:
the detection unit is used for detecting a peak signal and a direct current signal in a common mode signal in a target circuit, wherein the peak signal is used for indicating the peak value of the common mode signal, and the direct current signal is used for indicating the direct current component in the common mode signal;
the processing unit is used for performing quantization processing on the peak signal and the direct current signal to obtain a quantization result, wherein a difference value between a numerical value corresponding to the peak signal and a numerical value corresponding to the direct current signal in the quantization result is used for representing the jitter degree of the common mode signal;
and the determining unit is used for determining the duty ratio inside a target chip corresponding to the quantization result as the target duty ratio of the target circuit under the condition that the quantization result meets a target condition, wherein the duty ratio inside the target chip is used for correcting a control word of the target circuit, and the control word is used for controlling the jitter degree of the common-mode signal.
11. A storage medium, characterized in that the storage medium includes a stored program, wherein, when the program is executed, a device in which the storage medium is located is controlled to execute the signal processing method according to any one of claims 1 to 9.
12. A processor, characterized in that the processor is configured to run a program, wherein the program is configured to execute the signal processing method according to any one of claims 1 to 9 when running.
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