CN108021394B - PCM signal acquisition method and device - Google Patents
PCM signal acquisition method and device Download PDFInfo
- Publication number
- CN108021394B CN108021394B CN201711381503.8A CN201711381503A CN108021394B CN 108021394 B CN108021394 B CN 108021394B CN 201711381503 A CN201711381503 A CN 201711381503A CN 108021394 B CN108021394 B CN 108021394B
- Authority
- CN
- China
- Prior art keywords
- pcm
- module
- acquisition
- computer
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000000630 rising effect Effects 0.000 claims description 26
- 230000005540 biological transmission Effects 0.000 claims description 12
- 101100328519 Caenorhabditis elegans cnt-2 gene Proteins 0.000 description 9
- 238000004590 computer program Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 101100328518 Caenorhabditis elegans cnt-1 gene Proteins 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/16—Sound input; Sound output
- G06F3/162—Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Health & Medical Sciences (AREA)
- Audiology, Speech & Language Pathology (AREA)
- General Health & Medical Sciences (AREA)
- Human Computer Interaction (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
The invention is applicable to the technical field of digital audio acquisition, and provides a PCM signal acquisition device and method. The method comprises the following steps: the receiving module receives a PCM signal acquisition instruction sent by a computer; the receiving module converts the received PCM signal acquisition instruction and sends the converted PCM signal acquisition instruction to the acquisition module; the acquisition module acquires the PCM data according to the received instruction and stores the acquired PCM data into the storage module; the transmitting module transmits the PCM data in the storage module to the computer, and the receiving module, the collecting module and the transmitting module are integrated on the programmable logic device, so that parallel operation of each module is realized, the real-time performance of PCM signal collection is high, the collecting module can collect multiple paths of PCM data at the same time, and the hardware cost is saved.
Description
Technical Field
The invention belongs to the technical field of digital audio acquisition, and particularly relates to a PCM signal acquisition method and device.
Background
In telecommunication devices, the signals used for dialing, command and voice compression are all in the form of pulse code modulation (Pulse Code Modulation, PCM), and the grab analysis of each time slot signal in the PCM code stream is an essential step in debugging the telecommunication device.
The existing PCM data acquisition modes mainly comprise two modes, one is directly tested by using an oscilloscope, and the other is analyzed on a computer after a signal is captured by an acquisition card adopting a micro control unit (Microcontroller Unit, MCU) scheme. The inventor finds that in the process of realizing the invention, the two PCM data acquisition modes have certain defects: when the oscilloscope is used for testing the PCM signals, multiple paths of PCM data cannot be collected at the same time due to the fact that the number of the probes is limited; when the acquisition card of the MCU scheme is adopted to acquire the PCM data, the real-time performance of the system is limited by the speed and the bit width of a target signal, and when multiple paths of PCM data are required to be acquired simultaneously, multiple MCUs or processor chips with higher performance are required to be used, so that the hardware cost is increased.
Disclosure of Invention
In view of this, the embodiment of the invention provides a PCM signal acquisition device and method, so as to solve the problem of too high cost caused by a plurality of MCUs when an acquisition card adopting an MCU scheme is used for acquiring multi-path PCM data in the prior art.
A first aspect of an embodiment of the present invention provides a PCM signal acquisition apparatus, including a receiving module, an acquisition module, a storage module, a multiplexing module, and a transmitting module;
the receiving module is used for receiving the PCM signal acquisition instruction sent by the computer and converting the received acquisition instruction;
the acquisition module is used for receiving the PCM signal acquisition instruction converted by the receiving module and acquiring PCM data according to the received instruction, and comprises at least one data acquisition channel;
the storage module is used for storing the PCM data acquired by the acquisition module;
The multiplexing module is used for multiplexing the data stored by the storage module onto an output channel;
the sending module is used for sending the PCM data in the storage module to a computer;
the receiving module, the collecting module, the storage module, the multiplexing module and the sending module are arranged on the programmable logic device.
A second aspect of an embodiment of the present invention provides a PCM signal acquisition method, including:
the receiving module receives a PCM signal acquisition instruction sent by a computer;
the receiving module converts the received PCM signal acquisition instruction and sends the converted PCM signal acquisition instruction to the acquisition module; the acquisition module comprises at least one acquisition channel;
The acquisition module acquires the PCM data according to the received instruction and stores the acquired PCM data into the storage module;
The transmitting module transmits the PCM data in the storage module to a computer.
Optionally, the receiving module receives a PCM signal acquisition instruction sent by a computer, and specifically includes:
the receiving module detects whether the computer gives an acquisition instruction;
when the computer issues the acquisition instruction, the receiving module receives the PCM signal acquisition instruction sent by the computer.
Optionally, the receiving module detects whether the computer issues the acquisition instruction, and specifically includes: the receiving module detects the level of UartIn pins, and when the data collected by UartIn pins are changed from high level to low level, the computer sends out a collection instruction.
Optionally, the receiving module converts the received PCM signal acquisition instruction and sends the converted PCM signal acquisition instruction to the acquisition module, specifically:
The receiving module converts the received PCM signal acquisition instruction to obtain target PCM channel information and target time slot information, and sends the target PCM channel information and the target time slot information to the acquisition module.
Optionally, the collecting module collects PCM data according to the received instruction, and stores the collected PCM data in the storage module, which specifically includes:
when the rising edge of the core clock signal of the PCM bus is detected to come and the frame synchronization signal is at a high level, acquiring the PCM signal according to the target PCM channel information and the target time slot information;
Controlling a target acquisition channel of the acquisition module to acquire PCM data according to the target PCM channel information;
Setting a first counter for counting time slots in a target acquisition channel and a second counter for counting data bits in the target time slots, outputting the acquired PCM data to the storage module when the first counter and the second counter reach preset values, and positioning acquisition flag bits.
Optionally, before detecting that the rising edge of the core clock signal of the PCM bus arrives, the collecting module collects PCM data according to the received instruction, and stores the collected PCM data in the storage module, and further includes:
And initializing the target time slot information, the first counter, the second counter and the acquisition zone bit.
Optionally, the sending module sends the PCM data in the storage module to a computer, specifically including:
when the sending module receives the rising edge of the Latch mark signal and the rising edge of the sending clock signal comes, the data stored in the storage module is sent to a computer;
and setting a third counter for counting the clock width of the collected PCM data, and finishing the transmission of the collected PCM data when the third counter reaches a preset value.
Optionally, before the data stored in the storage module is sent to the computer, the method further includes: the sending module sends a start bit to the computer;
After the data stored in the storage module is sent to the computer, the method further comprises: the sending module sends a stop bit to the computer.
Optionally, after the sending module sends a stop bit 1 to the computer, the sending module further includes: the transmitting module transmits a plurality of idle bits to the computer.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: according to the embodiment of the invention, the receiving module receives the PCM signal acquisition instruction sent by the computer, converts the PCM signal acquisition instruction, transmits the converted PCM signal acquisition instruction to the acquisition module, acquires PCM data according to the received instruction, transmits the acquired data to the computer through the sending module, and enables the receiving module, the acquisition module and the sending module to independently operate by utilizing the parallel operation characteristic of the programmable logic device by arranging the modules on the programmable logic device, so that the real-time performance of PCM signal acquisition is enhanced, and simultaneously enables the acquisition module to simultaneously acquire multiple paths of PCM data by utilizing the parallel operation characteristic of the programmable logic device, thereby realizing that acquisition of multiple paths of PCM data can be completed by adopting a single chip and saving hardware cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic system structure of a PCM signal acquisition device according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an implementation flow of a PCM signal acquisition method according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for receiving a PCM signal acquisition command by a receiving module according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating an exemplary method for a collection module to collect PCM data according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for a transmitting module to transmit collected PCM data according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Example 1
Referring to fig. 1, a system architecture diagram of a PCM signal acquisition device is shown, comprising a receiving module 101, an acquisition module 102, a storage module 103, a multiplexing module 104 and a transmitting module 105.
The receiving module 101 is configured to receive a PCM signal acquisition instruction sent by the computer 106, and convert the received acquisition instruction; the acquisition module 102 is configured to receive the PCM signal acquisition instruction converted by the receiving module 101, and acquire PCM data according to the received instruction, where the acquisition module 102 includes at least one data acquisition channel, such as an acquisition channel 1, an acquisition channel 2, an acquisition channel 3, and so on, as shown in the figure; a storage module 103, configured to store PCM data acquired by the acquisition module 102; a multiplexing module 104, configured to multiplex the data stored in the storage module onto an output channel; a transmitting module 105 for transmitting the PCM data in the storage module 103 to a computer 106; the above-described receiving module 101, acquisition module 102, storage module 103, multiplexing module 104, and transmitting module 105 are provided on a programmable logic device (Programmable Logic Device, PLD).
For example, the PLD may employ a LCMX C-3TN144C model IC chip, but is not limited to this chip, and any general purpose input output (General Purpose Input Output, GPIO) port of this chip may define its functionality according to the needs of the user. The chip of PLD has the characteristics of high speed and parallel operation, so that the interfaces of multiple PCM acquisition channels can be arbitrarily expanded under the condition of sufficient GPIO port resources, thereby realizing multiple data acquisition.
The PCM signal acquisition device receives a PCM signal acquisition instruction sent by a computer through the receiving module, acquires PCM data through the acquisition module, stores the data acquired by the acquisition module through the storage module, multiplexes the data stored by the storage module onto an output channel through the multiplexing module, sends the PCM data in the storage module to the computer through the sending module, and integrates all the modules onto the PLD through the sending module, so that the characteristics of parallelism of the PLD are utilized, all the modules can run in parallel, the instantaneity of PCM signal acquisition is enhanced, and the effect of simultaneously acquiring multiple paths of PCM data by adopting one chip is achieved, so that the hardware cost is saved.
Example two
Corresponding to the PCM signal acquisition device described above, the present embodiment provides a PCM signal acquisition method, see fig. 2, as follows:
step S101, a receiving module receives a PCM signal acquisition instruction sent by a computer.
The pulse code signal acquisition device starts working only when receiving an instruction issued by the upper computer. Specifically, the upper computer sends a PCM signal acquisition instruction to a receiving module of the pulse code signal acquisition device.
Optionally, the process of receiving the PCM signal acquisition instruction sent by the computer by the receiving module specifically includes: the receiving module detects whether the computer gives an acquisition instruction. Here, the change of the pin level is passed when detecting whether the computer issues the instruction, wherein the pin UartIn for detecting whether the computer issues the instruction is provided on the receiving module, and when the data collected by the pin is changed from the high level to the low level, it indicates that the computer issues the collection instruction. At this time, the receiving module starts to receive the data sent by the computer.
When the computer issues the acquisition instruction, the receiving module receives the PCM signal acquisition instruction sent by the computer.
It will be readily appreciated that in order to avoid jitter in the collected data, a counter is provided for sampling from the middle of each bit of data sent by the computer, and when the received clock signal is a rising edge, the counter is incremented by 1, when the number of counters is 4, the data sent by the computer is sampled via pin UartIn, and when the number of counters is 63, the next received clock signal is about to arrive, indicating that the collection of 8 bits of data is completed. Meanwhile, a receiving flag bit is set, and the multiplexing module is informed of the completion of data acquisition by setting the receiving flag bit.
Specifically, referring to fig. 3, a flowchart of a method for receiving a PCM signal acquisition instruction by a receiving module is shown, which is described in detail below:
in step S201, the counter Rstate is initialized.
Step S202, judging whether the rising edge of RCLK arrives, executing step S203 and step S205 when the rising edge of RCLK arrives, otherwise executing step S202.
Step S203, determining UartIn whether the high level is changed to the low level, executing step S204 when UartIn is changed from the high level to the low level, otherwise executing step S202.
In step S204, the counter Rstate is enabled, and its initial value is increased by 1, and the reception flag bit is cleared.
In step S205, the counter Rstate is incremented by 1.
Step S206, determining whether the counter Rstate is equal to 4, executing step S207 when the counter Rstate is equal to 4, otherwise executing step S205.
In step S207, uartIn is placed in the lowest order bit of the output buffer.
Step S208, it is determined whether the counter Rstate is equal to 63, and when the counter Rstate is equal to 63, step S209 is performed, otherwise step S205 is performed.
Step S209, outputting the collected 8-bit data, and positioning and receiving the flag bit.
It will be readily appreciated that the value of the counter in the above process corresponds to the value that the counter needs to reach when 8 bits of data are collected, but is not limited to collecting 8 bits of data.
Step S102, the receiving module converts the received PCM signal acquisition instruction and sends the converted PCM signal acquisition instruction to the acquisition module; the acquisition module includes at least one acquisition channel.
Optionally, the receiving module converts the received PCM signal acquisition instruction to obtain target PCM channel information and target time slot information, and sends the target PCM channel information and the target time slot information to the acquisition module.
When the acquisition module acquires PCM data, the acquisition module needs to acquire target PCM channel information and target time slot information of the data, and accurately positions the data to be acquired according to the target PCM channel information and the target time slot information. The target PCM channel information and the target time slot information are obtained by converting the received PCM signal acquisition instruction by the receiving module. The receiving module sends the obtained target PCM channel information and target time slot information to the multiplexing module, and the multiplexing module transmits the received information to the acquisition module, so that the acquisition module acquires data required by a computer.
Step S103, the acquisition module acquires the PCM data according to the received instruction and stores the acquired PCM data in the storage module.
Optionally, the process when the acquisition module acquires PCM data according to the received instruction includes the following steps.
When the rising edge of the core clock signal of the PCM bus is detected to come and the frame synchronization signal is at a high level, the PCM signal is acquired according to the target PCM channel information and the target time slot information. The acquisition module needs to be at the time when the core clock signal of the PCM bus is at the rising edge before the PCM data is acquired. Meanwhile, the frame synchronization signal needs to be at a high level to collect the data of the PCM bus.
And when the clock signal and the frame synchronization signal are in a preset state, controlling a target acquisition channel of the acquisition module to acquire PCM data according to the target PCM channel information. Wherein the acquisition module comprises at least one data acquisition channel, wherein different numbers of data acquisition channels can be set according to the requirements of acquiring PCM data. And starting a specific acquisition channel to acquire the data of the PCM bus according to the target PCM channel information acquired by the acquisition module.
Setting a first counter for counting time slots in a target acquisition channel and a second counter for counting data bits in the target time slots, outputting the acquired PCM data to the storage module when the first counter and the second counter reach preset values, and positioning acquisition flag bits.
When a specific acquisition channel acquires data from the PCM bus, a target time slot in the target PCM channel needs to be found, specifically, the time slot in the target PCM channel is counted by setting a first counter until the value counted by the first counter is equal to the value of the target time slot, then the data bit in the target time slot is counted by setting a second counter, and when the counted value of the second counter is equal to a preset value, the acquired data is the data to be acquired by a computer. After the acquired PCM data is obtained, the acquired data is required to be output to a storage module, and meanwhile, an acquisition flag bit is set to indicate that the acquisition of the PCM data is completed.
Optionally, before detecting that the rising edge of the core clock signal of the PCM bus arrives, the acquisition module acquires PCM data according to the received instruction, and stores the acquired PCM data in the storage module, and further includes: and initializing target time slot information, a first counter, a second counter and an acquisition zone bit.
It is easy to understand that before PCM data acquisition, the counter, the acquisition flag bit and the obtained target time slot information need to be initialized to ensure that the acquired data is consistent with the instructions issued by the computer.
Specifically, referring to fig. 4, a flowchart of a method for the acquisition module to acquire PCM data is shown, which is described in detail below:
in step S301, a counter, a time slot TS and an acquisition flag bit are initialized, where the counter includes a first counter cnt1 and a second counter cnt2.
Step S302, determining whether the rising edge of FCLK arrives, when the rising edge of FCLK arrives, executing step S303 and step S305, otherwise executing step S302. Where FCLK represents the core clock signal of the PCM bus.
Step S303, judging whether the FS is in a high level state, executing step S304 when the FS is in a high level state, otherwise, executing step S302. Where FS denotes a frame synchronization signal.
In step S304, the counters cnt1 and cnt2 are enabled.
In step S305, the counter cnt2 counts up by 1.
Step S306, it is determined whether the counter cnt2 is equal to 7, and when the counter cnt2 is equal to 7, step S307 is executed, otherwise step S305 is executed. Wherein the counter cnt2 has a technical range of 0 to 7, representing a one-bit data length.
In step S307, the count of the counter cnt2 is cleared, and the count of the counter cnt1 is incremented by 1.
Step S308, it is determined whether the cnt1 count is equal to TS and cnt2 is equal to 0, and when the cnt1 technique is equal to TS and cnt2 is equal to 0, step S309 is executed, otherwise step S305 is executed.
Step S309, outputting the PCM data, and locating the acquisition flag bit.
The method can collect the data of the target time slot information in the required target collecting channel, and simultaneously store the collected data into the storage module.
In step S104, the transmitting module transmits the PCM data in the storage module to the computer.
Optionally, the sending module sends the PCM data in the storage module to the computer, specifically including:
when the sending module receives the rising edge of the Latch mark signal and the rising edge of the sending clock signal comes, the data stored in the storage module is sent to the computer.
And setting a third counter for counting the clock width of the collected PCM data, and finishing the transmission of the collected PCM data when the third counter reaches a preset value.
It will be readily appreciated that when the sending module sends PCM data in the storage module, a flag signal needs to be received first, indicating that the sending module is allowed to send the data in the storage module. Meanwhile, the transmitting module itself also needs to perform transmitting the acquired PCM data when the transmit clock signal is at the rising edge.
Optionally, before sending the data stored in the storage module to the computer, the method further includes: the sending module sends a start bit to the computer; after sending the data stored in the storage module to the computer, the method further comprises: the sending module sends a stop bit to the computer.
When transmitting data, a start bit 0 is usually transmitted before transmitting data, a stop bit 1 is required to be transmitted after a frame signal is transmitted, and the start bit and the stop bit are transmitted to inform a receiving end that data transmission is about to start or the data transmission is finished. And when the data stored in the storage module is transmitted, counting the transmitted data bits by setting a third counter so as to obtain the required data bit number.
Optionally, after the sending module sends the stop bit to the computer, the method further includes: the transmission module transmits a plurality of idle bits to the computer.
After the stop bit is sent, similar to the above procedure, a number of idle bits need to be sent, indicating no data transmission on the line.
Specifically, referring to fig. 5, a flowchart of a method for the transmitting module to transmit the collected PCM data is shown, which is described in detail below:
Step S401, judging whether the rising edge of the transmission permission signal Latch arrives, executing step S402 when the rising edge of the transmission permission signal Latch arrives, otherwise executing step S401.
Step S402, determining SendClk whether a rising edge arrives, when SendClk comes, executing step S403 and step S404, otherwise executing step S402.
In step S403, the counter cnt3 counts up by 1, and transmits 0 of one clock width.
In step S404, the counter cnt3 counts up by 1.
Step S405, it is determined whether the counter cnt3 is equal to 8, and when the counter cnt3 is equal to 8, step S407 is executed, otherwise step S406 is executed. Here cnt3 is preset to 8 because a start bit of 0 is also sent before the acquired data is sent.
In step S406, data in the memory module is transmitted from the lowest bit.
Step S407, a clock width of 1 is transmitted. Here, the clock width 1 indicates a stop bit of transmission data.
In step S408, an idle bit is transmitted. The idle bit is sent to indicate that the current data transmission is complete.
It is to be understood that the method of transmitting the collected PCM data by the transmitting module is merely a specific embodiment, and other forms of data may be transmitted when transmitting the data.
According to the pulse code signal acquisition method, the receiving module receives the PCM signal acquisition instruction sent by the computer, converts the received acquisition instruction and sends the converted acquisition instruction to the acquisition module, the acquisition module comprises at least one acquisition channel so as to acquire multi-channel PCM data at the same time, the acquisition module acquires the PCM data according to the received converted acquisition instruction and stores the acquired data in the storage module, and the sending module is used for sending the acquired PCM data stored in the storage module to the computer. Through setting each module on the PLD, the parallel operation of each module is realized by utilizing the characteristic of PLD parallelism, so that the real-time performance of PCM signal acquisition is strong, the acquisition module can acquire multipath PCM data at the same time, and the hardware cost is saved.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (6)
1. The Pulse Code Modulation (PCM) signal acquisition device is characterized by comprising a receiving module, an acquisition module, a storage module, a multiplexing module and a sending module;
the receiving module is used for receiving the PCM signal acquisition instruction sent by the computer and converting the received acquisition instruction;
The acquisition module is used for receiving the PCM signal acquisition instruction converted by the receiving module and acquiring PCM data according to the received instruction, and specifically comprises the following steps: the receiving module converts the received PCM signal acquisition instruction to obtain target PCM channel information and target time slot information, and the acquisition module receives the target PCM channel information and the target time slot information; the acquisition module comprises at least one data acquisition channel;
The storage module is used for storing the PCM data acquired by the acquisition module, and specifically comprises: when the rising edge of the core clock signal of the PCM bus is detected to come and the frame synchronization signal is at a high level, acquiring the PCM signal according to the target PCM channel information and the target time slot information; controlling a target acquisition channel of the acquisition module to acquire PCM data according to the target PCM channel information; setting a first counter for counting time slots in a target acquisition channel and a second counter for counting data bits in the target time slots, outputting the acquired PCM data to the storage module when the first counter and the second counter reach preset values, and positioning acquisition flag bits;
The multiplexing module is used for multiplexing the data stored by the storage module onto an output channel;
The sending module is configured to send the PCM data in the storage module to a computer, and specifically includes: when the sending module receives the rising edge of the Latch mark signal and the rising edge of the sending clock signal comes, the data stored in the storage module is sent to a computer; setting a third counter for counting the clock width of the collected PCM data, and finishing the transmission of the collected PCM data when the third counter reaches a preset value;
The receiving module, the acquisition module, the storage module, the multiplexing module and the sending module are arranged on the programmable logic device;
The device is further configured to, prior to detecting the rising edge of the core clock signal of the PCM bus:
initializing the target time slot information, the first counter, the second counter and the acquisition zone bit; wherein, the device adopts a single chip.
2. A PCM signal acquisition method, comprising:
the receiving module receives a PCM signal acquisition instruction sent by a computer;
The receiving module converts the received PCM signal acquisition instruction and sends the converted PCM signal acquisition instruction to the acquisition module, and the method specifically comprises the following steps: the receiving module converts the received PCM signal acquisition instruction to obtain target PCM channel information and target time slot information, and sends the target PCM channel information and the target time slot information to the acquisition module; the acquisition module comprises at least one acquisition channel;
The acquisition module acquires PCM data according to the received instruction and stores the acquired PCM data in the storage module, and the acquisition module specifically comprises: when the rising edge of the core clock signal of the PCM bus is detected to come and the frame synchronization signal is at a high level, acquiring the PCM signal according to the target PCM channel information and the target time slot information;
Controlling a target acquisition channel of the acquisition module to acquire PCM data according to the target PCM channel information;
Setting a first counter for counting time slots in a target acquisition channel and a second counter for counting data bits in the target time slots, outputting the acquired PCM data to the storage module when the first counter and the second counter reach preset values, and positioning acquisition flag bits;
The sending module sends the PCM data in the storage module to the computer, and specifically comprises the following steps: when the sending module receives the rising edge of the Latch mark signal and the rising edge of the sending clock signal comes, the data stored in the storage module is sent to a computer; setting a third counter for counting the clock width of the collected PCM data, and finishing the transmission of the collected PCM data when the third counter reaches a preset value;
Before the rising edge of the core clock signal of the PCM bus is detected, the acquisition module acquires the PCM data according to the received instruction, stores the acquired PCM data into the storage module, and further comprises:
initializing the target time slot information, the first counter, the second counter and the acquisition zone bit;
The method adopts a single chip.
3. The PCM signal collection method according to claim 2, wherein the receiving module receives a PCM signal collection instruction sent by a computer, and specifically includes:
the receiving module detects whether the computer gives an acquisition instruction;
when the computer issues the acquisition instruction, the receiving module receives the PCM signal acquisition instruction sent by the computer.
4. A PCM signal acquisition method according to claim 3, wherein said receiving module detects whether the computer issues an acquisition instruction, specifically comprising: the receiving module detects the level of UartIn pins, and when the data collected by UartIn pins are changed from high level to low level, the computer sends out a collection instruction.
5. The PCM signal acquisition method according to claim 4, wherein before the data stored in the storage module is transmitted to a computer, further comprising: the sending module sends a start bit to the computer;
After the data stored in the storage module is sent to the computer, the method further comprises: the sending module sends a stop bit to the computer.
6. The PCM signal acquisition method according to claim 5, wherein after the transmitting module transmits the stop bit to the computer, further comprising: the transmitting module transmits a plurality of idle bits to the computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711381503.8A CN108021394B (en) | 2017-12-20 | 2017-12-20 | PCM signal acquisition method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711381503.8A CN108021394B (en) | 2017-12-20 | 2017-12-20 | PCM signal acquisition method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108021394A CN108021394A (en) | 2018-05-11 |
| CN108021394B true CN108021394B (en) | 2024-05-14 |
Family
ID=62074492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711381503.8A Active CN108021394B (en) | 2017-12-20 | 2017-12-20 | PCM signal acquisition method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108021394B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6785903B1 (en) * | 2000-04-05 | 2004-08-31 | K Tech Telecommunications, Inc. | Digital television translator with PSIP update |
| CN101998135A (en) * | 2009-08-13 | 2011-03-30 | 上海摩威电子科技有限公司 | System for collecting and playing mobile television signal and control method |
| CN103701624A (en) * | 2013-12-31 | 2014-04-02 | 广东公信数字设备有限公司 | Audio data mixing method and device |
| CN104731748A (en) * | 2015-03-31 | 2015-06-24 | 北京百度网讯科技有限公司 | Method and device for collecting multichannel audio data |
| CN106126186A (en) * | 2016-08-29 | 2016-11-16 | 北京声智科技有限公司 | A kind of multi-channel audio signal parallel acquisition device |
| CN106873464A (en) * | 2017-03-22 | 2017-06-20 | 深圳市中航世星科技有限公司 | A kind of airborne distributed parallel computing environment of restructural and method |
-
2017
- 2017-12-20 CN CN201711381503.8A patent/CN108021394B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6785903B1 (en) * | 2000-04-05 | 2004-08-31 | K Tech Telecommunications, Inc. | Digital television translator with PSIP update |
| CN101998135A (en) * | 2009-08-13 | 2011-03-30 | 上海摩威电子科技有限公司 | System for collecting and playing mobile television signal and control method |
| CN103701624A (en) * | 2013-12-31 | 2014-04-02 | 广东公信数字设备有限公司 | Audio data mixing method and device |
| CN104731748A (en) * | 2015-03-31 | 2015-06-24 | 北京百度网讯科技有限公司 | Method and device for collecting multichannel audio data |
| CN106126186A (en) * | 2016-08-29 | 2016-11-16 | 北京声智科技有限公司 | A kind of multi-channel audio signal parallel acquisition device |
| CN106873464A (en) * | 2017-03-22 | 2017-06-20 | 深圳市中航世星科技有限公司 | A kind of airborne distributed parallel computing environment of restructural and method |
Non-Patent Citations (1)
| Title |
|---|
| 基于DSP的语音采集和处理系统的研究与实现;王玉强;《中国优秀硕士学位论文全文数据库 (信息科技辑)》;20140115(第01期);第I136-295页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108021394A (en) | 2018-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8307344B2 (en) | Sliding granularity time stamping | |
| TWI431984B (en) | Method for capturing multiple data packets in a data signal for analysis | |
| US20150089301A1 (en) | Recording processor instruction execution cycle and non-cycle count trace events | |
| CN101425876B (en) | Communication protocol deciphering method and device | |
| CN103141142A (en) | System and method for collaborative spectrum analysis | |
| CN102438010B (en) | For the method and apparatus of streaming data profiling | |
| CN110191024B (en) | Network traffic monitoring method and device | |
| CN108833366B (en) | Control frame compression method based on AS6802 protocol | |
| CN103176014B (en) | A kind of Wave data decoding apparatus and oscillograph | |
| CN108021394B (en) | PCM signal acquisition method and device | |
| CN112653646B (en) | Method, system, device, processor and storage medium for time-frequency domain data conversion processing of 5G signals of vector signal analyzer platform | |
| CN207718361U (en) | PCM signal harvester and system | |
| CN117009185A (en) | Bus monitoring method, device, system on chip and equipment | |
| CN102779104B (en) | Fault injection method and device for serial port data | |
| KR101957660B1 (en) | Multi-channel oscilloscopes with trigger setup mode for each channel and control method thereof | |
| CN113032320A (en) | Asynchronous serial port communication baud rate self-adaption method | |
| WO2016000423A1 (en) | Delay compensation method and device | |
| US9229841B2 (en) | Systems and methods for detecting errors and recording actions on a bus | |
| CN104639280B (en) | A kind of method and device for transmitting time division multiplexed business | |
| CN1140976C (en) | Signaling No.7 analyzer | |
| CN107078788B (en) | High speed acquisition and analysis of downlink data in a telecommunications system | |
| CN114337708A (en) | Data transmission circuit, method and chip | |
| KR101668752B1 (en) | The method and apparatus for inserting additional information field in ethernet frame | |
| CN113961137A (en) | Data acquisition method and device and electronic equipment | |
| CN104581766A (en) | Special dynamic data collecting and analyzing method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |