CN108010918B - TFT array substrate and manufacturing method thereof - Google Patents
TFT array substrate and manufacturing method thereof Download PDFInfo
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- CN108010918B CN108010918B CN201711201198.XA CN201711201198A CN108010918B CN 108010918 B CN108010918 B CN 108010918B CN 201711201198 A CN201711201198 A CN 201711201198A CN 108010918 B CN108010918 B CN 108010918B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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Abstract
The invention provides a TFT array substrate and a manufacturing method of the TFT array substrate, which comprises the following steps: the device comprises a substrate, a shading layer, an insulating layer, a polycrystalline silicon layer, a grid insulating layer, grid metal, an isolating layer and a metal data line; the grid metal comprises a first grid metal and a second grid metal which are arranged in parallel; the metal data line is respectively connected with the first via hole and the second via hole, and the metal data line is connected with the first grid metal through the first via hole; the metal data line is connected with the polycrystalline silicon layer through a second through hole. The invention provides a TFT array substrate and a manufacturing method of the TFT array substrate, wherein a grid metal is additionally arranged on a grid insulation layer, so that a metal data wire is connected with the grid metal through via holes on two sides above the grid metal, the problem of vertical wire breakage of the TFT array substrate caused by wire breakage during film forming of the metal data wire is avoided, and the production yield of the TFT array substrate is greatly improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a TFT array substrate and a manufacturing method of the TFT array substrate.
Background
A Thin film transistor-liquid crystal display (TFT-LCD) has the advantages of low voltage, low power consumption, large amount of display information, easy colorization, and the like, and occupies a leading position in the current display market. It has been widely used in electronic devices such as electronic computers, electronic notebooks, mobile phones, video cameras, high-definition televisions, and the like.
At present, a TFT-LCD display panel mostly adopts a dual-gate design, as shown in fig. 1, the TFT array substrate includes: a substrate 111, a light-shielding layer 112, an insulating layer 113, a polysilicon layer 12, a gate insulating layer 13, a gate metal 14, a via 17, an isolation layer 15, and a metal data line 16; the metal data line 16 and the gate line 14 in each pixel use different layers of metal lines, and the metal data line 16 and the gate line 14 are separated by an isolation layer 15.
The high-definition display panel presents a finer display picture, and has higher challenge to the production process, namely all metal wires are required to be normally communicated and conducted; however, in the actual production process, the metal data lines 18 are broken during the film formation process of the metal data lines 16, so that the display panel is often broken vertically and difficult to repair, and the display panel cannot be restored normally, thereby affecting the production yield of the display panel.
Disclosure of Invention
The invention provides a TFT array substrate and a manufacturing method of the TFT array substrate, and aims to solve the problem that a display panel cannot normally display due to vertical disconnection of a TFT array substrate caused by disconnection of a metal data line in a film forming process of the metal data line.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
according to an aspect of the present invention, there is provided a TFT array substrate including:
a substrate;
a light shielding layer disposed on a surface of the substrate;
an insulating layer covering the surfaces of the substrate and the light-shielding layer
A polysilicon layer disposed over the insulating layer;
the grid insulation layer covers the surfaces of the polycrystalline silicon layer and the substrate;
the grid metal is arranged on the surface of the grid insulation layer and comprises a first grid metal and a second grid metal which are arranged in parallel;
an isolation layer disposed over the gate insulating layer and the gate metal;
the metal data line is arranged on the surface of the isolation layer and is respectively connected with the first via hole and the second via hole;
the metal data line is connected with the first grid metal through a first through hole; the metal data line is connected with the polycrystalline silicon layer through a second through hole.
According to a preferred embodiment of the present invention, the first via includes a leading end first via and a trailing end first via.
According to a preferred embodiment of the present invention, the first gate metal is a strip metal and is located between the second gate metals, and the first gate metal and the second gate metal are alternately distributed.
According to a preferred embodiment of the present invention, the head end first via hole and the tail end first via hole are located on the upper surfaces of two ends of the first gate metal and are connected to the metal data line.
According to a preferred embodiment of the present invention, the first via hole penetrates through the isolation layer to connect the metal data line and the first gate metal, and the second via hole penetrates through the isolation layer and the gate insulating layer in sequence to connect the metal data line and the polysilicon layer.
According to a preferred embodiment of the present invention, the substrate includes a rigid substrate, a light-shielding layer, and an insulating layer, which are sequentially stacked.
According to another aspect of the present invention, there is provided a method of fabricating a TFT array substrate, the method including:
step S10, providing a substrate, and sequentially arranging a light shielding layer and an insulating layer above the substrate;
step S20, preparing a polycrystalline silicon layer on the surface of the substrate;
step S30, preparing a gate insulation layer on the surface of the polysilicon layer;
step S40, preparing gate metal on the surface of the gate insulating layer, wherein the gate metal comprises a first gate metal and a second gate metal which are arranged in parallel;
step S50, forming an isolation layer on the surface of the gate metal;
step S60, preparing a first via hole and a second via hole, wherein the first via hole penetrates through the isolation layer and is connected with the first gate metal, and the second via hole penetrates through the isolation layer and the gate insulation layer and is connected with the polysilicon layer;
step S70, forming a metal data line on the surface of the isolation layer;
the metal data line is connected with the first grid metal through a first through hole; the metal data line is connected with the polycrystalline silicon layer through a second through hole.
According to a preferred embodiment of the present invention, the first via hole includes a head end first via hole and a tail end first via hole.
According to a preferred embodiment of the present invention, the first gate metal is a strip metal and is located between the second gate metals, and the first gate metal and the second gate metal are alternately distributed.
According to a preferred embodiment of the present invention, the head end first via hole and the tail end first via hole are located on the upper surfaces of two ends of the first gate metal and connected to the metal data line.
The invention provides a TFT array substrate and a manufacturing method of the TFT array substrate, wherein a grid metal is additionally arranged on a grid insulation layer, so that a metal data wire is connected with the grid metal through via holes on two sides above the grid metal, the problem of vertical wire breakage of the TFT array substrate caused by wire breakage during film forming of the metal data wire is avoided, and the production yield of the TFT array substrate is greatly improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a TFT array substrate with a metal data line vertically broken according to the prior art;
fig. 2 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a TFT array substrate according to an embodiment of the invention;
fig. 4a to 4g are schematic structural diagrams of a process of a method for manufacturing a TFT array substrate according to an embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The invention provides a manufacturing method of a TFT (thin film transistor) substrate and a manufacturing method of an OLED (organic light emitting diode) display device, aiming at solving the problem that in the existing TFT array substrate and TFT array substrate manufacturing technology, vertical disconnection occurs on the TFT array substrate due to disconnection during film forming of a metal data line.
The invention is further described with reference to the following figures and specific embodiments:
fig. 2 is a schematic structural diagram of a TFT array substrate in an embodiment of the present invention, fig. 3 is a flowchart of a manufacturing method of the TFT array substrate, fig. 4a to 4g are schematic structural diagrams of a flowchart of a manufacturing method of a TFT array substrate in an embodiment of the present invention, the present invention provides a schematic structural diagram of a TFT array substrate, and the TFT array substrate includes:
a base plate 211, which is typically a glass substrate;
a light shielding layer 212, wherein the light shielding layer 212 may be a metal plate or a non-metal plate, generally corresponds to the position of the second gate metal 24, and is located right below the second gate metal 24;
and the insulating layer 213 is completely covered on the surfaces of the light-shielding layer 212 and the substrate 211.
Generally, the insulating layer 213 may be silicon nitride or silicon dioxide, and the insulating layer 213 serves to isolate the substrate 211 from the polysilicon layer 22, so as to prevent metal ions in the substrate 211 from diffusing into the polysilicon layer 22, thereby reducing the formation of defect centers and the generation of leakage current.
A polysilicon layer 22 disposed on the surface of the substrate 21;
in general, the polysilicon layer 22 is an active layer, and the polysilicon layer 22 includes a source heavily doped region and a drain heavily doped region respectively located at two outer sides, and a channel region located between the source heavily doped region and the drain heavily doped region.
A gate insulating layer 23 covering the surfaces of the polysilicon layer 22 and the substrate 21;
typically, a gate insulating layer 23, also called a gate oxide, covers the polysilicon layer 22 and serves as an interface between the polysilicon layer 22 and the gate for isolating the polysilicon layer 22 from the gate, and the gate insulating layer 23 may be silicon nitride, or a layer of silicon nitride and a layer of silicon dioxide.
A gate metal disposed on the surface of the gate insulating layer 23, including a first gate metal 28 and a second gate metal 24 disposed in parallel;
the gate metal is disposed on the gate insulating layer 23, the first gate metal 28 and the second gate metal 24 are located on the same horizontal plane, and the first gate metal 28 and the second gate metal are alternately distributed.
In the embodiment of the present invention, the first gate metal 28 is a strip metal, and the second gate metal 24 is a block metal, preferably, the width of the first gate metal 28 is the same as the width of the second gate metal 24, but the length of the first gate metal 28 is much longer than that of the second gate metal 24.
The reason for this is that, in the embodiment of the present invention, the first gate metal 28 is used as a spare metal data line, and is separated from the data metal line 27 by the isolation layer 25, but is connected to the data metal line 27 through the first via 29, so that when the data metal line is vertically disconnected, current can still be conducted through the first gate metal 28, thereby preventing the TFT array substrate from being vertically disconnected.
Furthermore, the gate electrode is usually formed of aluminum or an aluminum alloy.
An isolation layer 25 disposed over the gate insulating layer 23 and the gate electrode;
the isolating layer 25 can be one layer or two layers; when the isolation layer 25 is a layer, this layer may be silicon oxide, silicon nitride, or aluminum oxide; when the isolation layer 25 is two layers, the first layer is a silicon dioxide film, and a second layer of silicon nitride is added on the silicon dioxide film in order to improve the quality of the film.
And the metal data line 26 is arranged on the surface of the isolation layer 25, and the metal data line 26 is respectively connected with the first via hole 29 and the second via hole 27.
Wherein, the metal data line 26 is connected to the first gate metal 28 through a first via 29; the metal data line is connected to the polysilicon layer 22 through a second via 27.
As shown in fig. 2, the first via 29 includes a head end first via and a tail end first via, which are respectively connected to two ends of the first gate metal 28.
The first via 29 penetrates through the isolation layer 25 to connect the metal data line 26 and the first gate metal 28, and the second via 27 penetrates through the isolation layer 25 and the gate insulating layer 23 in sequence to connect the metal data line 26 and the polysilicon layer 22.
According to another embodiment of the present invention, as shown in fig. 3 and 4a to 4g, the present invention provides a method for manufacturing a TFT array substrate, including:
as shown in fig. 4a, in step S10, providing a substrate 311, and sequentially disposing a light-shielding layer 312 and an insulating layer 313 above the substrate 311;
as shown in fig. 4b, step S20, preparing a polysilicon layer 32 on the surface of the substrate 311;
as shown in fig. 4c, step S30, preparing a gate insulating layer 33 on the surface of the polysilicon layer 32;
as shown in fig. 4d, in step S40, preparing a gate metal on the surface of the gate insulating layer 33, where the gate metal includes a first gate metal 38 and a second gate metal 34 that are arranged side by side;
as shown in fig. 4e, in step S50, forming an isolation layer 35 on the surface of the gate metal;
as shown in fig. 4f, step S60, preparing a first via 39 and a second via 37, where the first via 39 penetrates the isolation layer 35 to connect to the first gate metal 38, and the second via 37 penetrates the isolation layer 35 and the gate insulating layer 33 to connect to the polysilicon layer 32;
as shown in fig. 4g, step S70, forming a metal data line 36 on the surface of the isolation layer 35;
wherein the metal data line 36 is connected to the first gate metal 38 through a first via 39, and the metal data line 36 is connected to the polysilicon layer 33 through a second via 37.
The principle of the method for manufacturing the TFT array substrate in this embodiment is consistent with the above TFT array substrate principle, and reference may be made to the working principle of the TFT array substrate in the above preferred embodiment, which is not described herein again.
The invention provides a TFT array substrate and a manufacturing method of the TFT array substrate, wherein a grid metal is additionally arranged on a grid insulation layer, so that a metal data wire is connected with the grid metal through via holes on two sides above the grid metal, the problem of vertical wire breakage of the TFT array substrate caused by wire breakage during film forming of the metal data wire is avoided, and the production yield of the TFT array substrate is greatly improved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (3)
1. A TFT array substrate, comprising:
a substrate;
a light shielding layer disposed on a surface of the substrate;
the insulating layer is covered on the surfaces of the substrate and the shading layer;
a polysilicon layer disposed over the insulating layer;
the grid insulation layer covers the surfaces of the polycrystalline silicon layer and the substrate;
the grid electrode metal is arranged on the surface of the grid electrode insulating layer and comprises a first grid electrode metal and a second grid electrode metal which are arranged in parallel, the first grid electrode metal is a strip-shaped metal, and the first grid electrode metal and the second grid electrode metal are alternately distributed;
an isolation layer disposed over the gate insulating layer and the gate metal;
the metal data line is arranged on the surface of the isolation layer, is respectively connected with the first via hole and the second via hole, is connected with the first grid metal through the first via hole, and is connected with the polycrystalline silicon layer through the second via hole;
the first via hole comprises a first head end via hole and a first tail end via hole, and the first head end via hole and the first tail end via hole are located on the upper surfaces of two ends of the first grid metal and connected with the metal data line.
2. The TFT array substrate of claim 1, wherein the first via penetrates the isolation layer to connect the metal data line and the first gate metal, and the second via penetrates the isolation layer and the gate insulating layer in turn to connect the metal data line and the polysilicon layer.
3. A manufacturing method of a TFT array substrate is characterized by comprising the following steps:
step S10, providing a substrate, and sequentially arranging a light shielding layer and an insulating layer above the substrate;
step S20, preparing a polysilicon layer on the surface of the insulating layer;
step S30, preparing a gate insulation layer on the surface of the polysilicon layer;
step S40, preparing a gate metal on the surface of the gate insulation layer,
the grid metal comprises a first grid metal and a second grid metal which are arranged in parallel, the first grid metal is a strip metal, and the first grid metal and the second grid metal are alternately distributed;
step S50, forming an isolation layer on the surface of the gate metal;
step S60, preparing a first via hole and a second via hole, wherein the first via hole penetrates through the isolation layer and is connected with the first gate metal, and the second via hole penetrates through the isolation layer and the gate insulation layer and is connected with the polysilicon layer;
step S70, forming a metal data line on the surface of the isolation layer,
the metal data line is connected with the first grid metal through a first through hole, and the metal data line is connected with the polycrystalline silicon layer through a second through hole;
the first via hole comprises a first head end via hole and a first tail end via hole, and the first head end via hole and the first tail end via hole are located on the upper surfaces of two ends of the first grid metal and connected with the metal data line.
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| CN1619837A (en) * | 2003-09-03 | 2005-05-25 | 三星Sdi株式会社 | Active matrix organic light emitting device having series thin film transistor, and fabrication method therefor |
| CN105742296A (en) * | 2016-03-31 | 2016-07-06 | 上海天马有机发光显示技术有限公司 | Array substrate, fabrication method thereof, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1619837A (en) * | 2003-09-03 | 2005-05-25 | 三星Sdi株式会社 | Active matrix organic light emitting device having series thin film transistor, and fabrication method therefor |
| CN105742296A (en) * | 2016-03-31 | 2016-07-06 | 上海天马有机发光显示技术有限公司 | Array substrate, fabrication method thereof, display panel and display device |
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