CN108009119B - 处理器和控制工作流的方法 - Google Patents

处理器和控制工作流的方法 Download PDF

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CN108009119B
CN108009119B CN201710970437.1A CN201710970437A CN108009119B CN 108009119 B CN108009119 B CN 108009119B CN 201710970437 A CN201710970437 A CN 201710970437A CN 108009119 B CN108009119 B CN 108009119B
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memory
task
dpu
memory units
host
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CN108009119A (zh
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牛迪民
李双辰
鲍勃·布伦南
克里希纳·T·马拉丁
郑宏忠
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Databases & Information Systems (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
CN201710970437.1A 2016-10-27 2017-10-18 处理器和控制工作流的方法 Active CN108009119B (zh)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201662413977P 2016-10-27 2016-10-27
US201662413973P 2016-10-27 2016-10-27
US62/413,977 2016-10-27
US62/413,973 2016-10-27
US201662414426P 2016-10-28 2016-10-28
US62/414,426 2016-10-28
US201762485370P 2017-04-13 2017-04-13
US62/485,370 2017-04-13
US15/595,887 2017-05-15
US15/595,887 US10732866B2 (en) 2016-10-27 2017-05-15 Scaling out architecture for DRAM-based processing unit (DPU)

Publications (2)

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CN108009119A CN108009119A (zh) 2018-05-08
CN108009119B true CN108009119B (zh) 2023-04-11

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US (3) US10732866B2 (https=)
JP (1) JP6920170B2 (https=)
KR (1) KR102253582B1 (https=)
CN (1) CN108009119B (https=)
TW (1) TWI714803B (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11163707B2 (en) * 2018-04-23 2021-11-02 International Business Machines Corporation Virtualization in hierarchical cortical emulation frameworks
JP7053891B2 (ja) * 2018-06-27 2022-04-12 シャンハイ カンブリコン インフォメーション テクノロジー カンパニー リミテッド オンチップコードのブレークポイントによるデバッグ方法、オンチッププロセッサ及びブレークポイントによるチップデバッグシステム
US10915470B2 (en) * 2018-07-23 2021-02-09 SK Hynix Inc. Memory system
WO2020078470A1 (zh) * 2018-10-18 2020-04-23 上海寒武纪信息科技有限公司 片上网络数据处理方法及装置
US11327808B2 (en) * 2018-11-13 2022-05-10 Western Digital Technologies, Inc. Decentralized data processing architecture
US10884664B2 (en) * 2019-03-14 2021-01-05 Western Digital Technologies, Inc. Executable memory cell
US10884663B2 (en) 2019-03-14 2021-01-05 Western Digital Technologies, Inc. Executable memory cells
US11157692B2 (en) * 2019-03-29 2021-10-26 Western Digital Technologies, Inc. Neural networks using data processing units
CN111857061A (zh) * 2019-04-28 2020-10-30 北京国电智深控制技术有限公司 一种计算任务实现方法、装置及系统、存储介质
US12056382B2 (en) * 2020-05-26 2024-08-06 Qualcomm Incorporated Inference in memory
TWI742774B (zh) * 2020-07-22 2021-10-11 財團法人國家實驗研究院 運算系統及其主機資源分配方法
US11645111B2 (en) * 2020-10-23 2023-05-09 International Business Machines Corporation Managing task flow in edge computing environment
US12197601B2 (en) * 2020-12-26 2025-01-14 Intel Corporation Hardware offload circuitry
CN116204456A (zh) * 2021-11-30 2023-06-02 华为技术有限公司 数据访问方法及计算设备
CN114201421B (zh) 2022-02-17 2022-05-10 苏州浪潮智能科技有限公司 一种数据流处理方法、存储控制节点及可读存储介质
US12517711B2 (en) * 2023-03-07 2026-01-06 Lemon Inc. Computation architecture synthesis
CN116069480B (zh) * 2023-04-06 2023-06-13 杭州登临瀚海科技有限公司 一种处理器及计算设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4068305A (en) * 1975-05-12 1978-01-10 Plessey Handel Und Investments Ag Associative processors
US7401261B1 (en) * 2003-12-19 2008-07-15 Unisys Corporation Automatic analysis of memory operations using panel dump file
CN105573959A (zh) * 2016-02-03 2016-05-11 清华大学 一种计算存储一体的分布式计算机架构

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5713037A (en) * 1990-11-13 1998-01-27 International Business Machines Corporation Slide bus communication functions for SIMD/MIMD array processor
EP0570729A3 (en) 1992-05-22 1994-07-20 Ibm Apap i/o programmable router
EP0689712A4 (en) 1993-03-17 1997-05-28 Zycad Corp CONFIGURABLE FIELDS WITH DIRECT ACCESS MEMORY ARRANGEMENT
US5847577A (en) 1995-02-24 1998-12-08 Xilinx, Inc. DRAM memory cell for programmable logic devices
US6760833B1 (en) * 1997-08-01 2004-07-06 Micron Technology, Inc. Split embedded DRAM processor
US6026478A (en) 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
JPH11338767A (ja) 1998-05-22 1999-12-10 Mitsubishi Heavy Ind Ltd 画像処理用機能メモリ装置
US6424658B1 (en) 1999-01-29 2002-07-23 Neomagic Corp. Store-and-forward network switch using an embedded DRAM
WO2001001242A1 (en) 1999-06-30 2001-01-04 Sun Microsystems, Inc. Active dynamic random access memory
US6555398B1 (en) * 1999-10-22 2003-04-29 Magic Corporation Software programmable multiple function integrated circuit module
US20030105799A1 (en) 2001-12-03 2003-06-05 Avaz Networks, Inc. Distributed processing architecture with scalable processing layers
WO2004038599A1 (de) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Rekonfigurierbare sequenzerstruktur
US6947348B2 (en) 2003-07-15 2005-09-20 International Business Machines Corporation Gain cell memory having read cycle interlock
US7752380B2 (en) * 2003-07-31 2010-07-06 Sandisk Il Ltd SDRAM memory device with an embedded NAND flash controller
US20110026323A1 (en) 2009-07-30 2011-02-03 International Business Machines Corporation Gated Diode Memory Cells
US8478947B2 (en) * 2005-07-05 2013-07-02 Arm Limited Memory controller
US8301833B1 (en) 2007-06-01 2012-10-30 Netlist, Inc. Non-volatile memory module
US8694776B2 (en) * 2007-12-21 2014-04-08 Spansion Llc Authenticated memory and controller slave
US8341362B2 (en) 2008-04-02 2012-12-25 Zikbit Ltd. System, method and apparatus for memory with embedded associative section for computations
US8238173B2 (en) 2009-07-16 2012-08-07 Zikbit Ltd Using storage cells to perform computation
US9047351B2 (en) * 2010-04-12 2015-06-02 Sandisk Enterprise Ip Llc Cluster of processing nodes with distributed global flash memory using commodity server technology
US8566669B2 (en) 2010-07-07 2013-10-22 Ocz Technology Group Inc. Memory system and method for generating and transferring parity information
US8379433B2 (en) 2010-09-15 2013-02-19 Texas Instruments Incorporated 3T DRAM cell with added capacitance on storage node
US20140247673A1 (en) 2011-10-28 2014-09-04 Naveen Muralimanohar Row shifting shiftable memory
JP6106043B2 (ja) 2013-07-25 2017-03-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9921980B2 (en) * 2013-08-12 2018-03-20 Micron Technology, Inc. Apparatuses and methods for configuring I/Os of memory for hybrid memory modules
WO2015070110A2 (en) * 2013-11-07 2015-05-14 Netlist, Inc. Hybrid memory module and system and method of operating the same
US9455020B2 (en) 2014-06-05 2016-09-27 Micron Technology, Inc. Apparatuses and methods for performing an exclusive or operation using sensing circuitry
GB2530261B (en) * 2014-09-16 2016-08-03 Ibm Memory and processor hierarchy to improve power efficiency
US9954533B2 (en) 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
US9697877B2 (en) 2015-02-05 2017-07-04 The Board Of Trustees Of The University Of Illinois Compute memory
JP5974133B1 (ja) * 2015-03-20 2016-08-23 株式会社東芝 メモリシステム
US10430618B2 (en) * 2015-10-09 2019-10-01 George Mason University Vanishable logic to enhance circuit security

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4068305A (en) * 1975-05-12 1978-01-10 Plessey Handel Und Investments Ag Associative processors
US7401261B1 (en) * 2003-12-19 2008-07-15 Unisys Corporation Automatic analysis of memory operations using panel dump file
CN105573959A (zh) * 2016-02-03 2016-05-11 清华大学 一种计算存储一体的分布式计算机架构

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TW201816595A (zh) 2018-05-01
KR20180046363A (ko) 2018-05-08
US20240211149A1 (en) 2024-06-27
US10732866B2 (en) 2020-08-04
US12340101B2 (en) 2025-06-24
KR102253582B1 (ko) 2021-05-18
TWI714803B (zh) 2021-01-01
JP6920170B2 (ja) 2021-08-18
JP2018073414A (ja) 2018-05-10
US20180121120A1 (en) 2018-05-03
US11934669B2 (en) 2024-03-19
CN108009119A (zh) 2018-05-08
US20200363966A1 (en) 2020-11-19

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