CN108008660A - Orthogonal signalling high-speed, high precision processing method based on DSP and FPGA - Google Patents
Orthogonal signalling high-speed, high precision processing method based on DSP and FPGA Download PDFInfo
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- CN108008660A CN108008660A CN201710652068.1A CN201710652068A CN108008660A CN 108008660 A CN108008660 A CN 108008660A CN 201710652068 A CN201710652068 A CN 201710652068A CN 108008660 A CN108008660 A CN 108008660A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2612—Data acquisition interface
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2656—Instrumentation
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Abstract
The invention discloses a kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA, including FPGA industry level processor and DSP two parts, FPGA industry level processor, DSP to realize data communication by dual port RAM；Using DSP as data processing core, it is responsible for main mathematic(al) manipulation and calculates；Using FPGA as coprocessor, it is responsible for all Digital Logic controls, realizes collection, mean filter, error compensation, real-time phase computation, phase subdivision sensing and the storage of related data and the display of quadrature signal；DSP calculates the error compensation parameter of the orthogonal signalling data of FPGA collections by matrix operation, and is communicated by dual port RAM error compensation parameter being passed to FPGA.In signal acquisition, transmission, amendment, subdivision sensing to data store whole process, DSP is shared out the work and helped one another the present invention with FPGA, can either meet system real time requirement, and realizes the high Precision Processing of orthogonal signalling.
Description
Technical field：
The present invention relates to field of precision measurement, is mainly at a kind of orthogonal signalling high-speed, high precision based on DSP and FPGA
Reason method.
Background technology：
Grating sensor and laser interferometer are widely used in modern precision measuring instrument, numerically-controlled machine tool, litho machine, superfinishing
The fields such as processing, quantum physics, biomolecular science, are that modern precision tests typical measuring apparatus.Therefore grating is improved to pass
The range and precision of sensor and laser interferometer precision distance measurement technology have important practical significance.In practical applications,
The electronic noise introduced due to the foozles such as extraneous environmental noise, optical element, electronic circuit and other it is various it is comprehensive because
The influence of element, do not waited there is alternating-current magnitude in actually measured two paths of signals, DC level component and quadrature error etc. by mistake
Difference, finally influences displacement measurement accuracy.In order to meet increasingly accurate measurement request and application scenario, grating sensor and laser
Interferometer also develops to correspondingly high-resolution, high accuracy, height several directions such as test the speed.
The method of existing lifting grating sensor and laser interferometer measurement precision mainly relies on traditional
Heydemann ellipse modification methods.The method that oval modification method is estimated in real time based on quadrature interference signals parameter, utilizes mathematics
Model compensates error, then lifts measuring system precision by segmenting sensing.Based on Heydemann ellipse modification methods
Orthogonal signalling processing method due to being related to data acquisition, error parameter calculating, error compensation procedure, subdivision and are deposited at sensing process
Process, the speed and processing accuracy to links in signal processing such as storage display have very high requirement, therefore usual feelings
Condition may only carry out orthogonal signalling off-line analysis and compensation, it is difficult to while realize orthogonal signalling real-Time Compensation and high Precision Processing.
The content of the invention：
The purpose of patent of the present invention is to solve orthogonal signalling real-time existing for high Precision Processing process is poor, integrated level
The index such as the low, problem such as precision is low, the precision of optimization orthogonal signalling measuring system output measurement data, resolution ratio, real-time, carries
A kind of small, using flexible, small power consumption, performance height, the high speed of the orthogonal signalling based on DSP and FPGA of fast response time are supplied
High Precision Processing method；This method can overcome the electricity that the foozles such as extraneous environmental noise, optical element, electronic circuit introduce
Sub- noise and other various composite factors restrict, and based on FPGA and DSP architecture, improve conversion speed and signal processing essence
Degree, expands the use scope of the optical instruments such as homodyne interferometer, is carried for High Precision Grating Signals with Micro Computers analysis with error high-speed compensation
For hardware solution.
To achieve the above object, the technical solution of patent use of the present invention is：
A kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA, it is characterised in that：Including FPGA industry
Level processor (2) and DSP (3) two parts, FPGA industry level processor (2), DSP (3) realize data by dual port RAM (10)
Communication；The specific implementation step of the method is as follows：
First, light intensity signal includes the positive alternating current of simulation of displacement information through opto-electronic conversion and signal conditioning circuit (1) output
Signal is pressed, high speed analog-to-digital conversion is carried out to signal by FPGA industry level processor (2) driving AD sampling modules (4), and in FPGA
The orthogonal signalling data further optimized by mean filter (5) in industrial level processor (2), are handled by FPGA technical grades
Device (2) write-in dual port RAM (10) is stored and speed buffering；
Then, DSP (3) reads the orthogonal signalling number in dual port RAM (10) by way of EMIF interface outer extension memories
According to, and (11) are screened to sampled data, rejecting abnormalities point, then calculates compensating parameter (12) by matrix operation, and will
In compensating parameter write-in dual port RAM (10) and SDRAM (13), then by FPGA industry level processor (2) reading；
At this time, FPGA industry level processor (2) carries out Real-time Error using the compensating parameter quadrature signal for calculating gained
Compensate (6), real-time phase computation (7) and subdivision sensing (8)；
Finally, the phase number of real-time update writes dual port RAM (10) and is calculated in real time by DSP (3) and store displacement, position
Move data to be read by FPGA industry level processor (2) through dual port RAM (10) again, and store SD card (14) by data and protected
Deposit, while be sent to VGA display modules (9) and shown.
A kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA, it is characterised in that：It is described
Real time data between FPGA industry level processor (2) and DSP (3) interacts as follows：FPGA industry level processor (2) is to DSP (3)
The instruction in direction is by setting an interrupt signal in the FPGA industry level processor (2), when DSP (3) receives the signal, then
Start to carry out mean filter digital independent according to rule from dual port RAM (10)；DSP (3) to FPGA industry level processor (2) into
During row data transfer, it then follows same executing rule, DSP (3) provide an I/O signal, notice FPGA industry level processor (2)
Data are read from dual port RAM (10).
A kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA, it is characterised in that：In DSP
(3) parameter is compensated in and calculates (12), is comprised the concrete steps that：By error source substep compensation orthogonal signalling error, including orthogonal letter
Quadrature error α present in number, amplitude fluctuations, dc shift error, amount to 7 errors.
A kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA, it is characterised in that：In FPGA
(2) phase calculation (7) and subdivision sensing (8) are carried out in, is comprised the following steps that：Phase calculation (7) is based on according to cordic algorithm
Arc tangent trigonometric function operation calculates the corresponding phase value of each sampled point, and is converted to high-subdividing number by section, by thin
The size of fraction judges measurement data moving direction and realizes the tracking of displacement, exports each effective sampling points and corresponds to comprising real-time
The data of displacement information, and it is converted into displacement information in DSP (3).
FPGA industry level processor (2) is coprocessor, is responsible for all Digital Logic controls；DSP (3) is data processing
Corn module, is set using embedded hardware multiplier, modified Harvard structure, pipeline organization and the integrated circuit of optimization
Meter, increases the handling capacity of signal processor, the speed that DSP instructions perform is substantially improved, so as to fulfill efficient error compensation parameter
Calculate.
When FPGA industry level processor (2) drives high-speed sampling：When measurement data is positive to be incremented by, with real-time phase in the cycle
Place value is incremented by, and adjacent 2 phase differences are always just and are close to 0, and forward direction is moved to new moment in cycle real-time phase value from change
To π, the moment adjacent 2 phase differences are negative and are close to；When measurement data is reversely successively decreased, with real-time phase value in the cycle
Successively decreasing, adjacent 2 phase differences are always to bear and be close to 0, move backward to new moment in cycle real-time phase value and are changed to from π,
The moment adjacent 2 phase differences is just and are close to 2 π.Therefore, several sizes according to adjacent 2 phase differences complete cycle judge
Signal moving direction is simultaneously mutually increasing complete cycle issue into the new moment in cycle, is subtracting computing.
Compared with the prior art, it is an advantage of the invention that：
The present invention is in patent《Orthogonal signalling real-time processing method based on FPGA》(the patent No.：201710234903X) base
On plinth, improved on hardware structure and algorithm, a kind of pure hardware realization handled when being orthogonal signalling high-precision real.
The present invention coordinates hardware structures of the FPGA as core based on FPGA and DSP architecture in structure using DSP, using DSP as
Data processing core, is mainly responsible for main mathematic(al) manipulation and calculates；Using FPGA industry level processor as coprocessor, it is responsible for all
Digital Logic controls, the ability that the characteristics of giving full play to FPGA high-speed parallels and DSP are quickly calculated.FPGA and DSP cooperates
Work, both communications are completed by a piece of dual port RAM, and its inside is pressed two pieces of its memory space decile, utilize skill of rattling
Art completes quadrature signal high speed data buffering in real time.The method of the present invention is arrived in signal acquisition, transmission, amendment, subdivision sensing
In the whole process such as data storage, DSP is shared out the work and helped one another with FPGA, can either meet system real time requirement, and is realized orthogonal
The high Precision Processing of signal.The present invention is clear in structure, and signal processing is quick, efficient, it can be achieved that swashing to grating sensor and single-frequency
The online compensation of optical interferometer signal in orthogonal error, amplitude fluctuations, dc shift error etc., is the analysis of High Precision Grating Signals with Micro Computers
And the real-Time Compensation of error provides engineered solution.
Brief description of the drawings：
Fig. 1 is a kind of orthogonal signalling high-speed, high precision processing method system construction drawing based on DSP and FPGA.
Fig. 2 is real-time orthogonal signalling processing system block diagram.
Fig. 3 is the work flow diagram of FPGA industry level processors.
Fig. 4 is the work flow diagram of DSP.
Embodiment：
Referring to attached drawing 1, a kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA, including FPGA industry
Level processor 2 and DSP3 two parts, FPGA industry level processor 2, DSP3 realize data communication by dual port RAM 10；The side
The specific implementation step of method is as follows：
First, light intensity signal exports the simulation quadrature voltage for including displacement information through opto-electronic conversion and signal conditioning circuit 1
Signal, drives AD sampling modules 4 to carry out high speed analog-to-digital conversion to signal by FPGA industry level processor 2, and in FPGA technical grades
The orthogonal signalling data further optimized by mean filter 5 in processor 2, are write double by FPGA industry level processor 2
Mouth RAM10 is stored and speed buffering；
Then, DSP (3) reads the orthogonal signalling number in dual port RAM 10 by way of EMIF interface outer extension memories
According to, and screening 11 is carried out to sampled data, rejecting abnormalities point, then calculates compensating parameter 12 by matrix operation, and will compensation
In parameter read-in dual port RAM 10 and SDRAM13, then read by FPGA industry level processor 2；
At this time, FPGA industry level processor 2 carries out Real-time Error benefit using the compensating parameter quadrature signal for calculating gained
Repay 6, real-time phase computation 7 and subdivision sensing 8；
Finally, the phase number of real-time update writes dual port RAM 10 and is calculated in real time by DSP3 and store displacement, displacement number
According to being read again through dual port RAM 10 by FPGA industry level processor 2, and store SD card 14 by data and preserved, send at the same time
Shown to VGA display modules 9.
Real time data between FPGA industry level processor 2 and DSP3 interacts as follows：FPGA industry level processor 2 is to DSP3
The instruction in direction in FPGA industry level processor 2 by setting an interrupt signal, when DSP3 receives the signal, then start
From dual port RAM 10 mean filter digital independent is carried out according to rule；DSP3 carries out data transmission to FPGA industry level processor 2
When, it then follows same executing rule, DSP3 provide an I/O signal, and notice FPGA industry level processor 2 is from dual port RAM 10
Read data.
Referring to attached drawing 2, this signal processing method system can be divided into：Signal acquisition module, Logic control module, data storage
Module, real-time display module, high-speed transfer module and compensating parameter computing module etc..According to 2 He of FPGA industry level processor
The respective responsibilities of DSP3 are different, and FPGA industry level processor 2 is mainly responsible for the collection of orthogonal signalling, the display of displacement signal with depositing
The logic control of storage, the speed buffering of data and whole circuit；DSP3 is mainly responsible for the calculating of orthogonal signalling error compensation parameter.
Referring to attached drawing 3,4, whole signal processing system workflow is：System electrification, it is dynamic that FPGA circuitry completes initialization
After work, the high speed acquisition and mean filter of orthogonal signalling are proceeded by；DSP completes self-test, waits the external interrupt in FPGA directions
Signal 1；FPGA opens the data channel to DSP, starts the buffering of quadrature signal sampled data, and data are stored in dual port RAM
In, when amount of storage reaches certain quantity, beginning sends interrupt signal 1 to DSP in real time；After DSP receives the signal 1, immediately from
Data are read in dual port RAM and the matrix operation of parameter is compensated based on Heydemann ellipse fitting algorithms, calculates and completes
Afterwards, in compensating parameter deposit dual port RAM, and interrupt signal 2 is provided to FPGA；FPGA utilizes benefit immediately after receiving interrupt signal 2
Repay parameter to compensate sampled signal, the revise signal after compensation enters arctangent cp cp operation and base based on CORDIC algorithms
In the subdivision sensing module of section conversion, the phase information deposit dual port RAM of real-time update is obtained, and interruption is provided to DSP
Signal 3；DSP receives interrupt signal 3, phase information is converted into real-time displacement amount deposit dual port RAM in inside, and carry to FPGA
For interrupt signal 4；FPGA reads displacement data after receiving the signal 4 from dual port RAM, and displacement data is deposited with document form
Storage is in SD cards.At this time if extraneous do not send end signal, continue data transfer and signal processing；It is if extraneous
End signal is sent, then FPGA is notified that DSP terminates to encode.
Quadrature error α present in orthogonal signalling, amplitude fluctuations, dc shift error, amount to 7 errors.Signal passes through
The error compensation parameter that DSP is realized calculates, and algorithm is as follows：
Orthogonal signalling actual mathematical model is：
Then have：
It can obtain the elliptic equation of orthogonal signalling according to trigonometric function relation：
In order to facilitate curve matching, above formula can be rewritten as：
AX2+BY2+ CXY+DX+EY=1
Following matrix operation is carried out in dsp：
The value of coefficient A, B, C, D, E can be obtained by calculating five rank matrixes, then by being simply calculated the value of α, and
Quadrature signal compensates in write-in FPGA：
The embodiments of the present invention described above are not intended to limit the scope of the present invention.It is any in the present invention
Spirit and principle within the modifications, equivalent substitutions and improvements made etc., should be included in the claim protection model of the present invention
Within enclosing.
Claims (4)
- A kind of 1. orthogonal signalling high-speed, high precision processing method based on DSP and FPGA, it is characterised in that：Including FPGA technical grades Processor (2) and DSP (3) two parts, FPGA industry level processor (2), DSP (3) realize that data are led to by dual port RAM (10) Letter；The specific implementation step of the method is as follows：First, light intensity signal through opto-electronic conversion and signal conditioning circuit (1) output, believe by the simulation quadrature voltage comprising displacement information Number, high speed analog-to-digital conversion is carried out to signal by FPGA industry level processor (2) driving AD sampling modules (4), and in FPGA industry The orthogonal signalling data further optimized by mean filter (5) in level processor (2), by FPGA industry level processors (2) dual port RAM (10) is write to be stored and speed buffering；Then, DSP (3) reads the orthogonal signalling data in dual port RAM (10) by way of EMIF interface outer extension memories, And (11) are screened to sampled data, rejecting abnormalities point, then calculates compensating parameter (12) by matrix operation, and will compensation In parameter read-in dual port RAM (10) and SDRAM (13), then by FPGA industry level processor (2) reading；At this time, FPGA industry level processor (2) carries out real-time error compensation using the compensating parameter quadrature signal for calculating gained (6), real-time phase computation (7) and subdivision sensing (8)；Finally, the phase number of real-time update writes dual port RAM (10) and is calculated in real time by DSP (3) and store displacement, displacement number According to being preserved again through dual port RAM (10) by FPGA industry level processor (2) reading, and by data storage SD card (14), together When be sent to VGA display modules (9) and shown.
- 2. a kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA according to claim 1, its feature It is：Real time data between the FPGA industry level processor (2) and DSP (3) interacts as follows：FPGA industry level processors (2) instruction to DSP (3) direction in FPGA industry level processor (2) by setting an interrupt signal, when DSP (3) is received To the signal, then start to carry out mean filter digital independent according to rule from dual port RAM (10)；DSP (3) is to FPGA technical grades When processor (2) carries out data transmission, it then follows same executing rule, DSP (3) provide an I/O signal, notice FPGA industry Level processor (2) reads data from dual port RAM (10).
- 3. a kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA according to claim 1, its feature It is：Parameter is compensated in DSP (3) and calculates (12), is comprised the concrete steps that：Orthogonal signalling error is compensated by error source substep, Including quadrature error α present in orthogonal signalling, amplitude fluctuations, dc shift error, amount to 7 errors.
- 4. a kind of orthogonal signalling high-speed, high precision processing method based on DSP and FPGA according to claim 1, its feature It is：Phase calculation (7) and subdivision sensing (8) are carried out in FPGA (2), is comprised the following steps that：Phase calculation (7) basis Cordic algorithm, the corresponding phase value of each sampled point is calculated based on arc tangent trigonometric function operation, and is changed by section To high-subdividing number, measurement data moving direction is judged by the size of high-subdividing number and realizes the tracking of displacement, output is each effectively adopted Sampling point corresponds to the data for including real-time displacement information, and is converted into displacement information in DSP (3).
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Cited By (4)
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| CN110196391A (en) * | 2019-06-27 | 2019-09-03 | 中国兵器工业集团第二一四研究所苏州研发中心 | Digital circuit test device and method based on FPGA and DSP architecture |
| CN110426974A (en) * | 2019-08-08 | 2019-11-08 | 南京邮电大学 | A kind of equivalent sampling control circuit based on quadrature phase gating |
| CN111722559A (en) * | 2020-05-18 | 2020-09-29 | 四川九洲电器集团有限责任公司 | Low-power-consumption processing method based on DSP and FPGA architecture |
| CN114184837A (en) * | 2021-12-09 | 2022-03-15 | 电子科技大学 | Instantaneous frequency measurement method based on Cordic algorithm |
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Application publication date: 20180508 |