CN107992376A - Dsp processor data storage Active Fault Tolerant method and apparatus - Google Patents

Dsp processor data storage Active Fault Tolerant method and apparatus Download PDF

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Publication number
CN107992376A
CN107992376A CN201711192783.8A CN201711192783A CN107992376A CN 107992376 A CN107992376 A CN 107992376A CN 201711192783 A CN201711192783 A CN 201711192783A CN 107992376 A CN107992376 A CN 107992376A
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data
wrong
instruction
correct
data storage
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CN107992376B (en
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曹辉
何卫强
于飞
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Xian Microelectronics Technology Institute
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Xian Microelectronics Technology Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Abstract

The present invention provides dsp processor data storage Active Fault Tolerant method and apparatus, and device is arranged in dsp processor core assembly line and core between data storage, refreshes for data storage Active Fault Tolerant；Including for loading the LOAD instruction decoding of data storage, the STORE Instruction decodings for writing data storage, queue accesses module, RSEC Instruction decodings module, data storage, data error correction and detection module, general register file, wrong status register, circulation Record queues, data storage write operation module and interruption processing module for hard break processing can be corrected；Divided by suitable assembly line, have substantially no effect on the frequency performance of dsp processor.The present invention can flexibly control hardware to meet system reliability at lower cost to fault-tolerant processing strategy and opportunity, ensure execution efficiency of the dsp processor under the abnormal conditions that malfunction.

Description

Dsp processor data storage Active Fault Tolerant method and apparatus
Technical field
The invention belongs to microelectronics technology, is related to highly reliable, high-performance processor fault-tolerant architecture, is specially at DSP Manage device data storage Active Fault Tolerant method and apparatus.
Background technology
Memory is component most sensitive in modern processors.Especially with the continuous advancement of semiconductor fabrication process, The characteristic size of integrated circuit drastically reduces.On the one hand, the supply voltage that is constantly reduced in Nanometer integrated circuit, be continuously improved Working frequency, the node capacitor that persistently reduces and the chip transistor capacity of rapid growth cause memory cell to work Environment is more and more sensitive.When memory circuitry is influenced be subject to energetic particle hits, power supply noise, electromagnetic effect or cosmic ray, The content for causing to store in the storage unit of chip is by transient state or permanent destruction.On the other hand, on-chip memory is integrated with largely Transistor, generally taken up substantial amounts of area in whole processor.Substantial amounts of transistor and area add memory and are subject to Interference produces the possibility of mistake, reduces the global reliability of device.Therefore, in order to improve the reliability of processor, in piece Memory is pointedly reinforced, and is reliability problem important in ASIC design and processor design.Moreover, in many It is required that in the not high processor of reliability requirement, also only the reinforcing to on-chip memory to improve reliability.
To the reliability Design of Reinforcement of memory, there are process level, element layout level and system-level reinforcement measure.System The reinforcing of level is unrelated with concrete implementation technique because having higher protection level, is more common reinforcement measure.System Irrespective of size reinforcement measure includes carrying out error checking and correction coding protection, and increase redundancy using parity check code or ECC check code Ranks are stored to carry out build-in object, close the technology such as free memory locations, in advance write back data block and faulty section isolation.It is more Core dsp processor has real-time due to the application field such as data-oriented dense process and the image procossing exchanged, signal processing The characteristics of property and high-throughput.
In presently disclosed document, most of electronic device built-in storagies for central processing unit (CPU) type carry out Fault-tolerant reinforcing, rarely has the memory fault-tolerant measure for referring to the electronic device to digital signal processor (DSP) type.Document " A portable and fault-tolerant microprocessor based on disclosed in [Gaisler, 2002] The sparc v8 architecture " disclose a kind of data storage reinforcement means.When the data is accessed, to data Carry out " even-odd check ", if verification data mistake, just by data " calcellation ", and access the number again from external memory storage According to.This method is a kind of " passive " fault-tolerant method, and for a small number of processor cores of on piece monokaryon or shared memory, integrate can OK, but for the processor for being interconnected based on network-on-chip (NoC, Network-on-Chip), visited by network-on-chip Ask that external memory storage has that to have dsp processor larger etc. to be delayed.In addition, dsp processor data-oriented stream process, one Denier error in data can cause DSP data flows to disconnect it is necessary to access external memory storage, be unfavorable for improving dsp processor performance.Should Document discloses a kind of assembly line processing method at the same time, when the operand read in memory detects repairable mistake, Assembly line is emptied, and the data after correction are write back into memory.When assembly line is longer, the error correction and detection process of data is located at , it is necessary to which the instruction emptied is more before " writing back " operation.But if if subsequent instructions do not have phase with present instruction result Guan Shi, can continue to execute.Simply emptying pile line operation can fall the instruction " waste " for coming into assembly line.
Most dsp processors all only have single-level memory structure, as disclosed in Freescale companies 2005 " " TriMedia TM-1300 ", Texas disclosed in MSC8102Technical Data ", Philips companies 2000 " TMS320C6000 CPU and Instruction Set Reference disclosed in Instruments companies 2000 Guide ", it updates write-back not in time to data storage, can cause the cumulative effect of memory error.If in order to avoid Error event, disabling piece upper level storage, fetches from external memory storage, although correct data can be obtained, can cause Very big memory access latency, is unfavorable for the performance of dsp processor performance.
The content of the invention
For problems of the prior art, the present invention provides a kind of dsp processor data storage Active Fault Tolerant side Method and device, can be realized in data memory storage in the case of not interrupt instruction assembly line and " instruction retracts " Hold " active " error correction write-back after there is mistake；Reloading after data access error can be avoided, so as to ensure processor Execution efficiency under the abnormal conditions that malfunction.
The present invention is to be achieved through the following technical solutions：
Dsp processor data storage Active Fault Tolerant device, it is arranged on data in dsp processor core assembly line and core and deposits Between reservoir, refresh for data storage Active Fault Tolerant；Including the LOAD instruction for loading data storage is decoded, used In writing the STORE Instruction decodings of data storage, queue accesses module, RSEC Instruction decodings module, data storage, data Error correction and detection module, general register file, wrong status register can be corrected, circulation Record queues, data storage write behaviour Make module and the interruption processing module for hard break processing；
LOAD instruction decoding be used for receive dsp processor programmed instruction, judge current procedure instruction whether LOAD instruction, And the encoded control logic of LOAD instruction is exported to data storage；STORE Instruction decodings are used to receive dsp processor program Instruction, judges whether STORE is instructed current procedure instruction, and exports the encoded control logic of STORE instructions successively through circulation Record queues, queue accesses module and data memory write operation module are to data storage；RSEC Instruction decoding modules connect Dsp processor programmed instruction is received, judges whether RSEC is instructed current procedure instruction, and the encoded control for exporting RSEC instructions is patrolled Collect through queue accesses module to circulation Record queues；The data that the input of data error correction and detection module exports for data storage With data check code, the error condition and repairable correct data and check code for current accessed data are exported；Register text Part is used for the LOAD instruction corrected data, preserve after data error correction and detection resume module for receiving the output of data error correction and detection module The data of access；The error condition that wrong status register is used to connect data error correction and detection module samples current data can be corrected；Number According to the write control signal of memory write operation module output data memory；The input of interruption processing module is dsp processor Hardware interrupt request signal, wrong interrupt service routine connection RSEC Instruction decoding modules can be corrected through data by exporting.
Preferably, data error correction and detection module receives parallel input data and check code from data storage, completion pair Read in the error correction and detection function of data；And output can correct wrong Single_Error and can not correct wrong Multiple_Error shapes Data and information of check code after state information, error correction and detection；Wrong Single_Error states can be corrected be connected to can correct wrong state Register and interrupt flag register；Data connection after error correction and detection extremely circulates Record queues and destination register file；Entangle Check code after error detection is connected to circulation Record queues；
Described to correct wrong status register, preservation can correct wrong status information, identify whether current dsp processor enters Data can correct wrong state；Wrong status register reception can be corrected and correct wrong status information from data error correction and detection module The wrong state of correcting of Single_Error and RSEC Instruction decoding modules removes control；, will when Single_Error is effective Wrong status register set can be corrected；When can correct wrong state remove control signal it is effective when, it is clear that wrong status register can be corrected Zero；When Single_Error and can correct wrong state remove control signal it is effective at the same time when, Single_Error control signals tool There is higher priority, wrong status register can be corrected and reset；It can correct before wrong mode bit is eliminated, it is continuous multiple Data, which can correct wrong event pair, can correct wrong status register repetition set.
Preferably, the circulation Record queues include Record queues and quene state register；
Quene state register is used for the current state of mark queue, including whether queue overflowed and handled Tail of the queue；The depth number of circulation Record queues should be greater than the delay number of interrupt response, with pipeline decoding section and data error correction and detection The sum of flowing water segment number between flowing water section where module；Circulation Record queues have two parts input, and Part I input comes From the current LOAD instruction decoding in the error correction and detection data and error correcting code and dsp processor assembly line of data error correction and detection module Control information Core_Read_Control, Part II input the data from the output of STORE Instruction decodings, check code and work as The control information Core_Write_Control of preceding memory write operation instruction；
If data error correction and detection module detects that the data of current accessed have repairable mistake, just Part I is inputted In information write-in circulation Record queues, and it the input of wrong status information can be corrected can correct wrong status register and renewal team Row status register；In the case where wrong status register set can be corrected, if having STORE instructions in subsequent operation instruction Operation, by Part II input write-in circulation Record queues in and renewal quene state register；
Circulating the content of each single item record of Record queues includes accessing degree of parallelism Pon, concurrent access base address BaseAddr, word/byte mode BW, can correct data or write back data and the check code of data after wrong correct；The data Memory write operation module by the STORE data instructed and check code write back data memory, or by Record record in number Data storage is corrected back according to check code renewal.
Preferably, the interruption processing module, by entangling for one of hardware interrupt request connection current accessed data Positive mistake state interrupt, and data storage can correct wrong interrupt has higher interrupt priority level；The interrupt processing mould Block, including hardware Interrupt Process logic, interrupt flag register, interrupt enable register, interrupt vector table and hard break service Program area；The hardware Interrupt Process logic, interrupts assembly line of the current dsp processor assembly line to normal executive program, and Jump at interrupt vector table, obtain the entrance of hardware interrupts service routine；The interrupt flag register and interruption, which enable, posts Storage coordinates hardware Interrupt Process logic to enter the service of interruption, and wrong interrupt effectively can be corrected when interrupting enabled register pair data In the case of enabled, the data of hardware Interrupt Process logic judgment interrupt flag register can correct whether wrong interrupt flag has Effect, and can correct wrong interrupt flag it is effective in the case of, make dsp processor enter data can correct fault reason service routine In；Data error correction and detection module correct wrong state output Single_Error be connected to the data of interrupt flag register can Correct on wrong interruption position；Interrupt flag register can correct data wrong status signal and be sampled and be recorded；It is described it is hard in Disconnected service routine area, the entrance that the interrupt vector table handled by hard break is specified enter；Wrong interrupt simultaneously can be corrected when data occur And when enabled effective, dsp processor can correct wrong interrupt processing entrance by the data in interrupt vector table, and jumping to data can Correct wrong interrupt service routine.
Preferably, the RSEC Instruction decodings module, accesses circulation Record one entry of queue, and by entry The data and check bit that are preserved in Record entries are passed through data storage by output to data storage write operation module Write operation module is renewed back to data storage.
Dsp processor data storage Active Fault Tolerant method, comprises the following steps：
Step 1, dsp processor initializes, and wrong interrupt response can be corrected by opening；It can be corrected when data storage occurs in mistake When disconnected, wrong hardware interrupts can be corrected by dsp processor is responded；
Step 2, data will be accessed from data storage according to LOAD instruction, and according to the extension to LOAD instruction, it is right The error state of data is verified；To different error states in LOAD instruction implementation procedure, performing data can correct It is wrong/wrong state processing can not be corrected；
Data perform step 3 after can correcting fault reason；In the case where data occur and can not correct mistake, generation can not be corrected Wrong interrupt signal, dsp processor present instruction, which performs, to be terminated, and carries out other instruction processing；
Step 3, in the case where data occur and can correct mistake, judge that current processor assembly line and down-stream instruction are held During row, if having STORE instructions；Handled if so, continuing step 4；Otherwise, 5 processing are gone to step；
Step 4, STORE instructions are performed, and according to the extended operation instructed to STORE, in the data for instructing STORE While writing memory, the control information of STORE instructions and data record are entered into circulation Record queues；
Step 5, processor response can correct wrong hardware interrupts；Data can correct wrong triggering processor hardware and interrupt, and enter Data can correct wrong interrupt service routine processing；
Step 6, in interrupt service routine, the record in recursive call instruction RSEC instruction processing loops Record queues, Until sky is read in queue；And after wrong correct can be corrected, Refresh Data is write by the STORE memories instructed and returns data storage, it is complete Wrong data update of correcting into after by correction returns data storage；
Step 7, wrong interrupt can be corrected to return；
Step 8, dsp processor normal operation.
Preferably, the LOAD instruction processing method extended in step 2 includes,
Step A-1, dsp processor access instruction；
Step A-2, judges whether that LODA is instructed according to instruction operation code；It is LOAD instruction, handles rapid A-3；Otherwise, locate Manage step A-12；
Step A-3, LOAD instruction decoding；
Step A-4, accesses data storage, obtains data；
Step A-5, data are sent into data error correction and detection module and carry out error correction and detection, and can correct wrong Single_Error and Wrong Multiple_Error can not be corrected to judge；
Step A-6, if generation can not correct wrong Multiple_Error；If so, go to step A-10 processing；Otherwise, turn Step A-7；
Step A-7, the data that data error correction and detection module is exported, by the destination register index write-in mesh of LOAD instruction Register group in；
Step A-8, judges whether that generation can correct wrong Single_Error；If so, wrong register set can be corrected, Processing step A-9；Otherwise, A-11 is gone to step；
Step A-9, by the data after the error correction of data error correction and detection module output, check code and LOAD instruction assembly line Memory access control information, be sequentially written in circulation Record queues；Go to step A-11；
Step A-10, generation can not correct multi-bit error, and generation can not correct wrong interrupt signal；
Step A-11, dsp processor present instruction, which performs, to be terminated；
Step A-12, dsp processor carry out other instruction processing.
Preferably, the processing method of the STORE after being extended in step 4 includes：
Step B-1, dsp processor instruction fetch；
Step B-2, judges whether that STORE is instructed according to instruction operation code；It is STORE instructions, handles rapid B-3；Otherwise, Go to step B-9；
Step B-3, STORE Instruction decoding；From register group read operands；
Step B-4, produces operand check code；
Step B-5, judgement can currently correct wrong status register whether set；If so, processing step B-6；Otherwise, turn Step B-7；
Step B-6, by the memory access control information on operand data, operand check code and STORE instruction pipelines, It is sequentially written in circulation Record queues；
Step B-7, data storage is write by operand data, operand check code；
Step B-8, dsp processor present instruction, which performs, to be terminated.
Step B-9, dsp processor carry out other instruction processing.
Further, in the step A-9 and step B-6, the method for circulation Record queue records is：
Step E-1, if Single_Error=true, the data after mistake and check code will be corrected by error correction method, Together with reading data base address, degree of parallelism and word/byte-accessed pattern write-in queue tail of this data storage, go to step E- 3；Otherwise, processing step E-2；
Step E-2, if can currently correct, wrong status register is effective, and memory write operation instructs writing for STORE The effective Write_Valid of data manipulation is effective, and data and the check code produced by coding method are stored together with this data Device writes data base address, degree of parallelism and word/byte-accessed Mode B W write-in queue tails, goes to step E-3；Otherwise, go to step E-3；
Whether step E-3, detection queue overflow, juxtaposition corresponding state position.
Preferably, in step 6, when recursive call instructs the record in RSEC instruction processing loops Record queues, RESC instructions read a record from team's head of circulation Record queues, by the data in record according to memory access control information It is renewed back to data storage；Wherein, the operating method of RESC instructions is：
Step C-1, instruction fetch；
Step C-2, judges whether that RESC is instructed according to instruction operation code；It is RESC instructions, handles rapid C-3；Otherwise, turn Step C-9；
Step C-3, RESC Instruction decoding, outputs a control signal to queue accesses module；
Step C-4, queue accesses module read a record Record (Head) from team's head of circulation Record queues；
Step C-5, send the data and control information of Record (Head) into data storage write operation module；
Step C-6, data storage is write by operand data, operand check code；
Step C-7, removing can correct wrong marker register；
Step C-8, instruction execution terminate；
Step C-9, other instruction processing.
Compared with prior art, the present invention has technique effect beneficial below：
Dsp processor data storage fault tolerance facility of the present invention, dsp processor is placed on by the process of data error correction and detection On core assembly line, divided by suitable assembly line, have substantially no effect on the frequency performance of dsp processor.Conventional approach is by data Error correction and detection is placed in accumulator system, adds the access delay of memory data.
Dsp processor data storage fault-tolerance approach provided by the invention, it is proposed that a kind of soft by interrupt service routine The fault-tolerance approach of part and combination of hardware, with reference to service routine, can flexibly control hardware to holding according to the reliability index of system Wrong processing strategy and opportunity, meet system reliability at lower cost.Detecting entangling for data store access content , can be by dsp processor assembly line " active " error correction after lookup error, and data after correction are write with a brush dipped in Chinese ink into back data storage in time In；" cache miss " is produced, it is necessary to again from external memory storage or next stage memory again after avoiding data content error The situation of the corresponding monoblock data of loading, so as to ensure execution efficiency of the dsp processor under the abnormal conditions that malfunction.
Brief description of the drawings
Fig. 1 is the dsp processor data storage fault tolerance facility of the present invention；
Fig. 2 is the process flow that data storage read operation of the present invention instructs LOAD；
Fig. 3 is the process flow that data storage write operation of the present invention instructs STORE；
Fig. 4 is the process flow that queue accesses of the present invention instruct RSEC instructions；
Fig. 5 can correct wrong information and memory write operation information into the schematic diagram of enqueue for the present invention；
Fig. 6 is processor data memory fault-tolerance processing method flow of the present invention.
Embodiment
With reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and It is not to limit.
Dsp processor data storage fault tolerance facility provided by the invention and method, design towards highly reliable processor and lead Domain, is application oriented processor reliability design, there is provided the solution method in the support and software on hardware configuration.
Dsp processor data storage Active Fault Tolerant device of the present invention, to be arranged on dsp processor core assembly line and core Between interior data storage, the circuit for the refreshing of data storage Active Fault Tolerant.The Active Fault Tolerant device includes circuits below Module：LOAD instruction decoding, the STORE Instruction decodings for writing data storage, queue for loading data storage are visited Ask module, queue accesses write-back instructions decoding module (RSEC Instruction decodings module), data storage, data error correction and detection module, General register file, for can correct wrong data storage correct wrong status register, circulation Record queues, number Interruption processing module according to memory write operation module and for hard break processing.
The connection relation of each module is：LOAD instruction decoding receives dsp processor programmed instruction, judges that present procedure refers to Order whether LOAD instruction, and export the encoded control logic of LOAD instruction to data storage.STORE Instruction decodings receive DSP Processor program instructs, and judges whether STORE is instructed current procedure instruction, and export the encoded control logic of STORE instructions extremely Data storage.RSEC Instruction decodings module receives dsp processor programmed instruction, judges whether RSEC refers to current procedure instruction Order, and export RSEC instruction encoded control logic to circulate Record queues.The input of data storage is LOAD instruction Data are read to control and export to control the lower data accessed and data check code for LOAD instruction；Data storage also input data Control information and write-in data are write in the data storage write operation logic of memory write operation module, output.Data error correction and detection mould Block input for data storage output data and data check code, export for current accessed data error condition and can The correct data and check code of correction.Register file receives the data of correcting of data error correction and detection module output, preservation data The data that LOAD instruction after error correction and detection resume module accesses；Register file output STORE instructions will write data storage Data.The error condition of wrong status register sampling current data can be corrected.The input of circulation Record queues refers to for LOAD What order accessed corrects data and data store access control information and the data and data store access of STORE instructions Control information.The input of data storage write operation module is the memory write operation control signal of STORE Instruction decodings and follows The write operation control signal read in ring Record queues, exports the write control signal for data storage.Hard break processing Input the hardware interrupt request signal for dsp processor.
Further, the data error correction and detection module, receives parallel input data and check code from data storage, Complete the error correction and detection function to reading in data；And output can correct wrong Singl_e Err and or and can not correct wrong Multiple_ Data and information of check code after Error status informations, error correction and detection.Wrong Single_Error states can be corrected to be connected to and can entangle Positive mistake status register and interrupt flag register；Data connection to circulation Record queues and purpose after error correction and detection is deposited Device file；Check code after error correction and detection is connected to circulation Record queues.
Further, described to correct wrong status register, preservation can correct wrong status information, identify current DSP processing Whether device, which enters data, can correct wrong state.Wrong status register can be corrected and receive correcting from data error correction and detection module The wrong state of correcting of wrong status information Single_Error and RSEC Instruction decoding module removes control.Work as Single_ When Error is effective, wrong status register set can be corrected；When can correct wrong state remove control signal it is effective when, can correct Wrong status register is reset；When Single_Error and can correct wrong state remove control signal it is effective at the same time when, Single_ Error control signals have higher priority, can correct wrong status register and reset.Wrong mode bit can be corrected to be eliminated Before, continuous multiple data, which can correct wrong event pair, can correct wrong status register repetition set.
The circulation Record queues, including Record queues and quene state register.Circulation Record queues have two Part inputs, error correction and detection data and error correcting code and dsp processor assembly line of the Part I input from data error correction and detection module On current LOAD instruction decoding control information Core_Read_Control, Part II input from STORE instruction translates Data, check code and the control information Core_Write_Control of current storage write operation instruction of code output.If number Detect that the data of current accessed have repairable mistake according to error correction and detection module, just by Part I input information write-in circulation In Record queues, and it the input of wrong status information can be corrected can correct wrong status register and renewal quene state register； In the case where wrong status register set can be corrected, if having the operation that STORE is instructed in subsequent operation instruction, it is necessary to will Part II input write-in circulates in Record queues and renewal quene state register.
The control information Core_Read_Control of the memory read operation instruction includes：Read data access degree of parallelism Pon, reads base address address ReadBaseAddr, word/byte mode BW, reads the effective Read_Valid of data manipulation；Memory is write The control information Core_Write_Control of operational order STORE includes：Data access degree of parallelism Pon is write, with writing base address Location WriteBaseAddr, word/byte mode BW, the effective Write_Valid of data writing operation.
The content of each single item record of circulation Record queues includes：Access degree of parallelism Pon, concurrent access base address BaseAddr, word/byte mode BW, can correct data or write back data after wrong correct, the check code of data.
Preferably, the circulation Record queues, effective input record information is recorded in the way of first in first out and is entered RecordkIn queue.
Further, the circulation Record queues, including one group of quene state register.Quene state register is used for The current state of mark queue.Whether overflowed including queue and whether handled tail of the queue.Circulate the depth of Record queues Flowing water section between flowing water section where number should be greater than the delay number+pipeline decoding section and data error correction and detection module of interrupt response Quantity.
Preferably, whether the current decoding instruction of the STORE Instruction decodings, also detection is that data storage write operation refers to Order, and will to the control information Core_Write_Control of STORE Instruction decodings export and STORE data and check code, Can correct wrong status register it is effective in the case of, be input to circulation Record queues.
Further, the RSEC Instruction decodings module, accesses circulation Record one entry of queue, and will record Item output is stored the data and check bit that are preserved in Record entries by data to data storage write operation module Device write operation module is renewed back to data storage.Preferably, RSEC instruct, from circulation Record queues team head access queue, By team head record Record (head) outputs to data storage write operation module.
The data storage write operation module, according to the control information of STORE Instruction decodings and circulation Record queues The control information of output, produces the base address Addr of data storage write operation, accesses degree of parallelism Pon's and byte mode BW Control information, by STORE instruction data and check code write back data memory, or by Record record in data and school Test code renewal and correct back data storage.
Further, the interruption processing module, by one of hardware interrupt request connection current accessed data can Wrong state interrupt is corrected, and data storage can correct wrong interrupt has higher interrupt priority level.
Preferably, the interruption processing module, including hardware Interrupt Process logic, interrupt flag register, interrupt it is enabled Register, interrupt vector table and hard break service routine area.
The hardware Interrupt Process logic, interrupts assembly line of the current dsp processor assembly line to normal executive program, and Jump at interrupt vector table, obtain the entrance of hardware interrupts service routine.Preferably, interrupt flag register and interruption make Energy register coordinates hardware Interrupt Process logic to enter the service of interruption, when the enabled register pair data of interruption can correct wrong interruption In the case of effectively enabling, the data of hardware Interrupt Process logic judgment interrupt flag register, which can correct wrong interrupt flag, is It is no effectively, and can correct wrong interrupt flag it is effective in the case of, make dsp processor enter data can correct fault reason service In program.The number corrected wrong state output Single_Error and be connected to interrupt flag register of data error correction and detection module According to can correct on wrong interruption position；Interrupt flag register can correct data wrong status signal and be sampled and be recorded.
Preferably, the hard break service routine area, the entrance that the interrupt vector table handled by hard break is specified enter.When When generation data can correct wrong interruption and enable effective, dsp processor can correct wrong interruption by the data in interrupt vector table Entrance is handled, wrong interrupt service routine can be corrected by jumping to.
Dsp processor data storage Active Fault Tolerant method of the present invention, comprises the following steps：
Step 1, dsp processor initializes, and wrong interrupt response can be corrected by opening.It can be corrected when data storage occurs in mistake When disconnected, wrong hardware interrupts can be corrected by dsp processor is responded；
Step 2, data store access instruction (LOAD) will access data from data storage.And according to LOAD The extension of instruction, verifies the error state of data.To different error states in LOAD instruction implementation procedure, hold Row data can correct it is wrong/wrong state processing can not be corrected；
Step 3, in the case where data occur and can correct mistake, judge that current processor assembly line and down-stream instruction are held During row, if there is memory to write (STORE) instruction.Handled if so, continuing step 4；Otherwise, 5 processing are gone to step；
Step 4, STORE instructions are performed, and according to the extended operation instructed to STORE, in the data for instructing STORE While writing memory, the control information of STORE instructions and data record are entered into circulation Record queues；
Step 5, processor response can correct wrong hardware interrupts.Data can correct wrong triggering processor hardware and interrupt, and enter Data can correct wrong interrupt service routine processing；
Step 6, in interrupt service routine, the record in recursive call instruction RSEC instruction processing loops Record queues, Until sky is read in queue.Data update after correction is returned into data storage.And after wrong correct can be corrected, by STORE instructions Memory writes Refresh Data and returns data storage；
Step 7, wrong interrupt can be corrected to return；
Step 8, dsp processor normal operation.
A kind of control method of processor data memory Active Fault Tolerant, loads the data storage of processor (LOAD) processing method of instruction is extended.The LOAD instruction processing method position of extension：
Step A-1, dsp processor access instruction；
Step A-2, judges whether that LODA is instructed according to instruction operation code.It is LOAD instruction, handles rapid A-3；Otherwise, locate Manage step A-12；
Step A-3, LOAD instruction decoding；
Step A-4, accesses data storage, obtains data；
Step A-5, data are sent into data error correction and detection module and carry out error correction and detection and can correct wrong Single_Error, can not entangle Positive mistake Multiple_Error judges.
Step A-6, if generation can not correct wrong Multiple_Error.If so, go to step A-10 processing；Otherwise, turn Step A-7；
Step A-7, the data that data error correction and detection module is exported, by the destination register index write-in mesh of LOAD instruction Register group in；
Step A-8, judges whether that generation can correct wrong Single_Error.If so, wrong register set can be corrected, Processing step A-9；Otherwise, A-11 is gone to step；
Step A-9, by the data after the error correction of data error correction and detection module output, check code and LOAD instruction assembly line Memory access control information, be sequentially written in circulation Record queues；Go to step A-11；
Step A-10, generation can not correct multi-bit error, and generation can not correct wrong interrupt signal.
Step A-11, instruction execution terminate.
Step A-12, other instruction processing.
In the LOAD instruction operating process step A-5, data error correction and detection circuit is divided into N groups by data parallel degree, every group A corresponding 32bit word, data error correction and detection is carried out by word for unit.Error correction and detection logic is with 32 data bit
D=d32d31d20d29d28d27d26d25d24d23d22d21d20d19d18d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1
(di,{1≤i≤32}={ 0,1 })
With 8 bit check position P'=p'8p'7p'6p'5p'4p'3p'2p1'(pi',{1≤i≤8}={ 0,1 })
Generate 8 bit-errors flag P=p8p7p6p5p4p3p2p1(pi,{1≤i≤8}={ 0,1 })
The generation logic of flag is：
Wherein,For XOR operation；Order
Method according to P value error correction and detections is：
(1) if P=, " 0000000, " shows that data and check code are error-free, Multiple Single_ Error=false；
(2) if weight='0' and p8p7p6p5p4p3p2p1≠ " 0000000 ", shows in data D or check code P' Having two, there occurs mistake, Multiple_Error=true；Data or check code not error correction；
(3) if weight='1' and p8p7p6p5p4p3p2p1≠ " 0000000 ", shows in data D or check code P' Having one, there occurs mistake, Single_Error=true；The method of data bit error correction is：
Wherein, " " is step-by-step AND operation；"+" is step-by-step inclusive-OR operation；Computing " is negated " for step-by-step；di', 1≤i≤32 are data bit diThe data bit after wrong correct can be corrected；KiComputational methods it is as follows：
The method that check bit can correct wrong error correction is：
If pi≠ ' 0 ', (1≤i≤8), andSo p 'jAppearance can correct mistake,
Wherein, the p ' of equation right endj, 1≤j≤8 can correct the result after wrong correct for check bit；The p ' of equation left endj, 1≤j≤8 can correct the numerical value before wrong correct for check bit.
Further, for supporting the processor of multiple parallel degree, with above-mentioned error correction and detection method by carrying out data in units of word Error correction and detection.The method for the error correction and detection state that present parallel accesses data is obtained according to the degree of parallelism Pon of data is：
(1) if data parallel degree is 1, i.e. Pon=1, thenMultiple_Error= m0；Wherein miIt is that can correct wrong state, 0≤i≤3, s by word for the parallel data of unit respectivelyiBe respectively by word for unit and The double wrong states of row data, 0≤i≤3；
(2) if data parallel degree is 2, i.e. Pon=2, then Single_Error=s0∨s1, Multiple_Error =m0∨m1；∨ is step-by-step inclusive-OR operation；
(3) if data parallel degree is 4, i.e. Pon=4, then Single_Error=s0∨s1∨s2∨s3, Multiple_Error=m0∨m1∨m2∨m3；∨ is step-by-step inclusive-OR operation.
A kind of control method of processor data memory Active Fault Tolerant, writes the data storage of processor (STORE) processing method of instruction is extended.The processing method of STORE after extension is：
Step B-1, instruction fetch；
Step B-2, judges whether that STORE is instructed according to instruction operation code.It is STORE instructions, handles rapid B-3；Otherwise, Go to step B-9；
Step B-3, STORE Instruction decoding；From register group read operands；
Step B-4, produces operand check code；
Step B-5, judgement can currently correct wrong status register whether set.If so, processing step B-6；Otherwise, turn Step B-7；
Step B-6, by the memory access control information on operand data, operand check code and STORE instruction pipelines, It is sequentially written in circulation Record queues；
Step B-7, data storage is write by operand data, operand check code；
Step B-8, instruction execution terminate.
Step B-9, other instruction processing.
After the extension in memory write instruction STORE operating process steps B-4, the logic of operand check bit is produced For：
Wherein, data check code is produced in units of 32 bit data word D：
D=d32d31d20d29d28d27d26d25d24d23d22d21d20d19d18d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1
(di,{1≤i≤32}={ 0,1 })
Produce 8 bit check position P '=p '7p′6p′5p′4p′3p′2p′1(p′I, { 1≤i≤7 }={ 0,1 }).
Further, for the processor of support multiple parallel degree, the verification of data is produced for unit by word in aforementioned manners Code.Processor is set to possess the parallel multi-bit false retrieval brake in units of word.
In the step A-9 and step B-6, the method for circulation Record queue records is：
Step E-1, if Single_Error=true, data D and check code after mistake will be corrected by error correction method P', together with reading data base address ReadBaseAddr, degree of parallelism Pon, word/byte-accessed Mode B W of this data storage Write queue tail
Record (Tail)=Record (Single_Error)={ D, P', ReadBaseAddr, Pon, BW }, goes to step E- 3；Otherwise, processing step E-2；
Step E-2, if can currently correct, wrong status register is effective, and memory write operation instructs writing for STORE The effective Write_Valid of data manipulation is effective, and data D and the check code P' produced by coding method are deposited together with this data Reservoir writes data base address WriteBaseAddr, degree of parallelism Pon, word/byte-accessed Mode B W write-in queue tails Record (Tail)=Record (Write_Instruction)={ D, P', WriteBaseAddr, Pon, BW }, goes to step E-3；Otherwise, E-3 is gone to step；
Whether step E-3, detection queue overflow, juxtaposition corresponding state position.
After the extension in memory write instruction STORE operating process steps B-6, it can be corrected when data storage occurs Mistake, after " can correct wrong status register " set, circulation Record queues are sequentially recorded after generation can correct mistake, subsequently The control information Record (Write_Instruction) of the write command of data storage.Record Record (Write_ Instruction purpose) is when avoiding the Record (Single_Error) from being written back to data storage, and data storage occurs The write after write of device is related.
Further, the control method of a kind of processor data memory Active Fault Tolerant, in step 6, RESC refers to Make and read a record from team's head of circulation Record queues, the data in record are renewed back to according to memory access control information Data storage.RESC instruction operating method be：
Step C-1, instruction fetch；
Step C-2, judges whether that RESC is instructed according to instruction operation code.It is RESC instructions, handles rapid C-3；Otherwise, turn Step C-9；
Step C-3, RESC Instruction decoding, outputs a control signal to queue accesses module；
Step C-4, queue accesses module read a record Record (Head) from team's head of circulation Record queues；
Step C-5, send the data and control information of Record (Head) into memory write operation module；
Step C-6, data storage is write by operand data, operand check code；
Step C-7, removing can correct wrong marker register；
Step C-8, instruction execution terminate.
Step C-9, other instruction processing.
Further, in the step C-5 in memory write operation module, with STORE instruction flows step B-7 it is hard Part logic is identical, the hardware logic being multiplexed in processor pipeline on STORE instruction pipelines.
In the operating process step C-4 of the RESC instructions, the method for entry is read from circulation Record queues is：
Whether step F-1, detection current queue read sky, juxtaposition corresponding state position；Step F-2 is performed if not for sky, An empty team leader knowledge is then returned if empty；
Step F-2, reads team head record Record (Head), and team's head is directed toward the next record of current record.
Further, the control method of a kind of processor data memory Active Fault Tolerant, can correct mistake in step 6 Interrupt service routine processing method is：
Step D-1, judges whether previous cycle Record queues have read sky.If so, go to step D-3；Otherwise, handle Step D-2；
Step D-2, performs RESC instructions.Go to step D-1；
Step D-3, interruption service terminate, and interrupt and return.
In this preferred embodiment, the beneficial effect of the present invention is illustrated with the High Performance DSP processor of a SIMD frameworks Fruit.The processor uses Harvard structure, integrates 16KB data storages and 16KB program storages.Wherein, to data storage Access support the access of degree of parallelism Pon={ 1,2,4 }, i.e., each clock cycle, can with concurrent access 1 ×, 2 × or 4 × 32bit data.Instruction to data store access is memory-register load instruction LOAD；Behaviour is write to data storage The instruction of work is register-memory write command STORE.
List as shown in Figure 1 in the present invention as the device and connection relation of support data storage Active Fault Tolerant.This The processor data memory Active Fault Tolerant device of invention, is set in processor core assembly line and core between data storage The circuit that data storage Active Fault Tolerant refreshes.Fault tolerance facility includes circuits below module：
LOAD instruction decoding receives programmed instruction, judge present instruction whether LOAD instruction, and export translating for LOAD instruction Code control logic is to data storage.STORE Instruction decodings receive programmed instruction, judge whether STORE is instructed for present instruction, And the encoded control logic of STORE instructions is exported to data storage.
Data error correction and detection module：The module receives N roads parallel input data N × 32bit data from data storage (111) and check code N × 8bit check codes 112 the error correction and detection function to reading in data, is completed；And export current N × circuit-switched data Correct and wrong Single_Error 101 and the number after wrong Multiple_Error102 status informations, error correction and detection can not be corrected According to information of check code 103.Wrong Single_Error states can be corrected be connected to can correct wrong status register, interrupt identification Register；Data connection after error correction and detection is to round-robin queue and destination register file；Check code after error correction and detection, which is connected to, to follow Ring queue.
Wrong status register can be corrected, preservation can correct wrong status information, and whether mark current processor can into data Correct wrong state.Wrong status register reception can be corrected and correct wrong status information from data error correction and detection module The wrong state of correcting of Single_Error and RSEC Instruction decoding modules removes control 105.When Single_Error is effective When, wrong status register set can be corrected；When can correct wrong state remove control signal it is effective when, wrong state can be corrected and posted Storage is reset；When Single_Error and can correct wrong state remove control signal it is effective at the same time when, Single_Error controls Signal has higher priority, can correct wrong status register and reset.It can correct before wrong mode bit is eliminated, continuously Multiple data can correct wrong event and pair can correct wrong status register and repeat set.
Circulate Record queues, including Record queues and quene state register.Circulation Record queues have two parts Input, Part I input working as in error correction and detection data and error correcting code and processor pipeline from data error correction and detection module The control information Core_Read_Control 106 of preceding memory read operation instruction, Part II input write behaviour from memory Make data, check code 107 and the control information Core_ of current storage write operation instruction of instruction detection module output Write_Control 108.If current pipeline detects that reading in data has repairable mistake, just that Part I is defeated Enter in information write-in circulation Record queues, and wrong status register and renewal quene state register can be corrected；It can entangle In the case of positive mistake status register set, if the write operation for having data storage in subsequent operation instruction is instructed, it is necessary to will Part II input write-in circulates in Record queues and renewal quene state register.The output of round-robin queue is connected to team Row access modules.
The control information Core_Read_Control of memory read operation instruction includes：Data access degree of parallelism Pon is read, Base address address ReadBaseAddr is read, word/byte mode BW, reads the effective Read_Valid of data manipulation；Memory writes behaviour Making the control information Core_Write_Control of instruction STORE includes：Data access degree of parallelism Pon is write, writes base address address WriteBaseAddr, word/byte mode BW, the effective Write_Valid of data writing operation.Circulate each single item of Record queues The content of record includes：Access degree of parallelism Pon, concurrent access base address Read/WriteBaseAddr, word/byte mode BW, Data or write back data after wrong correct, the check code of data can be corrected；
Circulation Record queues record the defeated of each moment by the mode of first in first out (FIFO, First In First Out) Enter record information and enter RecordkQueue.
Quene state register 113, the current state of mark queue.Whether overflow and whether handled including queue Tail of the queue.The depth number of queue should be greater than flowing water where the delay number+pipeline decoding section and data error correction and detection module of interrupt response Flowing water segment number between section.
STORE Instruction decodings, detect whether current decoding instruction is the instruction of data storage write operation, and will be to STORE The control information Core_Write_Control outputs of Instruction decoding and the data and check code of STORE, can correct wrong state In the case of register is effective, circulation Record queues are input to.
Queue accesses module：Output control 109 and circulation Record of the module input from RSEC Instruction decoding modules The output 114 of queue.Team's head is recorded Record by queue accesses module by from team's head access queue of circulation Record queues (head) export to memory write operation module.
Data storage write operation module：The module inputs the output Record (head) 110 from queue accesses module. Data storage write operation module is according to the base address BaseAddr in Record (head) records, access degree of parallelism Pon and word Save the control information of Mode B W, by the data in Record (head) records and error correcting code write corresponding data storage and In error correction and detection memory.
RSEC Instruction decoding modules：Data of the input of the module from dsp processor program storage can be corrected in mistake The RSEC instructions 115 of disconnected service routine, export as that can correct wrong removing state control signal 105 and queue accesses control signal 109。
In the present invention, using interrupt processing, the renewal of mistake can be corrected by the complete paired data memory of interrupt service routine Write back.Since the data record after mistake is corrected can be corrected in circulating in Record queues, increase in dsp processor instruction set One special instruction RSEC (Record access and Single Error Correction instruction) refers to Make, write back for continuously reading team head record Record (head), and according to the renewal of record information completion data storage. This example illustrates the RSEC instructions realized on dsp processor.
Wrong interrupt service routine can be corrected, the entrance specified by the interrupt vector table of processor interruption processing module enters. Data error correction and detection module to correct the highest that wrong state output Single_Error102 is connected to interrupt flag register excellent On first level interruption position；Interrupt flag register can correct data wrong status signal and be sampled and be recorded.When generation data When can correct wrong interruption and enable effective, processor can correct wrong interrupt processing entrance by the data in interrupt vector table, jump Wrong interrupt service routine can be corrected by going to.
According to the setting of above device, LOAD instruction and the STORE process flow instructed are extended, respectively such as Shown in attached drawing 2 and attached drawing 3.Specific method step is：
The process flow for reading data memory instructions LOAD is：
Step A-1：Instruction fetch；
Step A-2：Judge whether that LODA is instructed according to instruction operation code.It is LOAD instruction, handles rapid A-3；Otherwise, locate Manage step A-12；
Step A-3：LOAD instruction decodes；
Step A-4：Data storage is accessed, obtains data；
Step A-5：Data be sent into data error correction and detection module carry out error correction and detection and wrong Single_Error can be corrected, can not Mistake Multiple_Error is corrected to judge.
Step A-6：Whether generation can not correct wrong Multiple_Error.If so, go to step A-10 processing；Otherwise, turn Step A-7；
Step A-7：The data that data error correction and detection module is exported, by the destination register index write-in mesh of LOAD instruction Register group in；
Step A-8：Judge whether that generation can correct wrong Single_Error.If so, wrong register set can be corrected, Processing step A-9；Otherwise, A-11 is gone to step；
Step A-9：By on the data after the error correction of data error correction and detection module output, check code and LOAD instruction assembly line Memory access control information, be sequentially written in circulation Record queues；Go to step A-11；
Step A-10：Generation can not correct multi-bit error, and generation can not correct wrong interrupt signal.
Step A-11：Instruction execution terminates.
Step A-12：Other instruction processing.
After extension memory write instruction STORE process flow be：
Step B-1：Instruction fetch；
Step B-2：Judge whether that STORE is instructed according to instruction operation code.It is STORE instructions, handles rapid B- 3；Otherwise, Go to step B-9；
Step B-3：STORE Instruction decodings；From register group read operands；
Step B-4：Produce operand check code；
Step B-5：Judgement can currently correct wrong status register whether set.If so, processing step B-6；Otherwise, turn Step B-7；
Step B-6：By the memory access control information on operand data, operand check code and STORE instruction pipelines, It is sequentially written in circulation Record queues；
Step B-7：By operand data, operand check code write-in data storage；
Step B-8：Instruction execution terminates.
Step B-9：Other instruction processing.
The processor of present example supports 1 ×, 2 × or 4 × 32bit, tri- kinds of data concurrent access pattern.To data Check code generation and data check and error correction and detection, wrong and double false retrievals can be corrected survey and handled in units of 32 bit data words.Cause This, data error correction and detection module needs the parallel data error correction and detection logic in four tunnels.
The data error correction and detection logic of the present invention is implemented by following algorithm：Data message position is by 32 data bit
D=d32d31d20d29d28d27d26d25d24d23d22d21d20d19d18d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1
(di,{1≤i≤32}={ 0,1 })
With 8 bit check position P '=p '8p′7p′6p′5p′4p′3p′2p′1(p′i,{1≤i≤8}={ 0,1 }) composition.
The logic of check bit generation is in STORE instruction flows：
The logic of error correction and detection compares 8 bit check codes and 8 bit-errors flags in LOAD instruction flow, and generation can correct mistake Single_Error and wrong Multiple_Error status signals can not be corrected.
8 bit-errors flag P=p8p7p6p5p4p3p2p1(pi,{1≤i≤8}={ 0,1 }) generation logic be：
Wherein,For XOR operation；Order
Method according to P value error correction and detections is：
(1) if P=" 0000000 ", show that data and check code are error-free, Multiple_Error=false, Single_Error=false；
(2) if weight='0' and p8p7p6p5p4p3p2p1≠ " 0000000 ", shows data D or check code P' In have two there occurs mistake, Multiple_Error=true；Data or check code not error correction；
(3) if weight='1' and p8p7p6p5p4p3p2p1≠ " 0000000 ", shows data D or check code P' In have one there occurs mistake, Single_Error=true；The method of data bit error correction is by the method introduced in the content of the invention Carry out.
Processor of the present invention is maximum to support the access of 4 × degree of parallelism totally 128 data, since data by word are unit progress Error correction and detection so that processor can support 128 data by the long numeric data error correction and detection function that word is unit.On the other hand, The error correction and detection logic using 64 or 128 is avoided in the error correction and detection logic of the present invention.Because the error correction and detection of 64 and 128 Logic needs more check bit, and than the 32 error correction and detection logics of logic coded and decoded need the area of bigger, production The circuit delay of raw bigger.
By the synergistic mechanism of software and hardware, correctable error occurs in data (can such as correct mistake, be drawn by single-particle the present invention The mistake of correcting risen is the frequent fault in electronic device, and, correctable error, which refers to, can correct mistake in this example hereinafter) when, Refresh Data after error correction is returned by data storage by software configuration.In the present invention, sent out by circulating Record queue records Life can correct the data and control information of mistake, for the Refresh Data for occurring to correct mistake to be restored reservoir.Verify and send out in EDAC Life can be corrected and staggered the time, and no matter which group generation can correct mistake in multi-set parallel data, can all correct wrong status register and put Position, and the records such as the data after current correct and EDAC check codes are write in Record queues, in follow-up fault-tolerant processing The write-back of data storage is updated.Meanwhile it can be covered subsequently to the write operation of identical address in order to avoid wrong write-back can be corrected Generation, in DSP architecture, can be corrected the data of the write operation instruction after mistake and write control information being also sequentially recorded to by data In queue.Record into enqueue process as shown in Figure 5.Processor in Figure 5 includes 10 level production lines, including, PF, FE, DC, EX1~4, EDAC and EX6.Each section of assembly line, according to the flow of instruction, including different functional units.Wherein, It pair can correct wrong information record and EDAC stages in assembly line occur for write operation command information record.With following program example Illustrate to record the process into enqueue：
LOAD (2) * AR5, R4//and in the case where degree of parallelism is 2, two data that AR5 base address is directed toward 0x0000000084 and 0x0000000204 write-in two registers of R4 and R5
ADDI R4, R5R6//R4 are added with R5, write R6
The storage unit for STORE R6*AR5//be directed toward the contents of R6 registers write-in AR5
LDI 0x00000040R3//constant 0x00000040 write-ins R3
STORE R3*AR6//by R3 contents write-in AR6 be directed toward storage unit
In examples detailed above, if the content that LOAD instruction is read from memory is：0x0000000080, AC and The front portion 32 of 0x0000000004,4B. data is data bit, and rear portion 8 is check bit.Patrolled according to error correction and detection Volume, it can be determined that first data occurs that mistake, error bit d can be corrected3, the data after correction are 0x0000000084, AC； Second data occurs that mistake, error bit d can be corrected10, the data after correction are 0x0000000204,4B.This data access There occurs two mistakes, but all it is repairable mistake.Therefore error correction and detection module data can correct wrong status information Single_ Error=true.According to the access information of current LOAD instruction, it is necessary to by following information record into queue：
Data and verification 0x0000000084, AC；0x0000000204,4B
Read base address AR5
Degree of parallelism 2
Word/byte mode 1 (' 1 ' is word pattern；' 0 ' is byte mode)
R6 contents are stored in AR5 addresses by first STORE instruction.Because data, which occur, for LOAD instruction can correct mistake, cause The information record by STORE instructions is needed into enqueue：
Data and verification 0x0000000288,07；
Read base address AR5
Degree of parallelism 1
Word/byte mode 1
R3 contents are stored in AR6 addresses by Article 2 STORE instructions.Because data, which occur, for LOAD instruction can correct mistake, cause The information record by STORE instructions is needed into enqueue：
Data and verification 0x00000040,4C；
Read base address AR6
Degree of parallelism 1
Word/byte mode 1
The present invention corrects wrong data by what is detected in above procedure example, and data storage is returned by software refreshing. Because the information of " refreshing " data storage be stored in circulation Record queue hardwares in, it is necessary to set a special instruction- - RSEC is instructed, and for access queue, and data, error correcting code and the control information " decoding " that data are write back are sent into storage afterwards Device write operation module, completes the write-back of data.
RSEC instructions instruct for 32bit.One in processor cores structure can be regarded as due to the access entrance of queue Specified register, RSEC instruction encodings use register access command encoding formats, by accessing an idle register Address, realizes the coding to RSEC instructions, produces corresponding microoperation.The process flow of RSEC instructions is as shown in attached drawing 4.Tool Body step is：
Step C-1：Instruction fetch；
Step C-2：Judge whether that RESC is instructed according to instruction operation code.It is RESC instructions, handles rapid C-3；Otherwise, turn Step C-9；
Step C-3：RESC Instruction decodings, output a control signal to queue accesses module；
Step C-4：Queue accesses module reads a record Record (Head) from team's head of circulation Record queues；
Step C-5：The data and control information of Record (Head) is sent into memory write operation module；
Step C-6：By operand data, operand check code write-in data storage；
Step C-7：Removing can correct wrong marker register；
Step C-8：Instruction execution terminates.
Step C-9：Other instruction processing.
Process flow as shown in Figure 6, is the controlling party of processor data memory Active Fault Tolerant provided by the invention Method, comprises the following steps：
Step 1.DSP processors initialize, and wrong interrupt response can be corrected by opening.It can be corrected when data storage occurs in mistake When disconnected, wrong hardware interrupts can be corrected by dsp processor is responded；
Step 2. data store access instruction (LOAD) will access data from data storage.And according to LOAD The extension of instruction, verifies the error state of data.To different error states in LOAD instruction implementation procedure, hold Row data can correct it is wrong/wrong state processing can not be corrected；
Step 3. judges that current processor assembly line and down-stream instruction are held in the case where data occur and can correct mistake During row, if there is memory to write (STORE) instruction.Handled if so, continuing step 4；Otherwise, 5 processing are gone to step；
Step 4. performs STORE instructions, and according to the extended operation instructed to STORE, in the data for instructing STORE While writing memory, the control information of STORE instructions and data record are entered into circulation Record queues；
Step 5. processor response can correct wrong hardware interrupts.Data can correct wrong triggering processor hardware and interrupt, and enter Data can correct wrong interrupt service routine processing；
In step 6. interrupt service routine, the record in recursive call instruction RSEC instruction processing loops Record queues, Until sky is read in queue.Data update after correction is returned into data storage.And after can correcting and can correcting mistake, STORE instructions Memory writes Refresh Data and returns data storage；
Step 7. can correct wrong interrupt and return；
Step 8.DSP processor normal operations.
In embodiment, interrupt service routine example is devised：
In program example, cycle-index is set to queue depth, i.e. RSEC circulations perform number and fix.So may be used To avoid in interrupt service routine caused by scene protection data storage read-write operation.
The present invention provides a kind of dsp processor data storage Active Fault Tolerant apparatus and method, pass through software and hardware combining Processing, the data for occurring to correct mistake are refreshed into back data storage in time, can be controlled in more flexible method soft or hard The fault-tolerant strategy of part, to meet Reliability Index.

Claims (10)

1.DSP processor data memory Active Fault Tolerant devices, it is characterised in that its be arranged on dsp processor core assembly line and In core between data storage, refresh for data storage Active Fault Tolerant；Including the LOAD for loading data storage refers to Make decoding, the storage of the STORE Instruction decodings for writing data storage, queue accesses module, RSEC Instruction decodings module, data Device, data error correction and detection module, general register file, can correct wrong status register, circulation Record queues, data storage Device write operation module and the interruption processing module for hard break processing；
LOAD instruction decoding is used to receive dsp processor programmed instruction, judge current procedure instruction whether LOAD instruction, and export The encoded control logic of LOAD instruction is to data storage；
STORE Instruction decodings are used to receive dsp processor programmed instruction, judge whether STORE is instructed current procedure instruction, and defeated Go out the encoded control logic of STORE instructions successively through circulating Record queues, queue accesses module and data memory write operation Module is to data storage；
RSEC Instruction decodings module receives dsp processor programmed instruction, judges whether RSEC is instructed current procedure instruction, and export The encoded control logic of RSEC instructions is through queue accesses module to circulation Record queues；
The input of data error correction and detection module is the data and data check code of data storage output, is exported as current accessed data Error condition and repairable correct data and check code；
What register file was used to receiving the output of data error correction and detection module corrects data, after preserving data error correction and detection resume module LOAD instruction access data；
The error condition that wrong status register is used to connect data error correction and detection module samples current data can be corrected；
The write control signal of data storage write operation module output data memory；
The input of interruption processing module is the hardware interrupt request signal of dsp processor, and wrong interrupt can be corrected through data by, which exporting, takes Program of being engaged in connection RSEC Instruction decoding modules.
2. dsp processor data storage Active Fault Tolerant device according to claim 1, it is characterised in that the data Error correction and detection module, receives parallel input data and check code from data storage, completes the error correction and detection work(to reading in data Energy；And output can correct wrong Single_Error and can not correct the number after wrong Multiple_Error status informations, error correction and detection According to and information of check code；
Wrong Single_Error states can be corrected be connected to can correct wrong status register and interrupt flag register；After error correction and detection Data connection to circulating Record queues and destination register file；Check code after error correction and detection is connected to circulation Record teams Row；
Described to correct wrong status register, preservation can correct wrong status information, identify whether current dsp processor enters data Wrong state can be corrected；Wrong status register reception can be corrected and correct wrong status information from data error correction and detection module The wrong state of correcting of Single_Error and RSEC Instruction decoding modules removes control；
When Single_Error is effective, wrong status register set can be corrected；Control signal is removed when wrong state can be corrected When effective, wrong status register can be corrected and reset；When Single_Error has at the same time with that can correct wrong state removing control signal During effect, Single_Error control signals have higher priority, can correct wrong status register and reset；Wrong shape can be corrected Before state position is eliminated, continuous multiple data, which can correct wrong event pair, can correct wrong status register repetition set.
3. dsp processor data storage Active Fault Tolerant device according to claim 1, it is characterised in that the circulation Record queues include Record queues and quene state register；
Quene state register is used for the current state of mark queue, including whether queue overflows and whether handled team Tail；The depth number of circulation Record queues should be greater than the delay number of interrupt response, with pipeline decoding section and data error correction and detection mould The sum of flowing water segment number between flowing water section where block；
Circulation Record queues have two parts input, and Part I inputs the error correction and detection data from data error correction and detection module and entangles The control information Core_Read_Control of current LOAD instruction decoding in error code and dsp processor assembly line, Part II Input the control information Core_ of the data from the output of STORE Instruction decodings, check code and the instruction of current storage write operation Write_Control；
If data error correction and detection module detects that the data of current accessed have repairable mistake, Part I is just inputted into information Write in circulation Record queues, and wrong status information input can be corrected can to correct wrong status register and renewal quene state Register；
In the case where wrong status register set can be corrected, if having the operation that STORE is instructed in subsequent operation instruction, by the The input write-in of two parts circulates in Record queues and renewal quene state register；
Circulating the content of each single item record of Record queues includes accessing degree of parallelism Pon, concurrent access base address BaseAddr, Word/byte mode BW, can correct data or write back data and the check code of data after wrong correct；
The data storage write operation module is by the STORE data instructed and check code write back data memory, or incites somebody to action Data and check code renewal in Record records correct back data storage.
4. dsp processor data storage Active Fault Tolerant device according to claim 1, it is characterised in that the interruption One of hardware interrupt request connection current accessed data are corrected wrong state interrupt by processing module, and data are deposited Reservoir, which can correct wrong interrupt, has higher interrupt priority level；
The interruption processing module, including hardware Interrupt Process logic, interrupt flag register, interrupt enable register, interruption Vector table and hard break service routine area；
The hardware Interrupt Process logic, interrupts assembly line of the current dsp processor assembly line to normal executive program, and redirects To interrupt vector table, the entrance of hardware interrupts service routine is obtained；
The interrupt flag register and interrupt enable register coordinate hardware Interrupt Process logic to enter the service of interruption, work as interruption Enabled register pair data can correct it is wrong interrupt it is effectively enabled in the case of, the deposit of hardware Interrupt Process logic judgment interrupt flag Whether the data of device can correct wrong interrupt flag effective, and can correct wrong interrupt flag it is effective in the case of, make dsp processor It can be corrected in fault reason service routine into data；The wrong state output Single_Error that corrects of data error correction and detection module connects Being connected to the data of interrupt flag register can correct on wrong interruption position；Interrupt flag register can correct data in wrong state letter Number sampled and recorded；
The hard break service routine area, the entrance that the interrupt vector table handled by hard break is specified enter；Can when data occur When correcting wrong interruption and enabling effective, dsp processor can correct wrong interrupt processing entrance by the data in interrupt vector table, jump Wrong interrupt service routine can be corrected by going to data.
5. dsp processor data storage Active Fault Tolerant device according to claim 1, it is characterised in that the RSEC Instruction decoding module, accesses circulation Record one entry of queue, and entry is exported to data storage write operation mould The data preserved in Record entries and check bit are renewed back to data by data storage write operation module and stored by block Device.
6.DSP processor data memory Active Fault Tolerant methods, it is characterised in that comprise the following steps：
Step 1, dsp processor initializes, and wrong interrupt response can be corrected by opening；When generation data storage can correct wrong interrupt, Wrong hardware interrupts can be corrected by dsp processor is responded；
Step 2, data will be accessed from data storage according to LOAD instruction, and according to the extension to LOAD instruction, to data Error state verified；To different error states in LOAD instruction implementation procedure, perform data can correct it is wrong/can not Correct wrong state processing；
Data perform step 3 after can correcting fault reason；In the case where data occur and can not correct mistake, generation can not be corrected in mistake Break signal, dsp processor present instruction, which performs, to be terminated, and carries out other instruction processing；
Step 3, in the case where data occur and can correct mistake, judge that current processor assembly line and down-stream instruction performed Cheng Zhong, if having STORE instructions；Handled if so, continuing step 4；Otherwise, 5 processing are gone to step；
Step 4, STORE instructions are performed, and according to the extended operation instructed to STORE, are deposited in the data write-in for instructing STORE While reservoir, the control information of STORE instructions and data record are entered into circulation Record queues；
Step 5, processor response can correct wrong hardware interrupts；Data can correct wrong triggering processor hardware and interrupt, into data Wrong interrupt service routine processing can be corrected；
Step 6, in interrupt service routine, the record in recursive call instruction RSEC instruction processing loops Record queues, until Queue is read empty；And after wrong correct can be corrected, Refresh Data is write by the STORE memories instructed and returns data storage, completing will Wrong data update of correcting after correction returns data storage；
Step 7, wrong interrupt can be corrected to return；
Step 8, dsp processor normal operation.
7. dsp processor data storage Active Fault Tolerant method according to claim 6, it is characterised in that expand in step 2 The LOAD instruction processing method of exhibition includes,
Step A-1, dsp processor access instruction；
Step A-2, judges whether that LODA is instructed according to instruction operation code；It is LOAD instruction, handles rapid A-3；Otherwise, processing step A-12；
Step A-3, LOAD instruction decoding；
Step A-4, accesses data storage, obtains data；
Step A-5, data feeding data error correction and detection module progress error correction and detection, and progress can correct wrong Single_Error and can not Mistake Multiple_Error is corrected to judge；
Step A-6, if generation can not correct wrong Multiple_Error；If so, go to step A-10 processing；Otherwise, go to step A-7；
Step A-7, the data that data error correction and detection module is exported, by the destination register index write-in purpose deposit of LOAD instruction In device group；
Step A-8, judges whether that generation can correct wrong Single_Error；If so, wrong register set can be corrected, processing step Rapid A-9；Otherwise, A-11 is gone to step；
Step A-9, by the memory access on the data after the error correction of data error correction and detection module output, check code and LOAD instruction assembly line Control information, is sequentially written in circulation Record queues；Go to step A-11；
Step A-10, generation can not correct multi-bit error, and generation can not correct wrong interrupt signal；
Step A-11, dsp processor present instruction, which performs, to be terminated；
Step A-12, dsp processor carry out other instruction processing.
8. dsp processor data storage Active Fault Tolerant method according to claim 6, it is characterised in that expand in step 4 The processing method of STORE after exhibition includes：
Step B-1, dsp processor instruction fetch；
Step B-2, judges whether that STORE is instructed according to instruction operation code；It is STORE instructions, handles rapid B-3；Otherwise, go to step B-9；
Step B-3, STORE Instruction decoding；From register group read operands；
Step B-4, produces operand check code；
Step B-5, judgement can currently correct wrong status register whether set；If so, processing step B-6；Otherwise, B- is gone to step 7；
Step B-6, by the memory access control information on operand data, operand check code and STORE instruction pipelines, sequential write Enter to circulate Record queues；
Step B-7, data storage is write by operand data, operand check code；
Step B-8, dsp processor present instruction, which performs, to be terminated；
Step B-9, dsp processor carry out other instruction processing.
9. the dsp processor data storage Active Fault Tolerant method according to claim 7 or 8, it is characterised in that the step In rapid A-9 and step B-6, the method for circulation Record queue records is：
Step E-1, if Single_Error=true, the data after mistake and check code will be corrected by error correction method, together with Reading data base address, degree of parallelism and the word of this data storage/byte-accessed pattern write-in queue tail, go to step E-3；It is no Then, processing step E-2；
Step E-2, if can currently correct, wrong status register is effective, and memory write operation instructs STORE's to write data Operate that effective Write_Valid is effective, by data and the check code produced by coding method, together with writing for this data storage Data base address, degree of parallelism and word/byte-accessed Mode B W write-in queue tails, go to step E-3；Otherwise, E-3 is gone to step；
Whether step E-3, detection queue overflow, juxtaposition corresponding state position.
10. dsp processor data storage Active Fault Tolerant method according to claim 6, it is characterised in that
In step 6, when recursive call instructs the record in RSEC instruction processing loops Record queues, RESC is instructed from circulation A record is read in team's head of Record queues, the data in record are renewed back to data storage according to memory access control information Device；Wherein, the operating method of RESC instructions is：
Step C-1, instruction fetch；
Step C-2, judges whether that RESC is instructed according to instruction operation code；It is RESC instructions, handles rapid C-3；Otherwise, C- is gone to step 9；
Step C-3, RESC Instruction decoding, outputs a control signal to queue accesses module；
Step C-4, queue accesses module read a record Record (Head) from team's head of circulation Record queues；
Step C-5, send the data and control information of Record (Head) into data storage write operation module；
Step C-6, data storage is write by operand data, operand check code；
Step C-7, removing can correct wrong marker register；
Step C-8, instruction execution terminate；
Step C-9, other instruction processing.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108845832A (en) * 2018-05-29 2018-11-20 西安微电子技术研究所 A kind of assembly line subdividing device improving processor host frequency
CN109002322A (en) * 2018-06-26 2018-12-14 天津飞腾信息技术有限公司 Register distribution and method for releasing and component for execution unit module level verification
CN110647357A (en) * 2018-06-27 2020-01-03 展讯通信（上海）有限公司 Synchronous multithread processor
CN110727401A (en) * 2019-09-09 2020-01-24 无锡江南计算技术研究所 Memory access system
CN110870286A (en) * 2018-06-28 2020-03-06 华为技术有限公司 Fault tolerance processing method and device and server
CN111798917A (en) * 2020-06-30 2020-10-20 湘潭大学 Data processing method and device for dynamic test result of single event effect of memory
CN112230995A (en) * 2020-10-13 2021-01-15 广东省新一代通信与网络创新研究院 Instruction generation method and device and electronic equipment
CN113671924A (en) * 2021-10-25 2021-11-19 西安热工研究院有限公司 DCS real-time value setting method and system, equipment and storage medium

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8190973B2 (en) * 2007-12-21 2012-05-29 Arm Limited Apparatus and method for error correction of data values in a storage device
CN103139060A (en) * 2013-03-01 2013-06-05 哈尔滨工业大学 High-fault-tolerance controller area network (CAN) bus digital gateway based on double digital signal processors (DSPs)
UA83799U (en) * 2013-04-26 2013-09-25 Леонид Григорьевич Гулега Fault-tolerant hydroacoustic station
CN104239120A (en) * 2014-08-28 2014-12-24 华为技术有限公司 State information synchronization method, state information synchronization device and state information synchronization system for virtual machine
CN105511984A (en) * 2015-11-27 2016-04-20 中国航天科技集团公司第九研究院第七七一研究所 Processor fault-tolerant structure based on active link backup data, and method thereof
US20170160963A1 (en) * 2015-12-08 2017-06-08 Ultrata, Llc Object memory interfaces across shared links

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8190973B2 (en) * 2007-12-21 2012-05-29 Arm Limited Apparatus and method for error correction of data values in a storage device
CN103139060A (en) * 2013-03-01 2013-06-05 哈尔滨工业大学 High-fault-tolerance controller area network (CAN) bus digital gateway based on double digital signal processors (DSPs)
UA83799U (en) * 2013-04-26 2013-09-25 Леонид Григорьевич Гулега Fault-tolerant hydroacoustic station
CN104239120A (en) * 2014-08-28 2014-12-24 华为技术有限公司 State information synchronization method, state information synchronization device and state information synchronization system for virtual machine
CN105511984A (en) * 2015-11-27 2016-04-20 中国航天科技集团公司第九研究院第七七一研究所 Processor fault-tolerant structure based on active link backup data, and method thereof
US20170160963A1 (en) * 2015-12-08 2017-06-08 Ultrata, Llc Object memory interfaces across shared links

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
XIN WANG: "Sensorless direct torque control ofinduction motors with fault-", 《2017 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)》 *
汪金林、王友仁、张砦: "面向数字信号处理的自修复可重构阵列设计", 《电子测量与仪器学报》 *

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108845832A (en) * 2018-05-29 2018-11-20 西安微电子技术研究所 A kind of assembly line subdividing device improving processor host frequency
CN109002322A (en) * 2018-06-26 2018-12-14 天津飞腾信息技术有限公司 Register distribution and method for releasing and component for execution unit module level verification
CN110647357A (en) * 2018-06-27 2020-01-03 展讯通信（上海）有限公司 Synchronous multithread processor
CN110647357B (en) * 2018-06-27 2021-12-03 展讯通信（上海）有限公司 Synchronous multithread processor
CN110870286A (en) * 2018-06-28 2020-03-06 华为技术有限公司 Fault tolerance processing method and device and server
US11231983B2 (en) 2018-06-28 2022-01-25 Huawei Technologies Co., Ltd. Fault tolerance processing method, apparatus, and server
CN110870286B (en) * 2018-06-28 2021-07-09 华为技术有限公司 Fault tolerance processing method and device and server
CN110727401A (en) * 2019-09-09 2020-01-24 无锡江南计算技术研究所 Memory access system
CN110727401B (en) * 2019-09-09 2021-03-02 无锡江南计算技术研究所 Memory access system
CN111798917B (en) * 2020-06-30 2021-07-30 湘潭大学 Data processing method and device for dynamic test result of single event effect of memory
CN111798917A (en) * 2020-06-30 2020-10-20 湘潭大学 Data processing method and device for dynamic test result of single event effect of memory
CN112230995A (en) * 2020-10-13 2021-01-15 广东省新一代通信与网络创新研究院 Instruction generation method and device and electronic equipment
CN112230995B (en) * 2020-10-13 2024-04-09 广东省新一代通信与网络创新研究院 Instruction generation method and device and electronic equipment
CN113671924A (en) * 2021-10-25 2021-11-19 西安热工研究院有限公司 DCS real-time value setting method and system, equipment and storage medium
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