CN107977044B - DDS signal generator and linear interpolation method thereof - Google Patents
DDS signal generator and linear interpolation method thereof Download PDFInfo
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Abstract
The application relates to a DDS signal generator, comprising: the phase accumulator sends the accumulated frequency control word to the phase register, the phase register searches the first waveform data and the second waveform data in the first read-only memory and the second read-only memory according to the output phase value, the subtracter calculates the difference value between the second waveform data and the first waveform data and sends the difference value to the multiplier, the multiplier multiplies the difference value with the phase value in the phase register and shifts the result to the right to obtain a decimal value, and the adder adds the decimal value with the first waveform data to obtain waveform output data. The signal generator of the application effectively ensures the quality of the waveform under the condition of not increasing the cost and reducing the design difficulty of peripheral hardware, and ensures that the data output by waveform data in each clock cycle is changed.
Description
Technical Field
The application belongs to the field of signal generators, and particularly relates to a DDS signal generator and a linear interpolation method thereof.
Background
At present, the DDS signal generator is generated by adopting a most basic DDS mode, as shown in fig. 1, wherein a frequency control word freq_word is calculated by a peripheral processor according to the frequency required by a user, a phase accumulator 1 is used for accumulating the frequency control word freq_word, a phase register 2 is used for caching accumulated phase values, and a read-only memory (ROM) 3 stores waveform data which are digitized by the needed waveform data, generally periodic waveform data and waveform data of one period. The inquiry address of the read only memory 3 is the phase value of the high-cut bit of the phase register 2.
The data from the phase register 2 to the read only memory 3 is typically 10 to 16 bits due to resource limitations within the FPGA. If 14 bits of data are used, namely, if the depth of the ROM is 16K, if the required frequency is lower than Fsample/16384, the waveform data in the ROM can have a condition that one point is continuously read for a plurality of times; and under the condition of low demand frequency, the requirement on peripheral filtering is high, otherwise, the waveform can form stepped waveform output, so that the waveform can not meet the index demand. However, if the filter is used in the FPGA, a large amount of internal resources of the FPGA are occupied, and there is a certain requirement on the cost of the FPGA.
Disclosure of Invention
In view of the above problems, the present application is to provide a DDS signal generator and a linear interpolation method thereof, so as to solve the problem that in the prior art, when the required frequency is low, the waveform data can be continuously read for a plurality of times.
In order to achieve the above purpose, the present application adopts the following technical scheme:
the DDS signal generator of the present application includes: the phase accumulator sends the accumulated frequency control word to the phase register, the phase register searches the first waveform data and the second waveform data in the first read-only memory and the second read-only memory respectively according to the output phase value, the subtracter calculates the difference value between the second waveform data and the first waveform data and sends the difference value to the multiplier, the multiplier multiplies the difference value with the phase value in the phase register and shifts the result to the right to obtain a decimal value, and the adder adds the decimal value with the first waveform data to obtain waveform output data.
The DDS signal generator described above, preferably, further includes: the waveform output data is output after passing through the digital-to-analog converter and the filter.
In the DDS signal generator, preferably, the first rom and the second rom adopt dual-port rom of a hardware memory.
Preferably, the DDS signal generator includes a second rom having an address value greater than the first rom.
In the DDS signal generator, preferably, the address values of the first rom and the second rom are higher than the phase value.
The application relates to a linear interpolation method of a DDS signal generator, which comprises the following steps:
the phase accumulator sends the accumulated frequency control word to the phase register;
the phase register searches the first waveform data and the second waveform data in the first read-only memory and the second read-only memory respectively according to the output phase value;
calculating the difference value between the second waveform data and the first waveform data by a subtracter and sending the difference value to a multiplier;
multiplying the difference value by a phase value in the phase register by the multiplier and right-shifting the result to obtain a decimal value;
the decimal value is added to the first waveform data by an adder to obtain waveform output data.
The linear interpolation method of the DDS signal generator, preferably, the method further includes: intercepting high bits of the phase value to search first waveform data and second waveform data in the first read-only memory and the second read-only memory respectively; the high order of the phase value is the address value of the first read-only memory and the second read-only memory.
In the linear interpolation method of the DDS signal generator, preferably, the second rom is one greater than the first rom.
In the above DDS signal generator linear interpolation method, preferably, the multiplying the difference value by the phase value in the phase register by the multiplier further includes: the multiplier multiplies the difference value by a fractional portion of the phase value in the phase register.
In the linear interpolation method of the DDS signal generator, preferably, the difference between the second waveform data and the first waveform data is a signed difference.
The DDS signal generator and the linear interpolation method thereof mainly solve the problem that the waveform is discontinuous and trapezoidal output exists when the required frequency is low under the condition of saving resources, thereby reducing the design difficulty of a peripheral filter and improving the waveform quality.
Drawings
Fig. 1 is a schematic diagram of a prior art DDS signal generator;
fig. 2 is a schematic diagram of a DDS signal generator according to an embodiment of the present application;
fig. 3 is a flowchart of a linear interpolation method of a DDS signal generator according to an embodiment of the present application.
Detailed Description
The present application will be described in detail with reference to the accompanying drawings and examples.
An embodiment of the present application provides a DDS signal generator, as shown in fig. 2, including: the frequency control word accumulated by the phase accumulator 4 is sent to the phase register 5, the phase register 5 searches the first waveform data and the second waveform data in the first read-only memory 7 and the second read-only memory 8 according to the output phase value, the subtracter 9 calculates the difference value between the second waveform data and the first waveform data and sends the difference value to the multiplier 10, the multiplier 10 multiplies the difference value by the phase value in the phase register 5 and shifts the result to the right to obtain a decimal value, and the adder 11 adds the decimal value and the first waveform data to obtain waveform output data. Preferably, the DDS signal generator in the embodiment of the present application is implemented by an FPGA. In a specific embodiment, the phase value output by the phase register 5 takes 48 bits as an example, wherein the upper 14 bits of the phase value are address values of the first rom and the second rom, and are integer parts, so as to find the first waveform data and the second waveform data in the first rom 7 and the second rom 8 respectively; the lower 34 bits of the phase value are the phase data, in fractional parts. Wherein the values stored in the first read only memory 7 and the second read only memory 8 are the same value, and the storage depth is 16384 data. The first waveform data and the second waveform data are two adjacent waveform data values. The second waveform data in the second read only memory 8 is subtracted from the first waveform data in the first read only memory 7 by the subtractor 9 to obtain a difference value, and the difference value is signed data. The multiplier 10 receives the difference between the second waveform data and the first waveform data, multiplies the difference by the lower 34 bits of the phase value in the phase register 5, and right shifts the result to obtain a decimal value, which is the difference between the waveform values of the decimal part during phase accumulation. Specifically, in the present embodiment, the result of the multiplication is shifted to the right by 34 bits, i.e., divided by 34 to the power of 2. Preferably, the result of the multiplication is signed data. Finally, the adder 11 adds the fractional value to the first waveform data in the first read only memory 7 to obtain final waveform output data, which is also preferably signed.
The DDS signal generator provided by the embodiment of the application effectively ensures the quality of waveforms under the conditions of not increasing the cost and reducing the design difficulty of peripheral hardware of the FPGA, so that the data output by waveform data in each clock cycle are changed.
The DDS signal generator according to the embodiment of the present application preferably further includes: the waveform output data is output after passing through the digital-to-analog converter and the filter. The waveform is continuous and the harmonic component is less by the peripheral filter.
In the DDS signal generator according to the embodiment of the present application, preferably, the first rom and the second rom adopt dual-port rom of a hardware memory. Specifically, because the first read-only memory and the second read-only memory are realized by the FPGA, the first read-only memory and the second read-only memory can be simultaneously realized by generating a dual-port ROM through a hardware memory (BRAM) in the FPGA, so that BRAM resources in the FPGA can be saved.
In the DDS signal generator according to the embodiment of the present application, preferably, the second rom is one greater than the first rom. Specifically, the values stored in the first rom 7 and the second rom 8 are the same value, and the storage depths are 16384 pieces of data. Therefore, when the second read-only memory is larger than the first read-only memory address value, the first waveform data and the second waveform data are two adjacent waveform data.
In the DDS signal generator according to the embodiment of the present application, preferably, the address values of the first rom and the second rom are high bits of the phase value. Specifically, the upper bits of the phase value are used to store the address values of the read-only memory, so in the embodiment of the application, the addresses of the first read-only memory and the second read-only memory are searched by the upper 14 bits of the 48-bit phase value output by the phase register 5.
The application adopts the hardware memory (BRAM) to generate the ROM with double ports and the corresponding algorithm, thereby not increasing the peripheral cost and effectively solving the problem that the waveform has trapezium at low frequency.
The embodiment of the application also provides a linear interpolation method of the DDS signal generator, as shown in fig. 3, comprising the following steps:
step 301, the phase accumulator sends the accumulated frequency control word to the phase register;
step 302, searching the first waveform data and the second waveform data in the first read-only memory and the second read-only memory respectively according to the output phase value by the phase register;
step 303, calculating the difference between the second waveform data and the first waveform data by the subtracter and sending the difference to the multiplier;
step 304, multiplying the difference value by the phase value in the phase register by the multiplier and right-shifting the result to obtain a decimal value;
step 305, adding the decimal value and the first waveform data by an adder to obtain waveform output data.
Specifically, the phase value output by the phase register 5 takes 48 bits as an example, wherein the upper 14 bits of the phase value are address values of the first read-only memory and the second read-only memory, and are integer parts, so as to find the first waveform data and the second waveform data in the first read-only memory and the second read-only memory respectively; the lower 34 bits of the phase value are the phase data, in fractional parts. The first read-only memory and the second read-only memory store the same value, and the storage depth is 16384 data. The first waveform data and the second waveform data are two adjacent waveform data values. The second waveform data in the second read-only memory is subtracted from the first waveform data in the first read-only memory by a subtractor to obtain a difference value, and the difference value is signed data. The multiplier receives the difference value between the second waveform data and the first waveform data, multiplies the difference value by the lower 34 bits of the phase value in the phase register, and right shifts the result to obtain a decimal value, wherein the obtained decimal value is the difference value of the waveform value of the decimal part when the decimal part is accumulated in the phase. Specifically, in the present embodiment, the result of the multiplication is shifted to the right by 34 bits, i.e., divided by 34 to the power of 2. Preferably, the result of the multiplication is signed data. Finally, the adder adds the decimal value to the first waveform data in the first read-only memory to obtain final waveform output data, which is also preferably signed.
In the linear interpolation method of the DDS signal generator according to the embodiment of the present application, preferably, the difference between the second waveform data and the first waveform data is a signed difference.
In the linear interpolation method of the DDS signal generator according to the embodiment of the present application, preferably, the second rom is one larger than the first rom in address value. Therefore, when the second read-only memory is larger than the first read-only memory address value, the first waveform data and the second waveform data are two adjacent waveform data values.
In the linear interpolation method of the DDS signal generator according to the embodiment of the present application, preferably, the multiplying the difference value by the phase value in the phase register by the multiplier further includes: the multiplier multiplies the difference by the fractional part of the phase value in the phase register, i.e. the multiplier multiplies the signed difference of the second waveform data and the first waveform data, which is desired to be subtracted, by the low order bits in the phase register, which in the embodiment of the application is 34 bits.
In summary, the linear interpolation method and the signal generator according to the embodiments of the present application effectively ensure the quality of waveforms under the condition of reducing the design difficulty of peripheral hardware without increasing the cost, so that the data output by each clock cycle of waveform data is changed, and the advantages of continuous waveforms and few harmonic components are achieved through the peripheral filter.
The present application is not limited to the above-mentioned preferred embodiments, and any person who can obtain other various products under the teaching of the present application can make any changes in shape or structure, and all the technical solutions that are the same or similar to the present application fall within the scope of the present application.
Claims (8)
1. A DDS signal generator comprising: the phase accumulator sends the accumulated frequency control word to the phase register, the phase register searches first waveform data and second waveform data in the first read-only memory and the second read-only memory according to the output phase value, the subtracter calculates and obtains the difference value between the second waveform data and the first waveform data and sends the difference value to the multiplier, the multiplier multiplies the difference value with the phase value in the phase register and shifts the result to the right to obtain a decimal value, and the adder adds the decimal value with the first waveform data to obtain waveform output data;
the signal generator further comprises: the waveform output data is output after passing through the digital-to-analog converter and the filter;
the first read-only memory and the second read-only memory adopt dual-port read-only memories of a hardware memory.
2. The DDS signal generator of claim 1, wherein the second read-only memory is one greater than the first read-only memory address value.
3. A DDS signal generator according to claim 1 or 2, wherein the address values of the first and second read-only memories are high order bits of the phase value.
4. A method of linear interpolation of a DDS signal generator, the method comprising: the phase accumulator sends the accumulated frequency control word to the phase register;
the phase register searches the first waveform data and the second waveform data in the first read-only memory and the second read-only memory respectively according to the output phase value;
calculating the difference value between the second waveform data and the first waveform data by a subtracter and sending the difference value to a multiplier; multiplying the difference value by a phase value in the phase register by the multiplier and right-shifting the result to obtain a decimal value;
the decimal value is added to the first waveform data by an adder to obtain waveform output data.
5. The method of linear interpolation of a DDS signal generator of claim 4, further comprising: intercepting high bits of the phase value to search first waveform data and second waveform data in the first read-only memory and the second read-only memory respectively; the high order of the phase value is the address value of the first read-only memory and the second read-only memory.
6. The linear interpolation method of DDS signal generator of claim 5, wherein the second rom is one greater than the first rom address value.
7. The method of linear interpolation of a DDS signal generator of claim 4 wherein said multiplier multiplying said difference with a phase value in said phase register further comprises: the multiplier multiplies the difference value by a fractional portion of the phase value in the phase register.
8. The linear interpolation method of DDS signal generator of claim 4, wherein the difference between the second waveform data and the first waveform data is a signed difference.
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| CN109857188B (en) * | 2019-01-08 | 2020-06-23 | 优利德科技(中国)股份有限公司 | Pulse wave generation method, device and system based on DDS |
| CN109714048A (en) * | 2019-01-08 | 2019-05-03 | 优利德科技(中国)股份有限公司 | A kind of output method for the DDS circuit and phase that phase mode is variable |
| CN113281595A (en) * | 2021-05-19 | 2021-08-20 | 中航机载系统共性技术有限公司 | Airborne equipment testing device |
| CN114138051A (en) * | 2021-11-08 | 2022-03-04 | 西安电子科技大学 | Waveform generation method for electrochemical workstation |
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