CN107960010B - Printed circuit board and welding design thereof - Google Patents
Printed circuit board and welding design thereof Download PDFInfo
- Publication number
- CN107960010B CN107960010B CN201711091697.8A CN201711091697A CN107960010B CN 107960010 B CN107960010 B CN 107960010B CN 201711091697 A CN201711091697 A CN 201711091697A CN 107960010 B CN107960010 B CN 107960010B
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- Prior art keywords
- memory
- chip
- circuit board
- area
- printed circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10159—Memory
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention relates to a circuit board manufacturing technology, in particular to a welding design of a printed circuit board, which is applied to the printed circuit board; the chip comprises a system-on-chip welding area, a first memory welding area and a second memory welding area; the first transverse distance is arranged between the first memory welding area and the system-on-chip welding area; a second transverse distance is reserved between the second memory welding area and the system-on-chip welding area; wherein the first lateral distance is less than the second lateral distance; the system-on-chip welding area, the first storage welding area and the second storage welding area are respectively provided with a corresponding welding pad; the wiring area on the printed circuit board can be reduced and the electromagnetic interference between the system-on-chip and the memory is improved.
Description
Technical Field
The invention relates to a circuit board manufacturing technology, in particular to a printed circuit board and a welding design thereof.
Background
A Printed Circuit Board (PCB) is an important electronic component, is a support for an electronic component, and is a carrier for electrical connection of the electronic component.
Printed circuit boards have evolved from single-layer to double-sided, multi-layer, and flexible, and still remain the trend for each. Due to the continuous development towards high precision, high density and high reliability, the volume is continuously reduced, the cost is reduced, and the performance is improved, so that the printed board still keeps strong vitality in the development engineering of future electronic equipment.
In some integrated circuits, a configuration of two memories is often adopted, but the existing printed circuit board is affected by the process and often aligns the two memories so that the two memories are at the same lateral distance from the system-on-chip, but the aligned layout can cause the device to have higher electromagnetic interference.
Disclosure of Invention
In order to solve the problems, the invention provides a welding design of a printed circuit board, which is applied to the printed circuit board; the chip comprises a system-on-chip welding area, a first memory welding area and a second memory welding area;
the first memory bonding area and the system-on-chip bonding area have a first lateral distance therebetween;
the second memory bonding area and the system-on-chip bonding area have a second lateral distance therebetween;
wherein the first lateral distance is less than the second lateral distance; and corresponding bonding pads are arranged in the system-on-chip welding area, the first storage welding area and the second storage welding area.
In the above bonding design, a first longitudinal distance is provided between the first memory bonding area and the soc die bonding area;
the second memory bonding area and the system-on-chip bonding area have a second longitudinal distance therebetween;
the first longitudinal distance is less than the second longitudinal distance.
The above-mentioned welding design, wherein, still include:
and the address connecting line surrounds the system-on-chip welding area, the first memory welding area and the second memory welding area.
The weld design of above, wherein the address link comprises at least one chamfered corner.
The above-mentioned welding design, wherein, still include:
and the instruction connecting line surrounds the system-on-chip welding area, the first memory welding area and the second memory welding area.
A printed circuit board comprising a solder design as described in any one of the above, further comprising:
the system-on-chip is welded in the system-on-chip welding area;
a first memory soldered in the first memory pad region;
and the second memory is welded in the second memory welding area.
The printed circuit board, wherein the printed circuit board has a top layer and a bottom layer;
the system-on-chip, the first memory and the second memory are soldered on the top layer.
The printed circuit board described above, wherein the first memory is a double rate random access memory.
The printed circuit board described above, wherein the second memory is a double rate random access memory.
The printed circuit board, wherein the size of the printed circuit board is less than 20 × 15 cm.
Has the advantages that: the printed circuit board and the welding design thereof can reduce the wiring area on the printed circuit board and improve the electromagnetic interference between the system-on-chip and the memory.
Drawings
FIG. 1 is a diagram illustrating a soldering scheme for a printed circuit board according to an embodiment of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
Example one
In a preferred embodiment, as shown in fig. 1, a soldering design for a printed circuit board is provided, which can be applied to a printed circuit board; the system-on-chip bonding area comprises a system-on-chip bonding area 10, a first memory bonding area 20 and a second memory bonding area 30;
the first memory bonding area 20 has a first lateral distance from the SOC chip bonding area 10;
the second memory bonding area 30 has a second lateral distance from the SOC chip bonding area 10;
wherein the first lateral distance is less than the second lateral distance; the system-on-chip die bonding area 10, the first memory bonding area 20, and the second memory bonding area 30 each have a corresponding pad disposed therein.
In the above technical solution, the first lateral distance is smaller than the second lateral distance, that is, the first memory bonding area 20 is closer to the system-on-chip bonding area 10 than the second memory bonding area 30, and a connection loop between the first memory bonding area 20 and the system-on-chip bonding area 10 is shorter than a connection loop between the second memory bonding area 20 and the system-on-chip bonding area 10, so that the problem of electromagnetic interference is smaller, and meanwhile, the area of wiring is reduced, and a space is provided for a peripheral connection line; the first lateral distance may be a lateral distance between the first memory bonding area 20 and the center of the system-on-chip die bonding area 10, or a lateral distance between the first memory bonding area 20 and the edge of the same side of the system-on-chip die bonding area 10; similarly, the second lateral distance between the second memory bonding area 30 and the system-on-chip die bonding area 10 may also be the lateral distance between the center or the edge of the same side.
In a preferred embodiment, the first memory bonding area 20 is a first longitudinal distance from the SOC chip bonding area 10;
the second memory bonding area 30 has a second longitudinal distance from the SOC chip bonding area 10;
the first longitudinal distance is less than the second longitudinal distance.
In a preferred embodiment, the method further comprises the following steps:
the address wire encloses a system-on-chip die bonding area, a first memory bonding area 20, and a second memory bonding area 30.
In the above technical solution, the address connecting line includes at least one chamfered corner.
In a preferred embodiment, the method further comprises the following steps:
and the instruction connecting line surrounds the system-on-chip welding area 10, the first memory welding area 20 and the second memory welding area 30.
In the above technical solution, the command line may overlap the address line, thereby further reducing the area of the wiring.
Example two
In a preferred embodiment, there is also provided a printed circuit board, which may include any one of the above soldering designs, wherein the method further includes:
a system-on-chip soldered in the system-on-chip-soldering region 10;
a first memory soldered in the first memory soldering area 20;
a second memory is soldered in the second memory soldering area 30.
In a preferred embodiment, the printed circuit board has a top layer and a bottom layer;
the system-on-chip, the first memory and the second memory are welded on the top layer.
In a preferred embodiment, the first memory is a double rate random access memory, but this is only a preferred case and may be other types of memory devices or memory devices.
In a preferred embodiment the second memory is a double rate random access memory, but this is only a preferred case and may be other types of memory devices or memory devices.
In a preferred embodiment, the size of the printed circuit board can be less than 20 x 15cm, so that the printed circuit board can be adapted to a small-sized printed circuit board, and the application range is expanded.
In summary, the present invention provides a printed circuit board soldering design, which is applied to a printed circuit board; the chip comprises a system-on-chip welding area, a first memory welding area and a second memory welding area; the first transverse distance is arranged between the first memory welding area and the system-on-chip welding area; a second transverse distance is reserved between the second memory welding area and the system-on-chip welding area; wherein the first lateral distance is less than the second lateral distance; the system-on-chip welding area, the first storage welding area and the second storage welding area are respectively provided with a corresponding welding pad; the wiring area on the printed circuit board can be reduced and the electromagnetic interference between the system-on-chip and the memory is improved.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (9)
1. A printed circuit board welding design is applied to a printed circuit board; the system comprises a system-on-chip welding area, a first memory welding area and a second memory welding area;
the first memory bonding area and the system-on-chip bonding area have a first lateral distance therebetween;
the second memory bonding area and the system-on-chip bonding area have a second lateral distance therebetween;
wherein the first lateral distance is less than the second lateral distance; the system-on-chip welding area, the first storage welding area and the second storage welding area are respectively provided with a corresponding welding pad;
the first memory bonding area and the system-on-chip bonding area have a first longitudinal distance therebetween;
the second memory bonding area and the system-on-chip bonding area have a second longitudinal distance therebetween;
the first longitudinal distance is less than the second longitudinal distance.
2. The weld design of claim 1, further comprising:
and the address connecting line surrounds the system-on-chip welding area, the first memory welding area and the second memory welding area.
3. The weld design of claim 2, wherein the address link includes at least one chamfered corner.
4. The weld design of claim 1, further comprising:
and the instruction connecting line surrounds the system-on-chip welding area, the first memory welding area and the second memory welding area.
5. A printed circuit board comprising a solder design according to any of claims 1 to 4, further comprising:
the system-on-chip is welded in the system-on-chip welding area;
a first memory soldered in the first memory pad region;
and the second memory is welded in the second memory welding area.
6. The printed circuit board of claim 5, wherein the printed circuit board has a top layer and a bottom layer;
the system-on-chip, the first memory and the second memory are soldered on the top layer.
7. The printed circuit board of claim 5, wherein the first memory is a double rate random access memory.
8. The printed circuit board of claim 5, wherein the second memory is a double rate random access memory.
9. The printed circuit board of claim 5, wherein the printed circuit board has a size of less than 20 x 15 cm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711091697.8A CN107960010B (en) | 2017-11-08 | 2017-11-08 | Printed circuit board and welding design thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711091697.8A CN107960010B (en) | 2017-11-08 | 2017-11-08 | Printed circuit board and welding design thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107960010A CN107960010A (en) | 2018-04-24 |
| CN107960010B true CN107960010B (en) | 2020-08-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711091697.8A Active CN107960010B (en) | 2017-11-08 | 2017-11-08 | Printed circuit board and welding design thereof |
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| Country | Link |
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| CN (1) | CN107960010B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789816A (en) * | 1996-10-04 | 1998-08-04 | United Microelectronics Corporation | Multiple-chip integrated circuit package including a dummy chip |
| CN101754664A (en) * | 2008-12-12 | 2010-06-23 | 微盟电子(昆山)有限公司 | Method for suppressing electromagnetic wave radiation on printed circuit board |
| CN202172527U (en) * | 2011-08-04 | 2012-03-21 | 山东新北洋信息技术股份有限公司 | Printed circuit board |
| CN107172799A (en) * | 2017-04-10 | 2017-09-15 | 晶晨半导体(上海)有限公司 | A kind of method for the Electro-static Driven Comb ability for improving general-purpose storage chip cabling |
-
2017
- 2017-11-08 CN CN201711091697.8A patent/CN107960010B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789816A (en) * | 1996-10-04 | 1998-08-04 | United Microelectronics Corporation | Multiple-chip integrated circuit package including a dummy chip |
| CN101754664A (en) * | 2008-12-12 | 2010-06-23 | 微盟电子(昆山)有限公司 | Method for suppressing electromagnetic wave radiation on printed circuit board |
| CN202172527U (en) * | 2011-08-04 | 2012-03-21 | 山东新北洋信息技术股份有限公司 | Printed circuit board |
| CN107172799A (en) * | 2017-04-10 | 2017-09-15 | 晶晨半导体(上海)有限公司 | A kind of method for the Electro-static Driven Comb ability for improving general-purpose storage chip cabling |
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| Publication number | Publication date |
|---|---|
| CN107960010A (en) | 2018-04-24 |
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