CN107958679B

CN107958679B - Memory module and processing data buffer for memory module

Info

Publication number: CN107958679B
Application number: CN201710953332.5A
Authority: CN
Inventors: 吴成一; 金南昇; 孙永训; 金灿景; 宋镐永; 安廷镐; 黄祥俊
Original assignee: Samsung Electronics Co Ltd; SNU R&DB Foundation; Wisconsin Alumni Research Foundation
Current assignee: Samsung Electronics Co Ltd; SNU R&DB Foundation; Wisconsin Alumni Research Foundation
Priority date: 2016-10-14
Filing date: 2017-10-13
Publication date: 2023-05-23
Anticipated expiration: 2037-10-13
Also published as: CN107958679A

Abstract

Memory modules and process data buffers for memory modules are provided. The memory module includes a memory device, a command/address buffer device, and a process data buffer. The memory device includes: a memory cell array; a first set of input/output terminals, each terminal configured to receive a first command/address bit; a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffer is configured to output a first command/address bit to the first input/output terminal group. The processing data buffer is configured to output data bits and second command/address bits to the second input/output terminal set. The memory device is configured such that the first command/address bits, the second command/address bits, and the data bits are used to access the memory cell array.

Description

Memory module and processing data buffer for memory module

Technical Field

Example embodiments of the inventive concepts relate to semiconductor memory devices, and more particularly, to memory modules having a processor mode and memory systems including the same.

Background

In conventional computing system architectures, instructions (or programs) and data are stored in a memory device separate from the host processor from which the instructions and data should be transferred to the host processor to perform data processing on the data based on the instructions. Thus, although the processing speed of the host processor has increased, the data transfer rate between the memory device and the host processor can become a bottleneck for performance improvement, and thus the throughput of the computing system can be limited. To address this problem, in-memory Processing (PIM) devices have been developed in which the processor logic is tightly coupled to a memory unit. The PIM device may improve the data processing speed and the data transfer rate.

Disclosure of Invention

Some example embodiments provide a memory module that may conform to a memory module standard and may be implemented in an in-memory processing architecture without structural changes to the memory device.

Some example embodiments provide a memory system including the memory module.

In some embodiments, a memory module includes a memory device, a command/address buffer device, and a processing data buffer. The memory device includes an array of memory cells; a first set of input/output terminals, each terminal configured to receive a first command/address bit; a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffer is configured to output a first command/address bit to the first input/output terminal group. The processing data buffer is configured to output data bits and second command/address bits to the second input/output terminal set. The memory device is configured such that the first command/address bits, the second command/address bits, and the data bits are used to access the memory cell array.

In some embodiments, a memory module includes a plurality of memory devices, a command/address buffer device, and a plurality of processing data buffers. Each of the plurality of memory devices includes: a memory cell array; a first set of input/output terminals, each terminal configured to receive a first command/address bit; a second set of input/output terminals, each terminal configured to receive a data bit. The command/address buffer is configured to output a first command/address bit to the first input/output terminal group. Each of the plurality of processing data buffers is configured to switch between a data buffer that serves as a respective memory device and a processor that serves to perform processing operations on data received from the respective memory device.

In some embodiments, a process data buffer for a memory module includes: a data buffer section; a processor section; a selection circuit connected to the data buffer portion and the processor portion and configured to select between the data buffer portion and the processor portion; a plurality of first input/output lines connected between the selection circuit and the data buffer section; a plurality of second input/output lines connected between the selection circuit and the processor section; a first input/output terminal group connected to the data buffer section and for communicating with an outside of the process data buffer; and a second input/output terminal group connected to the selection circuit and configured to communicate with an outside of the process data buffer.

In some embodiments, a non-volatile dual in-line memory module (NVDIMM) formed on a module board includes: a plurality of DRAM memory devices, a plurality of nonvolatile memory devices connected to the plurality of DRAM memory devices, an NVDIMM controller, and a plurality of processing data buffers respectively connected to the plurality of DRAM memory devices. The plurality of DRAM memory devices each include: a memory cell array; a first set of input/output terminals, each terminal configured to receive a first command/address bit; and a second set of input/output terminals, each terminal configured to receive a first data bit. The plurality of non-volatile memory devices each include: a memory cell array; a third set of input/output terminals, each terminal configured to receive a second command/address bit; and a fourth set of input/output terminals, each terminal configured to receive a second data bit. The NVDIMM controller is configured to output a first command/address bit to the first input/output terminal set and configured to output a second command/address bit to the third input/output terminal set. Each of the plurality of processing data buffers is configured to switch between a data buffer that serves as its respective memory device and a processor that serves to perform processing operations on data received from its respective memory device.

In some embodiments, a method of performing near data processing includes: transmitting a processor mode enter command to the memory module indicating that the processing data buffer of the memory module is operating in the processor mode; and sending a processor mode exit command to the memory module indicating that the processing data buffer of the memory module is to end operating in the processor mode and to operate in the data buffer mode.

In some embodiments, a method of performing near data processing includes: receiving a first mode command at a processing data buffer of the memory module, the first mode command indicating that the processing data buffer is to operate in a processor mode; transmitting command and address information from the process data buffer to a memory device connected to the process data buffer when operating in the processor mode; receiving a second mode command at the processing data buffer, the second mode command indicating that the processing data buffer operates as a data buffer of the memory device; and transferring data from the process data buffer to the memory device when operating in the data buffer mode.

Drawings

Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Fig. 1A is a block diagram illustrating a memory module in a normal mode according to an example embodiment.

FIG. 1B is a block diagram illustrating a memory module in processor mode according to an example embodiment.

Fig. 2A is a diagram describing an example of notifying a plurality of processing apparatuses included in a memory module of entry and exit of a processor mode.

FIG. 2B is a diagram depicting another example of notifying a plurality of processing devices included in a memory module of entry and exit of a processor mode.

Fig. 3A is a diagram describing an example in which a plurality of processing apparatuses included in a memory module write operation state information into a processor state register.

Fig. 3B is a diagram describing an example in which the memory controller reads operation state information stored in the processor state register.

Fig. 4 is a block diagram showing an example of each memory device included in a memory module according to an example embodiment.

Fig. 5 is a block diagram illustrating another example of each memory device included in a memory module according to an example embodiment.

Fig. 6 is a timing diagram illustrating an example of signals transmitted via the data pins of the memory device of fig. 4.

Fig. 7 is a timing diagram illustrating an example of signals transmitted via the data pins of the memory device of fig. 5.

Fig. 8A is a block diagram showing an example of each processing apparatus included in a memory module according to an example embodiment.

Fig. 8B is a block diagram showing an example of each processing device included in a memory module according to other example embodiments.

Fig. 9 is a block diagram showing an example of a processor included in the processing apparatus of fig. 8A.

Fig. 10 is a block diagram showing another example of each processing device included in the memory module according to the example embodiment.

Fig. 11A is a diagram describing an example of data transmission in a normal mode including a memory module of the processing apparatus of fig. 10.

Fig. 11B is a diagram describing an example of data transmission in a processor mode including a memory module of the processing apparatus of fig. 10.

Fig. 12 is a block diagram illustrating a memory module in a processor mode according to an example embodiment.

Fig. 13 is a block diagram illustrating a memory module in a processor mode according to an example embodiment.

Fig. 14 is a timing diagram describing the operation of the memory module of fig. 13 according to an example embodiment.

Fig. 15 is a block diagram illustrating a memory module in a processor mode according to an example embodiment.

Fig. 16A is a block diagram illustrating a memory module in a normal mode according to an example embodiment.

Fig. 16B is a block diagram illustrating a memory module in a processor mode according to an example embodiment.

Fig. 17 is a block diagram illustrating a memory system according to an example embodiment.

Fig. 18 is a diagram describing an example of bit arrangement change performed in a memory system according to an example embodiment.

FIG. 19 is a block diagram illustrating a computing system including a host processor performing bit placement changes according to an example embodiment.

Fig. 20 is a block diagram illustrating a memory system including a bit reorderer that performs bit placement changes, according to an example embodiment.

Fig. 21 is a diagram illustrating a non-volatile dual inline memory module (NVDIMM) according to an example embodiment.

Detailed Description

The present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. These example embodiments are merely examples, many implementations and variations are possible and no details need be provided herein. It should also be emphasized that this disclosure provides details of alternative examples, but such listing of alternatives is not exhaustive. Moreover, any correspondence of details between the various examples should not be construed as requiring such details, and it is impractical to list every possible variation for each of the features described herein. In determining the requirements of the present invention, reference should be made to the language of the claims.

Although the various drawings illustrate variations of the exemplary embodiments and may be referred to using a language such as "in one embodiment," the drawings are not necessarily intended to be mutually exclusive. Rather, as will be seen from the context of the following specific embodiments, when the figures and their descriptions are considered as a whole, certain features depicted and described in different figures may be combined with other features in other figures to arrive at various embodiments.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless the context indicates otherwise, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, e.g., as a naming convention. Thus, a first element, component, region, layer or section discussed below in one section of the specification could be termed a second element, component, region, layer or section in other sections of the specification or in the claims without departing from the teachings of the present invention. In addition, in some cases, even if the terms "first", "second", etc. are not used in the specification to describe the terms, they may be referred to as "first" or "second" in the claims in order to distinguish different elements that are required to be protected from each other.

It will be understood that when an element is referred to as being "connected" or "coupled" to or "on" another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element or being "in contact" with "or" contacting "another element, there are no intervening elements present. Other words used to describe the relationship between elements (e.g., "between … …" and "directly between … …", "adjacent" and "directly adjacent", etc.) should be interpreted in a similar manner.

Terms such as "about" or "approximately" may reflect an amount, size, direction, or layout that varies only in a small relative manner and/or in a manner that does not significantly alter the operation, function, or structure of certain elements. For example, in particular, if the deviation described below maintains the same effect as that of the listed range, the range of "about 0.1 to about 1" may include a range such as 0% -5% deviation around about 0.1 and 0% to 5% deviation around 1.

As is conventional in the art disclosed, features and embodiments are described in terms of functional blocks, functional units, and/or functional modules and are shown in the figures. Those skilled in the art will appreciate that the blocks, units, and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wired connections, which may be formed using semiconductor-like manufacturing techniques and/or other manufacturing techniques. Where blocks, units, and/or modules are implemented by microprocessors or the like, they may be programmed with software (e.g., microcode) to perform the various functions recited herein, and may optionally be driven by firmware and/or software. Alternatively, each block, each unit, and/or each module may be implemented by dedicated hardware or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs other functions. Furthermore, each block, unit, and/or module of an embodiment may be physically separated into two or more interacting and discrete blocks, units, and/or modules without departing from the scope of the inventive concept. Furthermore, the blocks, units and/or modules of the embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.

Fig. 1A is a block diagram illustrating a memory module in a normal mode according to an example embodiment, and fig. 1B is a block diagram illustrating a memory module in a processor mode according to an example embodiment.

Referring to fig. 1A and 1B, the memory module 100 includes a plurality of memory devices 111 to 118 each having a command/address pin CAP and a data pin DQP, a command/address buffer device 130 connected to the command/address pins CAP of the memory devices 111 to 118, and a plurality of processing devices 151 to 158 each connected to the data pin DQP of a corresponding one of the memory devices 111 to 118. The command/address buffer 130 is connected to the memory controller via a command/address BUS ca_bus, and the processing devices 151 to 158 are connected to the memory controller via a data BUS dq_bus.

The command/address pin CAP may be generally referred to as an input/output terminal set, and the data pin DQP may be generally referred to as an input/output terminal set. In some embodiments, the different sets of input/output terminals may be referred to as a first set of input/output terminals, a second set of input/output terminals, or a third set of input/output terminals. These input/output terminals are used to transmit and/or receive signals between the memory devices 111 to 118 and devices external to the memory devices 111 to 118. The command/address input/output terminal CAP may be a first input/output terminal set configured to receive a first command/address bit (e.g., a command bit and/or an address bit), among other things. Thus, the command/address input/output terminal CAP may be connected to communicate command and/or address signals between circuitry in the command/address buffer device 130 and circuitry in the corresponding memory device for processing the command/address. The data input/output terminal DQP may be a second set of input/output terminals configured to receive, among other things, both data bits and second command/address bits. Thus, the data input/output terminal DQP can be connected to communicate both data and command/address signals between circuitry in the corresponding processing device and circuitry in the corresponding memory device. These features will be described further below.

In the normal mode, as illustrated in fig. 1A, the memory module 100 may write data DAT1 received from the memory controller into the memory devices 111 to 118 or may read data DAT1 from the memory devices 111 to 118 in response to command/address signals CMD/ADDR received from the memory controller.

For example, in the normal mode, the command/address buffer 130 may receive the command/address signal CMD/ADDR from the memory controller via the command/address BUS ca_bus, may buffer the received command/address signal CMD/ADDR, and may output and provide the same buffered command/address signal CMD/ADDR to the command/address pins CAP of the memory devices 111 to 118. By buffering the command/address signals CMD/ADDR, the command/address buffer device 130 may improve signal integrity of the command/address signals CMD/ADDR and may reduce loads experienced by the memory controller with respect to the command/address signals CMD/ADDR. The command/address buffer 130 may be referred to as a "Registered Clock Driver (RCD)", or simply as a command/address buffer. In some example embodiments, the command/address buffer 130 may be a registered clock driver that conforms to a memory module standard, such as a double data rate 4 load reduced dual inline memory module (DDR 4 LRDIMM) standard.

In the case where the command/address signal CMD/ADDR indicates a write command, the processing devices 151 to 158 (also referred to herein as processing data buffers) may receive data DAT1 (e.g., data bits) from the memory controller via the data BUS dq_bus, buffer the received data DAT1, and may output and provide the data DAT1 to the data pin DQP of the memory devices 111 to 118 to write the data DAT1 to the memory devices 111 to 118. Since the memory devices 111 to 118 receive the same command/address signal CMD/ADDR in the normal mode, the data DAT1 can be written at the same address or the same location of the respective memory devices 111 to 118. In certain embodiments, the processing devices (e.g., processing data buffers) 151-158 described herein may be semiconductor chips (e.g., die formed from a wafer) or semiconductor packages (e.g., one or more dies packaged on a package substrate and encapsulated by an encapsulant). Similarly, in some embodiments, the memory devices 111-118 described herein may be semiconductor chips or semiconductor packages.

In the case where the command/address signal CMD/ADDR indicates a read command, the processing devices 151 to 158 may receive the data DAT1 read from the memory devices 111 to 118 via the data pin DQP, may buffer the received data DAT1, and may provide the data DAT1 to the memory controller via the data BUS dq_bus. Since the memory devices 111 to 118 receive the same command/address signal CMD/ADDR in the normal mode, the data DAT1 at the same address or the same location of the respective memory devices 111 to 118 can be read at the same time, for example.

As described above, in the normal mode, the processing devices 151 to 158 can function as a data buffer for buffering the data DAT1 transferred between the memory controller and the memory devices 111 to 118. In some example embodiments, the processing devices 151 through 158 may function as data buffers that conform to a memory module standard (e.g., the DDR4LRDIMM standard). Because the processing devices 151 through 158 serve as data buffers, the signal integrity of the data DAT1 may be improved, and the load experienced by the memory controller with respect to the data DAT1 may be reduced.

Further, as described above, the memory module 100 according to the example embodiment may include the command/address buffer device 130 conforming to the memory module standard and the processing devices 151 to 158 serving as data buffers conforming to the memory module standard. Thus, the memory module 100 according to example embodiments may be connected to a memory channel conforming to a memory module standard, and may be used as a normal memory module (e.g., DDR4 LRDIMM) conforming to the memory module standard in a normal mode.

The memory module 100 may be instructed by the memory controller (e.g., via a command/address BUS CA_BUS as shown in FIG. 2A, via a data BUS DQ_BUS as shown in FIG. 2B, or via other control lines as further described below with reference to FIGS. 8A, 8B, and 13) to enter the processor mode, and may operate in the processor mode. In the processor mode, as shown in fig. 1B, the memory module 100 may perform data processing on the data DAT2 stored in the memory devices 111 to 118. For example, in the processor mode, each processing device (e.g., 151) may perform data processing on data DAT2 stored in a memory device (e.g., 111) directly connected to the corresponding processing device (e.g., 151). The data processing performed by the processing means 151 to 158 may be any data processing including arithmetic operations and/or logical operations. For example, the data processing may include graphic data processing, in-memory database data processing, real-time analysis data processing, and the like. The results of the data processing may be sent back to the memory controller, for example, via the data BUS dq_bus, or may be stored in the memory device. As described above, in certain embodiments, the set of input/output terminals (e.g., DQP pins) are configured to function as data terminals during a normal mode of operation of the memory module 100, such that the processing device or devices function as data buffers, and are configured to function as command and address terminals during a processor mode of operation of the memory module, such that the processing device or devices perform arithmetic and/or logical operations on data stored in the corresponding memory device or devices. In this way, the processing devices are each configured to switch between the data buffer serving as the respective memory device and the processor serving as the processor that performs the processing operation on the data received from the respective memory device. The normal operation mode may also be described herein as a data buffer mode.

Further, in the processor mode, the processing devices 151 through 158 may perform data processing in parallel, and the memory devices 111 through 118 may perform data read operations and/or data write operations independently of each other. For example, in the processor mode, the data DAT2 may be read or written at different addresses or at different relative locations of the memory devices 111 to 118. In order to access the data DAT2 located at different addresses of the memory devices 111 to 118, the plurality of processing devices 151 to 158 may generate a plurality of different command/address signals CMD/ADDR1 to CMD/ADDR8, respectively, and may provide the plurality of command/address signals CMD/ADDR1 to CMD/ADDR8 to the plurality of memory devices 111 to 118, respectively.

In the example embodiment shown in fig. 1B, each processing device (e.g., 151) may provide command/address signals (e.g., CMD/ADDR 1) generated by the processing device (e.g., 151) to a corresponding memory device (e.g., 111) connected to the processing device (e.g., 151) via data pin DQP of the memory device (e.g., 111). In some embodiments, the command/address signal (CMD/ADDR 1) may be generated by a processing device (e.g., 151), and the processing device (151) may be preprogrammed to generate certain command/address signals upon receiving the processor mode enter signal. For example, in one embodiment, the processor mode enter signal may be received from the memory controller directly to the processing device via the DQ_BUS (see further description with respect to FIG. 2B and FIG. 8A). In response, processing device 151 can enter a processor mode in which one or more preprogrammed command/address signals CMD/ADDR1 are transmitted to the corresponding memory device 111. Alternatively, the memory controller may transmit signals including both the processor mode enter command and the additional command/address signals, which the processing device 151 may then send to the corresponding memory device 111.

In another embodiment, as described further below with respect to fig. 2A, 8B and 13, a processor mode enter signal may be received from the memory controller at the command/address buffer 130 or with an additional command/address signal, which may then be forwarded/transferred directly from the command/address buffer 130 to the processing device 151, e.g., via a control BUS (bcom_bus). In some example embodiments, each processing device (e.g., 151) may transmit/receive data DAT2 or transmit command/address signals (e.g., CMD/ADDR 1) to a corresponding memory device (e.g., 111) via data pin DQP in a time-division manner (or time-multiplexed manner). For example, each processing device (e.g., 151) may use data pin DQP as a pin for transmitting command/address signals (e.g., CMD/ADDR 1) during one time period and may use data pin DQP as a pin for transmitting/receiving data DAT2 during another time period, both time periods being part of the processor mode. In other example embodiments, each processing device (e.g., 151) may transmit/receive data DAT2 or transmit command/address signals (e.g., CMD/ADDR 1) to a corresponding memory device (e.g., 111) via data pin DQP in a space division (or spatially multiplexed) manner. For example, each processing device (e.g., 151) may use a portion of the data pins DQP as pins for transmitting command/address signals (e.g., CMD/ADDR 1), and may use the remaining portion of the data pins DQP as pins for transmitting/receiving data DAT 2. This will be described in further detail later. Thus, during processor mode, both data and command/address signals may be sent between memory devices 111-118 and corresponding processing devices 151-158 as part of data processing operations performed by processing devices 151-158.

Thus, the processing data buffer (e.g., each of processing devices 151 through 158) as discussed above with respect to fig. 1A and 1B is configured to output both data bits and command/address bits to the input/output terminal set DQP of the corresponding memory device, and may also receive data bits from the corresponding memory device. In this way, each memory device is configured such that both the first command/address bits (e.g., received from the CAP pin during normal operation), the second command/address bits (e.g., received from the DQP pin during processor operation), and the data bits (e.g., received from the DQP pin in either operation) are used to access the memory cell array.

Unlike normal memory modules that interface with memory channels that conform to the memory module standard, conventional memory modules, including PIM (processing-in-memory) devices, interface to the memory channels in a point-to-point (P-to-P) manner. Thus, in order to increase the capacity of the data storage space in a computing system comprising conventional memory modules with PIM devices, not only the number of memory modules, but also the number of memory controllers and the number of memory channels should be increased. However, since the processing apparatuses 151 to 158 serve as data buffers conforming to the memory module standard, the memory module 100 according to the example embodiment may be connected to a memory channel conforming to the memory module standard and may serve as a normal memory module conforming to the memory module standard in the normal mode. Accordingly, in a computing system including the memory modules 100 according to example embodiments, the capacity of the data storage space can be easily increased by simply increasing the number of memory modules 100 connected to the memory channel.

Furthermore, conventional PIM devices are implemented by integrating the processor logic and memory on the same die or by stacking the processor logic die on a memory die. Thus, conventional PIM devices including processor logic suitable for a particular application cannot be applied to other applications, and thus are not suitable for mass production. However, the memory module 100 according to example embodiments may be implemented in an in-memory Processing (PIM) architecture, which may be referred to as a near-data-processing (NDP) architecture, without making structural changes to the memory devices 111-118 with respect to the layout of the memory module 100. Accordingly, the memory devices 111 to 118 and the memory module 100 can be widely used in various applications and can be mass-produced.

In addition, in the memory module 100 according to the example embodiment, the processing devices 151 to 158 may perform parallel data processing on the data DAT2 stored in the memory devices 111 to 118 directly connected to the processing devices 151 to 158, thereby improving the data processing speed and data throughput of the computing system including the memory module 100.

Although fig. 1A and 1B illustrate an example in which the memory module 100 includes eight memory devices 111 through 118, the memory module 100 may include any number of memory devices according to example embodiments. For example, the memory module 100 may include four to thirty-six memory devices. In an example embodiment of a computing system employing 64-bit data words, memory module 100 may include nine memory devices including eight memory devices 111-118 each storing 8-bit data words and one memory device storing 8-bit Error Correction Codes (ECCs).

Furthermore, in one embodiment, fig. 1A and 1B illustrate an example where the memory module 100 includes one memory rank (rank) having eight memory devices 111 through 118. However, according to an example embodiment, the memory module 100 may include any number of memory columns, e.g., up to four memory columns. In this case, each processing device (e.g., 151) may be directly connected to one to four memory devices (e.g., 111).

Each processing device (e.g., 151) and corresponding memory device (e.g., 111) may be implemented as a separate integrated circuit (e.g., a separate chip) or a separate package. Alternatively, in some example embodiments, each processing device (e.g., 151) and corresponding memory device (e.g., 111) may be implemented or integrated as a single integrated circuit (e.g., chip) or a single package (e.g., such that an external DQP pin receives signals for both the processing device and the memory device, separate channels within the chip or package transmitting signals between the processing device and the memory device).

Fig. 2A is a diagram describing an example of notifying a plurality of processing apparatuses included in a memory module of entering and exiting a processor mode, fig. 2B is a diagram describing another example of notifying a plurality of processing apparatuses included in a memory module of entering and exiting a processor mode, fig. 3A is a diagram describing an example of writing operation state information into a processor state register by a plurality of processing apparatuses included in a memory module, and fig. 3B is a diagram describing an example of a memory controller reading operation state information stored in a processor state register.

Referring to FIG. 2A, in some example embodiments, the memory module 100 may be instructed by the memory controller 105 to enter the processor mode via the command/address BUS CA_BUS. In one embodiment, the command/address BUS CA_BUS may be a BUS configured to transfer bits received from the memory controller to the command/address buffer 130. For example, memory controller 105 may transmit a processor mode enter command PMODE_ENTRY_CMD, which indicates ENTRY into processor mode, as command/address signals via command/address BUS CA_BUS. The command/address buffer means 130 may transmit the processor mode ENTRY signal spm_entry to the processing means 151 to 158 via the control BUS bcom_bus between the command/address buffer means 130 and the processing means 151 to 158 in response to the processor mode ENTRY command pmode_entry_cmd, and the processing means 151 to 158 may operate in the processor mode in response to the processor mode ENTRY signal spm_entry. An example of a control BUS bcom_bus can also be seen in fig. 13 for a memory module and fig. 8B for a processing device. In some example embodiments, the control BUS bcom_bus between the command/address buffer device 130 and the processing devices 151 through 158 may be a Buffer Communication (BCOM) BUS (e.g., having a bit width of 4 bits) for transmitting buffer control commands and status information. The BCOM bus (shown in fig. 2A but not shown in fig. 1A or 1B) may be directly connected to both the command/address buffer device 130 and the processing devices 151 to 158, and may be an additional bus with respect to both the command/address buffer device 130 and the processing devices 151 to 158 shown in fig. 1A and 1B (see, for example, fig. 13).

Referring to FIG. 2B, in other example embodiments, the memory module 100 may be instructed by the memory controller 105 to enter the processor mode via the data BUS DQ_BUS. In one embodiment, the data BUS DQ_BUS may be a BUS configured to transfer bits received from a memory controller to a processing data buffer or a plurality of processing data buffers. For example, memory controller 105 may transmit processor mode ENTRY data PMODE_ENTRY_DAT, which represents ENTRY into processor mode, as part of a processor mode ENTRY command via data BUS DQ_BUS. Processing devices 151 through 158 may operate in a processor mode in response to processor mode ENTRY data PMODE_ENTRY_DAT. Later, a subsequent mode command, such as a processor mode exit command, may be transferred from the memory controller 105 (in one example) to the processing devices 151-158 via the data BUS DQ_BUS. The processor mode exit command may instruct the processing devices 151 through 158 to stop operating as processing devices and reenter operation in the data buffer mode.

In yet another example embodiment, the memory module 100 may receive a processor mode entry signal from the memory controller 105 via a control line other than the line of the command/address BUS ca_bus and the line of the data BUS dq_bus, and may operate in the processor mode in response to the processor mode entry signal.

In some example embodiments, once the memory module 100 operates in the processor mode, the memory controller 105 may check an operational state of the memory module 100 (e.g., an operational state of the processing devices 151 through 158 included in the memory module 100).

As shown in fig. 3A, each of the memory devices 111 to 118 may include a processor state register 120 as one of the mode registers, and in the processor mode, each processing device (e.g., 151) may provide operating state information OSI to the processor state register 120 included in the corresponding memory device (e.g., 111). For example, to store the operating state information OSI in the processor state register 120, each processing device (e.g., 151) may transmit a command to cause the operating state information OSI to be written to the processor state register 120 as a command/address signal (e.g., CMD/ADDR1 in fig. 1B) to the corresponding memory device (e.g., 111).

As shown in fig. 3B, in the processor mode, the memory controller 105 may (e.g., periodically) receive the operating state information OSI of the processing devices 151 through 158. For example, in the processor mode, the memory devices 111 to 118 may receive a processor state READ command pst_read_cmd from the memory controller 105 via the command/address BUS ca_bus and the command/address buffer device 130, and may transmit the operation state information OSI stored in the processor state register 120 to the memory controller 105 via the processing devices 151 to 158 and the data BUS dq_bus in response to the processor state READ command pst_read_cmd. In some example embodiments, when the memory controller 105 receives the operation state information OSI, the processing devices 151 to 158 may stop performing data processing, and may function as a data buffer. Although fig. 3A and 3B show examples in which the operation state information OSI of the processing means 151 to 158 is stored in the processor state registers 120 of the memory means 111 to 118, in other example embodiments the processing means 151 to 158 may provide the operation state information OSI to the command/address buffer means 130 via the control BUS bcom_bus, and the command/address buffer means 130 may store the operation state information OSI of the processing means 151 to 158.

When the memory controller 105 determines that the processing devices 151 to 158 have completed data processing based on the received operation state information OSI, or when the memory controller 105 determines that the memory module 100 needs to operate in the normal mode, the memory controller 105 may instruct the memory module 100 to exit the processor mode. In some example embodiments, as shown in fig. 2A, the memory controller 105 may transmit a processor mode EXIT command pmode_exit_cmd via the command/address BUS ca_bus, the command/address buffer device 130 may transmit a processor mode EXIT signal spm_exit to the processing devices 151 to 158 via the control BUS bcom_bus in response to the processor mode EXIT command pmode_exit_cmd, and the processing devices 151 to 158 may operate in the normal mode in response to the processor mode EXIT signal spm_exit. In other example embodiments, as shown in fig. 2B, the memory controller 105 may transmit the processor mode EXIT data spm_exit_dat via the data BUS dq_bus, and the processing devices 151 through 158 may operate in the normal mode in response to the processor mode EXIT data spm_exit_dat. In yet another example embodiment, the memory module 100 may receive a processor mode exit signal from the memory controller 105 via a control line other than the line of the command/address BUS ca_bus and the line of the data BUS dq_bus, and may operate in the normal mode in response to the processor mode exit signal.

Referring to fig. 4, a memory device 111A (e.g., each of the memory devices 111 to 118 shown in fig. 1A and 1B) may include a command/address pin CAP (e.g., a first input/output terminal group), a command/address path 160 (also described as a channel or as a line) connecting the command/address pin CAP and a peripheral circuit 170, a data pin DQP (e.g., a second input/output terminal group), a data path 165 (also described as a channel or as a line) connecting the data pin DQP and the peripheral circuit 170, a memory cell array 180, and a path selection unit 190a.

The memory cell array 180 may include a plurality of memory cells storing data. In some example embodiments, the memory cells may be Dynamic Random Access Memory (DRAM) cells and the memory device 111a may be a DRAM device. In other example embodiments, the memory device 111a may be a volatile memory device such as a Static Random Access Memory (SRAM) device, a Thyristor Random Access Memory (TRAM) device, or a nonvolatile memory device such as a Ferroelectric Random Access Memory (FRAM) device, a Magnetoresistive Random Access Memory (MRAM) device, a phase change random access memory (PRAM) device, or the like. In response to the command/address signal CMD/ADDR received via the command/address path 160, the peripheral circuit 170 may write data DAT received via the data path 165 to the memory cell array 180, or may output data DAT read from the memory cell array 180 via the data path 165.

In the normal mode, the memory device 111A may receive the command/address signal CMD/ADDR from the command/address buffer device 130 in fig. 1A at the command/address pin CAP. The command/address signal CMD/ADDR may be transmitted to the command decoder 171 and the address register 173 included in the peripheral circuit 170 via the command/address path 160. The command decoder 171 may decode a command included in the command/address signal CMD/ADDR, and the peripheral circuit 170 may perform an operation corresponding to the decoded command.

In an example where the decoded command represents a data write command, the memory device 111A may receive data DAT from the processing device 151 in fig. 1A at data pin DQP. In the normal mode, the path selection unit 190a may connect the data pin DQP to the data path 165. Accordingly, the data DAT received at the data pin DQP can be transmitted via the data path 165 to a data input/output (I/O) buffer 175 included in the peripheral circuit 170. The peripheral circuit 170 may write the data DAT temporarily stored in the data I/O buffer 175 to the memory cells in the memory cell array 180 at the addresses stored in the address register 173.

In another example where the decoded command represents a data read command, the peripheral circuit 170 may read the data DAT from a memory cell in the memory cell array 180 located at an address stored in the address register 173, and may temporarily store the read data DAT in the data I/O buffer 175. Because the path selection unit 190a connects the data pin DQP to the data path 165 in the normal mode, the data DAT temporarily stored in the data I/O buffer 175 can be output to the processing device 151 via the data path 165 and the data pin DQP.

In the processor mode, the memory device 111a may receive the command/address signal CMD/ADDR1 from the processing device 151 in fig. 1B in a time division manner at the data pin DQP, or may transmit the data DAT to the processing device 151 in fig. 1B or receive the data DAT from the processing device 151 in fig. 1B. In processor mode, path selection unit 190a may selectively connect data pin DQP to either data path 165 or command/address path 160. In some example embodiments, the path selection unit 190a may be implemented using a multiplexer (demultiplexer) or other circuit having similar operations. Further, in some example embodiments, the path selection unit 190a may receive a selection signal from the processing device 151 in fig. 1B via any pin of the memory device 111a (e.g., any pin other than the command/address pin CAP and the data pin DQP) to control the selective connection.

For example, during a period of time, the memory device 111a may receive command/address signals CMD/ADDR1 from the processing device 151 in fig. 1B. During the time period described, path selection unit 190a may connect data pin DQP to command/address path 160. Accordingly, the command/address signal CMD/ADDR1 may be transmitted to the command decoder 171 and the address register 173 included in the peripheral circuit 170 via the command/address path 160. In some example embodiments, the memory device 111a may further include a command/address buffer 195a that temporarily stores command/address signals CMD/ADDR1. In an example, the number of data pins DQP may be less than the number of command/address pins CAP, and thus command/address signals CMD/ADDR1 may be received via data pins DQP for multiple clock cycles. The command/address buffer 195a may temporarily store the command/address signals CMD/ADDR1 for the plurality of clock cycles, and once the full command/address signals CMD/ADDR1 are stored in the command/address buffer 195a, the command/address buffer 195a may provide the command/address signals CMD/ADDR1 to the command/address path 160.

During another time period (e.g., a second time period that is still during the processor mode) after the time period, the path selection unit 190a may connect the data pin DQP to the data path 165. Accordingly, in the case where the command/address signal CMD/ADDR1 represents a data write command, the memory device 111a may store data DAT received from the processing device 151 in fig. 1B via the data pin DQP, the path selection unit 190a, and the data path 165. In the case where the command/address signal CMD/ADDR1 represents a data read command, the memory device 111a may output the stored data DAT to the processing device 151 in fig. 1B via the data path 165, the path selection unit 190a, and the data pin DQP.

As described above, using the path selection unit 190a that selectively connects the data pin DQP to the data path 165 or the command/address path 160, the memory device 111a may receive the command/address signal CMD/ADDR1 from the processing device 151 in fig. 1B via the data pin DQP in a time-sharing manner in the processor mode, or may transmit the data DAT to the processing device 151 in fig. 1B via the data pin DQP or receive the data DAT from the processing device 151 in fig. 1B via the data pin DQP. In this manner, the path selection unit 190a may be a selection circuit configured to select whether to send bits received at the second input/output terminal set (e.g., DQP pin) to the command decoder 171 and the address register 173 (e.g., via an internal command/address path) or to send bits received at the second input/output terminal set (e.g., DQP pin) to the data I/O buffer 175 (e.g., via an internal path).

Referring to fig. 5, in the memory device 111b, a line DQL1 connected to a portion of the data pins DQP can be selectively connected to the command/address path 160 or to the data path 165 through the path selection unit 190b, and a line DQL2 connected to the remaining portion of the data pins DQP can be connected to the data path 165 (or included in the data path 165). The path selection unit 190b may connect the line DQL1 connected to a portion of the data pins DQP to the data path 165 in the normal mode, and may connect the line DQL1 connected to the portion of the data pins DQP to the command/address path 160 in the processor mode. Thus, in the normal mode, the data pin DQP can be used as a pin for transmitting/receiving data DAT. In the processor mode, the data pin DQP may be divided into a pin for transmitting/receiving data DAT and a pin for receiving command/address signals CMD/ADDR1 in a space division manner. Memory device 111b may have a similar configuration and similar operation as memory device 111a of fig. 4, except that data pin DQP is used as a pin for data DAT and a pin for command/address signals CMD/ADDR1 in a space division manner. In some example embodiments, because the command/address signal CMD/ADDR1 is received in memory device 111b via a portion of the data pins DQP unlike memory device 111a of fig. 4 which receives command/address signal CMD/ADDR1 via all of the data pins DQP, memory device 111b may receive command/address signal CMD/ADDR1 for more clock cycles than memory device 111a of fig. 4. The command/address buffer 195b may store command/address signals CMD/ADDR1 for more clock cycles, and once full command/address signals CMD/ADDR1 are stored in the command/address buffer 195b, the command/address buffer 195b may provide command/address signals CMD/ADDR1 to the command/address path 160. Thus, the DQP pin in this embodiment may include a second group and a third group of input/output terminal groups of the memory device 111 b. The second group includes a pin group connected to the line DQL1, the pin group being configured to serve as a data terminal to cause the processing apparatus to operate as a data buffer during a normal operation mode of the memory module, and to serve as command and address terminals to cause the processing apparatus to perform arithmetic and/or logical operations on data stored in the memory apparatus 111b during a processor operation mode of the memory module. The third group includes a pin group connected to line DQL2, the pin group being connected to the data I/O buffer 175 and configured to serve as a data terminal both during the normal mode of operation and during the processor mode of operation.

Fig. 6 is a timing diagram illustrating an example of a signal transmitted via a data pin of the memory device of fig. 4, and fig. 7 is a timing diagram illustrating an example of a signal transmitted via a data pin of the memory device of fig. 5.

Referring to fig. 4 and 6, in processor mode, command/address signals CMD/ADDR1 (e.g., data read command RD) may be received as signals DQ [0:7] on data pins DQP. The memory device 111a may output the data DAT as signals DQ [0:7] on data pins DQP in response to the data read command RD. In an example, the memory device 111a may output the data DAT with a burst length (burst length) 8 (BL 8). In the example shown in fig. 6, the data pin DQP may not be used during a predetermined time TINT1 during which the data pin DQP transitions from the pin receiving the command/address signal CMD/ADDR1 to the pin transmitting/receiving the data DAT. Further, after a predetermined time TINT2 from the time that the data DAT is output as signals DQ [0:7] on data pin DQP, memory device 111a may receive the next command/address signal CMD/ADDR1 (e.g., RD) via data pin DQP.

Referring to fig. 5 and 7, command/address signals CMD/ADDR1 (e.g., data read command RD) may be received as signals DQ [0:3] on a portion of the data pins DQP. In the memory device 111b of fig. 5, in the processor mode, a part of the data pins DQP may be used as pins receiving only the command/address signals CMD/ADDR1, and the remaining part of the data pins DQP may be used as pins transmitting/receiving only the data DAT. Thus, the memory device 111b can output the data DAT of the signals DQ [4:7] on the data pins that are the remainder of the data pins DQP without waiting for the predetermined time TINT 1. However, because the memory device 111b of fig. 5 receives the command/address signal CMD/ADDR1 using a smaller number of data pins DQP than the memory device 111a of fig. 4, the time taken for the memory device 111b to receive the command/address signal CMD/ADDR1 may be longer than the time taken for the memory device 111a of fig. 4 to receive the command/address signal CMD/ADDR 1. Further, because the memory device 111b of fig. 5 uses a smaller number of data pins DQP to transmit/receive data DAT than the memory device 111a of fig. 4, the time taken for the memory device 111b to transmit/receive data DAT may be longer than the time taken for the memory device 111a of fig. 4 to transmit/receive data DAT. For example, four of the eight data pins DQP can be used to transmit/receive data DAT in the memory device 111 b. In this case, in order to output data DAT of the same size as data DAT output by the memory device 111a of fig. 4 with the burst length 8 (BL 8), the memory device 111b may output the data DAT with the burst length 16 (BL 16).

Fig. 8A is a block diagram illustrating an example of each processing apparatus included in the memory module according to an example embodiment, and fig. 9 is a block diagram illustrating an example of a processor included in the processing apparatus of fig. 8A.

Referring to fig. 8A, a processing device 151A (e.g., each of the processing devices 151 to 158 illustrated in fig. 1A and 1B) may include: a data buffer 210 buffering first data DAT1 transferred between a memory controller and a corresponding memory device, a processor 230 performing data processing on second data DAT2 stored in the memory device, and a control unit 250 (e.g., a control circuit) connecting the memory device with the data buffer 210 in a normal mode and the memory device with the processor 230 in a processor mode.

The control unit 250 may include a multiplexer (demultiplexer) 270 and control logic 290, wherein the multiplexer (demultiplexer) 270 selectively connects a data pin DQP of the memory device to the data buffer 210 or the processor 230, and the control logic 290 controls the multiplexer (demultiplexer) 270. In addition, control logic 290 may control the overall operation of processing device 151 a.

The data buffer 210 may be a data buffer compliant with a memory module standard (e.g., DDR4LRDIMM standard). The data buffer 210 may be connected to the data BUS dq_bus and may also be connected to the data pin DQP of the memory device through the control unit 250 in a normal mode. In the normal mode, the data buffer 210 may buffer the first data DAT1 transferred between the memory controller and the memory device. In some example embodiments, the data buffer 210 may include synchronization circuits, signal amplifiers, input/output circuits, and the like. The data buffer 210, also described as the data buffer portion of the processing device 151a, may store and transmit data such that the data received at the data buffer 210 is the same as the data transmitted from the data buffer 210. The normal mode or normal operation mode may also be described herein as a data buffer mode. During this mode, the data buffer 210 is operating on data passing between the data BUS DQ_BUS and the data pin DQP. The first data DAT1 may be internally transmitted within the processing device 151a between the data buffer 210 and the control unit 250 via a plurality of first input/output lines connected between a selection circuit (such as a multiplexer 270) and the data buffer part 210.

In processor mode, processor 230 may be connected to data pin DQP of the memory device through control unit 250. In processor mode, processor 230 may initially receive controller-generated commands (such as processor mode enter commands), for example, via command/address BUS CA_BUS, command/address buffer 130, and control BUS BCOM_BUS, or directly from a memory controller via DQ_BUS, data buffer 210, and multiplexer 270. In response, the processor 230 transmits the command/address signal CMD/ADDR1 (in a time division manner as shown in fig. 6 or in a space division manner as shown in fig. 7) to the data pin DQP, and can receive the second data DAT2 stored in the memory device via the data pin DQP. For example, the command/address signal CMD/ADDR1 may be based on a command from the memory controller, or may be generated in response to a command from the memory controller (such as a processor mode enter command). The processor 230 may perform any data processing including arithmetic operations and/or logical operations on the received second data DAT2. Further, the processor 230 may transmit a command/address signal CMD/ADDR1, may provide a result of the data processing as second data DAT2 to a data pin DQP to write the result of the data processing to the memory device, or may output the result via the dq_bus. According to an example embodiment, the processor 230 may be a Central Processing Unit (CPU), a microcontroller, a microprocessor, a hardware accelerator, or any data processing device.

In some example embodiments, as shown in fig. 9, the processor 230 may include an instruction buffer 231, a register file (file) 233, an Arithmetic Logic Unit (ALU) 235, a processor control unit 237, and an interconnect 239. The instruction buffer 231 may receive the instruction INST as the second data DAT2 from the data pin DQP of the memory device via the multiplexer (demultiplexer) 270, and may temporarily store the instruction INST. The instructions INST may be, for example, machine language code representing data processing performed by the processor 230. The register file 233 may receive the input data RDAT as the second data DAT2 from the data pin DQP of the memory device via the multiplexer (demultiplexer) 270 and may temporarily store the input data RDAT. The ALU 235 may perform an arithmetic operation or a logical operation corresponding to the instruction INST on the input data RDAT as a data process. The result of the arithmetic operation or the logical operation may be temporarily stored in the register file 233. The result of the arithmetic operation or logical operation temporarily stored in the register file 233 may be used as an input for the next arithmetic operation or the next logical operation, or may be supplied as write data WDAT to the data pin DQP of the memory device via the multiplexer 270. To perform these operations, the processor control unit 237 may control the ALU 235 and the register file 233 based on the instruction INST stored in the instruction buffer 231. In addition, the processor control unit 237 may generate a command/address signal CMD/ADDR1 to control the memory device, and may transmit the command/address signal CMD/ADDR1 to a data pin DQP of the memory device via the multiplexer 270. An interconnect 239 may provide a connection between the instruction buffer 231, the register file 233, the ALU 235, and the processor control unit 237. Although the configuration of the processor 230 is illustrated in fig. 9, the processor 230 according to the example embodiment is not limited to the configuration shown in fig. 9.

Fig. 10 is a block diagram showing another example of each processing apparatus included in a memory module according to an example embodiment, fig. 11A is a diagram describing an example of data transmission in a normal mode of the memory module including the processing apparatus of fig. 10, and fig. 11B is a diagram describing an example of data transmission in a processor mode of the memory module including the processing apparatus of fig. 10.

Referring to fig. 10, the processing device 151b may have a similar configuration and a similar operation as the processing device 151a of fig. 8A, except that the processing device 151b may further include a clock generator 240. In processor mode, clock generator 240 may generate fast clock signal FCLK and may provide fast clock signal FCLK to clock pin CKP of the memory device connected to processing device 151 b. In some example embodiments, the fast clock signal FCLK generated by the clock generator 240 in the processor mode may have a clock frequency higher than that of the clock signal (CLK in fig. 11A) provided from the memory controller in the normal mode.

Referring to fig. 11A, in the normal mode, the processing device 151b and the memory device 111 may receive the clock signal CLK from the memory controller 105 (via the command/address buffer device 130 in fig. 1A). Data transfer between the memory controller 105 and the processing device 151b (or the memory device 111) may be performed based on the clock signal CLK.

Referring to fig. 11B, in the processor mode, the processing device 151B may provide the fast clock signal FCLK to the memory device 111, and data transmission between the processing device 151B and the memory device 111 may be performed based on the fast clock signal FCLK. Although data transfer in the normal mode is performed via the data BUS dq_bus having a relatively long distance, data transfer in the processor mode may be performed via the short data connection SDC between the processing device 151b and the memory device 111. Thus, data transmission in processor mode may have better signaling conditions than data transmission in normal mode. Further, although the data BUS dq_bus is connected to a plurality of memory modules in a multi-drop connection (multi-drop), the short data connection SDC between the processing device 151b and the memory device 111 may be a point-to-point (P-to-P) connection. Thus, the signaling conditions for data transmission in processor mode may be much better than the signaling conditions for data transmission in normal mode. Therefore, even if the data transfer rate in the processor mode is higher than that in the normal mode, the data DAT2 and the command/address signals CMD/ADDR1 can be transferred accurately between the processing device 151b and the memory device 111. For example, the data transmission rate in the normal mode may be about 2.4Gb/s, while the data transmission rate in the processor mode may be about 3.2Gb/s.

Referring to fig. 12, the memory module 100a may have a similar configuration and a similar operation as the memory module 100 of fig. 1B, except that the command/address buffer device 130a includes a clock generator 135 that generates a fast clock signal FCLK in a processor mode. In the processor mode, the clock generator 135 of the command/address buffer device 130a may provide the fast clock signal FCLK to the plurality of memory devices 111 through 118 and the plurality of processing devices 151 through 158. In the processor mode, each of the processing devices 151 through 158 and the corresponding memory devices 111 through 118 may perform data transfer via the short data connection SDC based on the fast clock signal FCLK, thereby improving the data transfer rate and data processing speed of the memory module 100a in the processor mode.

Fig. 13 is a block diagram illustrating a memory module in a processor mode according to an example embodiment, and fig. 14 is a timing diagram describing an operation of the memory module of fig. 13.

Referring to fig. 13, the memory module 100B may have a similar configuration and a similar operation as the memory module 100 of fig. 1B, except that command/address signals CMD/ADDR1 to CMD/ADDR8 may be transmitted through the control BUS bcom_bus in the processor mode. In the processor mode, the plurality of processing devices 151 to 158 may generate a plurality of command/address signals CMD/ADDR1 to CMD/ADDR8, respectively, and may transmit the command/address signals CMD/ADDR1 to CMD/ADDR8 to the command/address buffer device 130 via the control BUS bcom_bus between the processing devices 151 to 158 and the command/address buffer device 130. In addition, commands (e.g., processor mode entry commands) initially received from the memory controller via the command/address BUS ca_bus and sent to the processing devices 151 to 158 via the control BUS bcom_bus may cause the command/address signals CMD/ADDR1 to CMD/ADDR8 to be initiated (initiated), or may cause the command/address signals CMD/ADDR1 to CMD/ADDR8 to be generated in response to the commands. The command/address buffer device 130 may provide command/address signals CMD/ADDR1 to CMD/ADDR8 received via the control BUS bcom_bus to the memory devices 111 to 118, respectively.

In some example embodiments, the command/address signals CMD/ADDR1 to CMD/ADDR8 may be transferred to the memory devices 111 to 118, respectively, in a time-sharing manner via the control BUS bcom_bus and the command/address buffer device 130. For example, as shown in fig. 14, the first to eighth processing devices 151 to 158 may sequentially transmit the first to eighth command/address signals C/A1 to C/A8. The first processing device 151 may transmit the first command/address signal C/A1 to the control BUS bcom_bus, and the command/address buffer device 130 may transmit the first command/address signal C/A1 to the first to eighth memory devices 111 to 118. In some example embodiments, the command/address buffer device 130 may transmit the first device Identifier (ID) to the first through eighth memory devices 111 through 118 together with the first command/address signal C/A1. The first memory device 111 may transmit/receive data DAT as signals DQ [0:7] @111 on the data pin DQP in response to the first command/address signal C/A1 and the first device ID. For example, the first device ID may be transmitted as part of a command signal, transmitted as a separate and pre-received signal, and/or may include signals transmitted on a separate line or set of lines of the memory module 100b for selecting a memory device. After a predetermined time TINT from the transmission of the first command/address signal C/A1, the second processing device 152 may transmit the second command/address signal C/A2 to the control BUS bcom_bus, and the command/address buffer device 130 may transmit the second command/address signal C/A2 and the second device ID indicating the second memory device 112 to the first to eighth memory devices 111 to 118. The second memory device 112 may transmit/receive data DAT as signals DQ [0:7] @112 on data pins DQP in response to the second command/address signal C/A2 and the second device ID. Similarly, the third to eighth processing devices 153 to 158 may sequentially output third to eighth command/address signals C/A8, and each of the third to eighth processing devices 158 may transmit/receive data DAT as signals DQ [0:7] @118 on the data pin DQP in response to the corresponding command/address signal C/A8.

Fig. 8B depicts an example of a processing device 151B, which may be one of the processing devices 151 through 158 of fig. 13.

Referring to fig. 8B, a processing device 151B (e.g., each of processing devices 151 to 158 shown in fig. 13) may include: a data buffer 210 buffering first data DAT1 transferred between a memory controller and a corresponding memory device, a processor 230 performing data processing on second data DAT2 stored in the memory device, and a control unit 250 (e.g., a control circuit) connecting the memory device with the data buffer 210 in a normal mode and the memory device with the processor 230 in a processor mode.

The control unit 250 may include a multiplexer (demultiplexer) 270 and control logic 290, wherein the multiplexer (demultiplexer) 270 selectively connects a data pin DQP of the memory device to the data buffer 210 or the processor 230, and the control logic 290 controls the multiplexer (demultiplexer) 270. In addition, control logic 290 may control the overall operation of processing device 151 b.

The data buffer 210 may be a data buffer compliant with a memory module standard (e.g., DDR4LRDIMM standard). The data buffer 210 may be connected to the data BUS dq_bus and may also be connected to the data pin DQP of the memory device through the control unit 250 in a normal mode. In the normal mode, the data buffer 210 may buffer the first data DAT1 transferred between the memory controller and the memory device. In some example embodiments, the data buffer 210 may include synchronization circuits, signal amplifiers, input/output circuits, and the like. The data buffer 210, also described as the data buffer portion of the processing device 151b, may store and transmit data such that the data received at the data buffer 210 is the same as the data transmitted from the data buffer 210. The normal mode or normal operation mode may also be described herein as a data buffer mode. During this mode, the data buffer 210 is operating on data passing between the data BUS DQ_BUS and the data pin DQP. The first data DAT1 may be internally transmitted within the processing device 151b between the data buffer 210 and the control unit 250 via a plurality of first input/output lines connected between a selection circuit (such as a multiplexer 270) and the data buffer part 210.

In processor mode, processor 230 may be connected to data pin DQP of the memory device through control unit 250. In processor mode, processor 230 may initially receive a processor mode enter command (e.g., from a memory controller), for example, via control BUS bcom_bus. The control BUS bcom_bus may be connected to an external connection terminal of the processing device 151b, which is connected to the processor 230 via an internal line. In the embodiment of FIG. 8B, the BCOM_BUS line is shown as being directly connected to processor 230. However, in another embodiment, the bcom_bus line may be connected between an external connection terminal of the processing device 151b and the multiplexer 270, and an external command may reach the processor 230 through the multiplexer 270.

In some embodiments, signals transmitted and/or received to and/or from the data pins DQP of the respective memory devices and signals transmitted and/or received to and/or from the data BUS dqs_bus may be communicated from or to the processing device via different input/output terminal groups of the processing device, which may be separate input/output terminal groups from the input/output terminal groups used by the control BUS bcom_bus. The processing device 151a of fig. 8A may have similar input/output terminals for DQP and dq_bus. Here, the input/output terminal group of the processing apparatus connected to the data BUS dqs_bus may be referred to as a first input/output terminal group, the input/output terminal group of the processing apparatus connected to the data pin DQP of the corresponding memory apparatus may be referred to as a second input/output terminal group, and the external connection terminal of the processing apparatus connected to the control BUS bcom_bus may be referred to as a third input/output terminal group.

In response to a processor mode enter command, the processor 230 transmits command/address signals CMD/ADDR1 back to the command/address buffer 130 via the control BUS BCOM_BUS (or other processors transmit command address signals CMD/ADDR2 through CMD/ADDR8 back to the command/address buffer 130 via the control BUS BCOM_BUS), the command/address buffer 130 then transmits the command to the appropriate memory device or devices.

In response to the command/address signals, the appropriate memory device may send data DAT2 to the processing device, e.g., via a DQP pin. The processor 230 may perform any data processing including arithmetic operations and/or logical operations on the received second data DAT 2. Further, the processor 230 may provide the result of the data processing to the data pin DQP as the second data DAT2 to write the result of the data processing to the memory device, or may output the result via the dq_bus. According to an example embodiment, the processor 230 may be a Central Processing Unit (CPU), a microcontroller, a microprocessor, a hardware accelerator, or any data processing device.

The second data DAT2 may be internally transmitted within the processing device 151b between the processor 230 and the control unit 250 via a plurality of second input/output lines connected between a selection circuit (such as a multiplexer 270) and the processor portion 230.

Referring to fig. 15, memory module 100c may have a similar configuration and similar operation as memory module 100 of fig. 1A and 1B (e.g., including similar ca_bus and dq_bus connections, not shown in fig. 15), except that memory module 100c may also include a bridging network 140 that provides connections between the plurality of processing devices 151 through 158. In processor mode, the bridge network 140 may provide a connection between one processing device and another processing device that may perform data processing on data stored in a memory device directly connected to the other processing device by using the bridge network 140. For example, in the processor mode, a first processing device 151 of the processing devices 151-158 may transmit command/address signals C/A representing data read commands to a second processing device 155 of the processing devices 151-158 via the bridge network 140, and the second processing device 155 may transmit the command/address signals C/A to the corresponding memory device 115. The memory device 115 may output data DAT3 in response to the command/address signal C/a, and the first processing device 151 may receive the data DAT3 output from the memory device 115 via the second processing device 155 and the bridge network 140. Accordingly, the first processing device 151 may receive the data DAT3 stored not only in the memory device 111 directly connected to the first processing device 151 but also in another memory device 115 other than the memory device 111 directly connected to the first processing device 151, and may perform data processing on the data DAT stored in the other memory device 115.

Fig. 16A is a block diagram illustrating a memory module in a normal mode according to an example embodiment, and fig. 16B is a block diagram illustrating a memory module in a processor mode according to an example embodiment.

Referring to fig. 16A and 16B, the memory module 100d may have a similar configuration and a similar operation as the memory module 100 of fig. 1A and 1B, except that the memory module 100d does not include the command/address buffer device 130 of fig. 1A and 1B. In the memory module 100d, the command/address pins CAP of the plurality of memory devices 111 to 118 may be directly connected to the command/address BUS ca_bus, and may receive command/address signals CMD/ADDR directly from the memory controller.

As further described in fig. 1A, 2A, 12, 13, 15, 16A, and 16B and as may be seen from the various embodiments described above, a memory module may include a set of memory module terminals that connect the memory module to an external device. The memory module terminals may be located on one edge of the memory module (e.g., the bottom as shown in the figures). The plurality of processing data buffers may be located between the memory module terminal set and the plurality of memory devices. In some embodiments, the command/address buffer device is located between a first subset of memory devices and a second subset of memory devices. In addition, the command/address buffer device may have the same number of memory devices on either side of the command/address buffer device (e.g., four memory devices as shown in the example embodiment).

Further, according to the various embodiments described above, a method of performing near data processing may be performed. The method may include: for example, a first mode command is received at a processing data buffer of a memory module, the first mode command indicating that the processing data buffer is to operate in a processor mode. The method may further comprise: transmitting command and address information from a process data buffer to a memory device coupled to the process data buffer while operating in a processor mode; and receiving a second mode command at the processing data buffer, the second mode command indicating that the processing data buffer operates as a data buffer of the memory device. The first mode command may be, for example, a host or controller generated command, such as a processor mode enter command, and the second mode command may be a host or controller generated command, such as a processor mode exit command. The command and address information transferred during the processor mode may include a memory device identifier. The method may further comprise: data is transferred from the process data buffer to the memory device while operating in the data buffer mode.

In some embodiments, when operating in the processor mode, the process data buffer may transfer command and address information to the memory device at a first time and may transfer data to the memory device at a second time that is subsequent to the first time. The clock speed for transferring data from the process data buffer to the memory device during the processor mode may be faster than the clock speed for transferring data from the process data buffer to the memory device during the data buffer mode.

In one embodiment, as described above, after completion of transferring command and address information from the process data buffer to the memory device, there is a delay before transferring data from the process data buffer to the memory device. During this delay, the selection circuit processing the data buffer may switch between selecting a command/address path for an input bit (incoming bit) and selecting a data path for the input bit.

In some embodiments, both data and command and address information are sent to the memory device through the same set of process data buffer output terminals. In other embodiments, data is sent to the memory device through a first set of processing data buffer output terminals and command and address information is sent to the memory device through a second set of processing data buffer output terminals.

Fig. 17 is a block diagram showing a memory system according to an example embodiment, and fig. 18 is a diagram describing an example of bit arrangement change performed in the memory system according to the example embodiment.

Referring to fig. 17, the memory system 300 may include at least one of

memory modules

340 and 360 having

processing devices

350 and 370 and a memory controller 320 controlling the

memory modules

340 and 360. The

memory modules

340 and 360 including the

processing devices

350 and 370 may be referred to as PIM (or NDP) memory modules, and may be the memory module 100 of fig. 1A and 1B, the memory module 100a of fig. 12, the memory module 100B of fig. 13, the memory module 100c of fig. 15, or the memory module 100d of fig. 16A and 16B. The

memory modules

340 and 360 may be connected to the memory controller 320 via a memory channel MCH including a command/address BUS CA_BUS and a data BUS DQ_BUS. Memory system 300 may be a memory system included in any computing system, such as a personal computer, server computer, workstation, laptop computer, mobile computer, digital television, and the like.

In some example embodiments, memory system 300 may also include a normal memory module 380 that is connected to the same memory channel MCH as

memory modules

340 and 360. The normal memory module 380 may include a data buffer 390 instead of the

processing devices

350 and 370. The normal memory module 380 may be a memory module that conforms to a memory module standard (e.g., the DDR4LRDIMM standard).

Because PIM (or NDP)

memory modules

340 and 360 of memory system 300 are connected to a memory channel MCH compliant with a memory module standard, the storage capacity of memory system 300 may be easily increased by increasing the number of

memory modules

340, 360, and 380 connected to the memory channel MCH. Further, in the memory system 300, the

processing devices

350 and 370 included in each of the

memory modules

340 and 360 may perform data processing in parallel, and thus the memory system 300 may have improved data processing performance. In addition, the data processing performance of the memory system 300 can be easily improved by increasing the number of

memory modules

340 and 360.

In some example embodiments, the memory controller 320 may provide data to each memory module (e.g., 340) on which a bit arrangement change (bit arrangement change) is performed in a normal mode so that each memory device included in the memory module 340 may store a full data word. FIG. 18 illustrates an example of a computing system using 64-bit data words and one cache line having a size of 64 bytes. In general, the memory controller 320 may write data to the memory modules based on the cache lines. For example, the memory controller 320 may transmit a data write command to the memory module 340, and may also transmit data to the memory module 340 including eight x 8 memory devices 341 through 348 with a burst length of 8. In the case where the memory controller 320 transfers the original data including the first to eighth data words W1 to W8 in one cache line without a bit arrangement change, the memory devices 341 to 348 may store different bytes of the first to eighth data words W1 to W8. For example, the first memory device 341 may store the first bytes W1B1 to W8B1 of the first to eighth data words W1 to W8. In this case, in the processor mode, the processing device connected to the first memory device 341 may not be able to read the full data word, which is a unit of data processing, from the first memory device 341. However, in the memory system 300 according to the example embodiment, the memory controller 320 may provide the data to which the bit arrangement change is performed to the memory module 340. In some example embodiments, the bit placement change may be performed based on the cache line. As shown in fig. 18, the bit arrangement change may be performed such that first bytes W1B1 to W8B1 of the first to eighth data words W1 to W8 may be first provided to the memory module 340, and then second bytes W1B2 to W8B2 to eighth bytes W1B8 to W8B8 may be sequentially provided to the memory module 340. In case the memory module 340 receives data for which the bit arrangement change is performed, the first to eighth memory devices 341 to 348 may store the first to eighth data words W1 to W8, respectively. Thus, in the processing mode, each processing device can read the full data word from the corresponding memory device 341 to 348, and can perform data processing on the full data word.

FIG. 19 is a block diagram illustrating a computing system including a host processor that performs bit placement changes.

Referring to fig. 19, a computing system 400 may include a host processor 410 and a memory system 300a. The host processor 410 may perform a bit placement change on the original data ori_dat by performing a bit shuffling (bit shuffling) operation 420 (as shown in fig. 18). In the normal mode, the memory controller 320 may provide the data shf_dat, on which the bit arrangement change is performed, to the memory module 340a via the memory channel MCH.

FIG. 20 is a block diagram illustrating a memory system including a bit reorderer that performs bit placement changes.

Referring to fig. 20, a memory controller 320b of a memory system 300b may include a bit reorderer 330. The bit reorderer 330 may perform a bit arrangement change on the original data ori_dat (as shown in fig. 18), and in the normal mode, the memory controller 320b may provide the data shf_dat, on which the bit arrangement change is performed, to the memory module 340b via the memory channel MCH.

The embodiments discussed herein may be applied to any memory module and any memory system including a memory module.

Fig. 21 depicts an example of a non-volatile dual in-line memory module (NVDIMM) according to an example embodiment.

As shown in fig. 21, one example of an NVDIMM includes a module board 2100, a plurality of Dynamic Random Access Memory (DRAM) memory devices 111-118, a plurality of non-volatile memory devices (NVM) 181-188 connected to the plurality of DRAM memory devices, an NVDIMM controller 130a, and a plurality of processing devices 151-158. Some elements shown in fig. 21 may be identical to those of other embodiments previously described, and thus, these details will be omitted for brevity. Furthermore, although fig. 21 depicts a system similar to that shown in fig. 1A and 1B, a nonvolatile dual in-line memory module may also be implemented by adding a nonvolatile memory device to the memory module depicted in fig. 12, 13, 15, 16A, and 16B.

Each DRAM may include a memory cell array, and may have a structure and operation such as that shown in fig. 4 or 5 as an example. For example, each DRAM may include a first input/output terminal group such as a CAP terminal. Each terminal may be configured to receive a first command/address bit, for example, from the controller 130 a. Each DRAM may also include a second set of input/output terminals (e.g., DQP terminals), each terminal configured to receive a first data bit. The plurality of nonvolatile memory devices 181 to 188 such as a flash memory device or an MRAM device may be connected to a plurality of DRAM memory devices. For example, each non-volatile memory device may include a memory cell array, a third set of input/output terminals (e.g., CAP) each configured to receive a second command/address bit (e.g., from the controller 130 a), and a fourth set of input/output terminals (e.g., DQP) each configured to receive a second data bit. For example, the fourth input/output terminal group may be connected to the data terminals of the respective DRAM devices. NVDIMM controller 130a may perform the functions of command/address buffer 130 described in the various embodiments above, and may also perform the functions of controlling access to non-volatile memory devices. For example, the controller 130a may be configured to output the first command/address bits to the first input/output terminal set and the second command/address bits to the third input/output terminal set, among other things. The plurality of processing data buffers 151 to 158 may be respectively connected to the plurality of DRAM memory devices, each configured to switch between a data buffer as its corresponding memory device and a processor as performing processing operations on data received from its corresponding memory device, as described above.

In some embodiments, a memory module terminal group connecting the memory module to an external device is located on one edge of the memory module, and a plurality of process data buffers 151 to 158 are located between the memory module terminal group and the plurality of DRAM memory devices 111 to 118.

The controller may be located between a first subset of DRAM memory devices (e.g., 111-114) and a second subset of DRAM memory devices (e.g., 115-118). For example, there may be an equal number of DRAM memory devices (e.g., four DRAM memory devices) on either side of the controller.

As shown in fig. 21, the plurality of DRAM memory devices 111 to 118 are respectively located between the plurality of process data buffers 151 to 158 and the plurality of nonvolatile memory devices 181 to 188.

The plurality of processing data buffers 151 through 158 may include a fifth input/output terminal set configured to transmit data bits and connected to respective ones of the plurality of memory module terminals for communication external to the NVDIMM. For example, one input/output terminal group may connect the process data buffers 151 to 158 to their respective DRAMs 111 to 118, and the other input/output terminal group may connect the process data buffers 151 to 158 to the data BUS dq_bus via the memory module terminal.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concepts. Accordingly, all such modifications are intended to be included within the scope of the present inventive concepts. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A memory module, the memory module comprising:

a memory device, comprising: a memory cell array; a first set of input/output terminals, each terminal configured to receive a first command/address bit; and a second set of input/output terminals, each terminal configured to receive a data bit and a second command/address bit;

a command/address buffer configured to output a first command/address bit to the first input/output terminal group; and

A process data buffer configured to output data bits and second command/address bits to the second input/output terminal group,

wherein the memory device is configured such that the first command/address bits, the second command/address bits, and the data bits are used to access the array of memory cells,

wherein the second input/output terminal set is configured to serve as a data terminal during a normal operation mode of the memory module such that the process data buffer serves as a data buffer, and

the second set of input/output terminals is configured to serve as command and address terminals during a processor mode of operation of the memory module such that the processing data buffer performs arithmetic and/or logical operations on data stored in the memory device.

2. The memory module of claim 1, wherein the memory device further comprises peripheral circuitry including a command decoder, an address register, and a data input/output buffer, and the memory device further comprises selection circuitry configured to select whether to send bits received at the second set of input/output terminals to the command decoder and the address register, or to send bits received at the second set of input/output terminals to the data input/output buffer.

3. The memory module of claim 1, further comprising a first bus configured to transmit bits received from the memory controller to the command/address buffer and a second bus configured to transmit bits received from the memory controller to the processing data buffer.

4. The memory module of claim 3, wherein the memory device further comprises a selection circuit configured to receive bits received via the second bus, and the selection circuit is configured to select whether the received bits are transmitted to peripheral circuitry of the memory cell array via the internal data path or via the internal command/address path.

5. The memory module of claim 1, further comprising a third set of input/output terminals of the memory device connected to the processing data buffer, the third set of input/output terminals configured to function as data terminals both during the normal mode of operation and during the processor mode of operation.

6. A memory module, the memory module comprising:

a plurality of memory devices, each memory device comprising: a memory cell array; a first set of input/output terminals, each terminal configured to receive a first command/address bit; and a second set of input/output terminals, each terminal configured to receive a data bit and a second command/address bit;

a plurality of processing data buffers each configured to switch between a data buffer serving as a respective memory device and a processor serving to perform processing operations on data received from the respective memory device,

wherein the second input/output terminal set is configured to function as a data terminal during a normal operation mode of the memory module such that at least one of the plurality of process data buffers functions as a data buffer, and

the second set of input/output terminals is configured to serve as command and address terminals during a processor mode of operation of the memory module such that at least one of the plurality of processing data buffers performs processing operations on data received from the respective memory device.

7. The memory module of claim 6, wherein the plurality of processing data buffers are each configured to function as a processor upon receiving a processor mode enter command from a device external to the memory module.

8. The memory module of claim 6, wherein the processing operation comprises at least one of an arithmetic operation and a logical operation.

9. The memory module of claim 8, wherein processing operations include graphics data processing, in-memory database data processing, or real-time analysis.

10. The memory module of claim 6, the memory module further comprising:

a bus connected between the command/address buffer and each of the plurality of process data buffers, the bus being used to transfer command and address information between the command/address buffer and each of the plurality of process data buffers.

11. The memory module of claim 10, wherein the bus is connected to a processor on each processing data buffer.

12. The memory module of claim 6, the memory module further comprising:

a memory module terminal group disposed on one edge of the memory module and for connecting the memory module to an external device,

wherein the plurality of processing data buffers are located between the memory module terminal set and the plurality of memory devices.

13. The memory module of claim 12, wherein,

the command/address buffer means is located between the first subset of memory means and the second subset of memory means.

14. The memory module of claim 13, wherein,

the command/address buffer has the same number of memory devices on either side of the command/address buffer.

15. The memory module of claim 6, wherein,

each of the process data buffers includes:

a third set of input/output terminals, each terminal configured to receive and transmit command bits;

a fourth set of input/output terminals, each terminal configured to receive data bits from and transmit data bits to a respective memory device;

a fifth set of input/output terminals configured to receive data bits from and transmit data bits to respective sets of memory module terminals for communication external to the memory module.

16. A process data buffer for a memory module, the process data buffer comprising:

a data buffer section;

a processor section;

a selection circuit connected to the data buffer portion and the processor portion and configured to select between the data buffer portion and the processor portion;

A plurality of first input/output lines connected between the selection circuit and the data buffer section;

a plurality of second input/output lines connected between the selection circuit and the processor section;

a first input/output terminal group connected to the data buffer section and for communicating with an outside of the process data buffer;

a second input/output terminal group connected to the selection circuit and adapted to communicate with an outside of the process data buffer,

wherein each terminal of the second input/output terminal group is configured to: the data bits are transmitted during a normal mode of operation of the memory module such that the data buffer portion of the processing data buffer functions as a data buffer and the command/address bits are transmitted during a processor mode of operation of the memory module such that the processor portion of the processing data buffer performs arithmetic and/or logical operations on data stored in the memory module.

17. The process data buffer of claim 16 wherein,

each terminal of the first input/output terminal set is configured to transmit a data bit.

18. The process data buffer of claim 17 wherein,

each of the plurality of first input/output lines is configured to transmit a data bit;

Each of the plurality of second input/output lines is configured to transmit data bits and command/address bits.

19. The process data buffer of claim 18, the process data buffer further comprising:

and a third set of input/output terminals, each terminal configured to transmit command/address bits and for communicating with the outside of the process data buffer.

20. A non-volatile dual in-line memory module formed on a module board, the non-volatile dual in-line memory module comprising:

a plurality of dynamic random access memory devices, each dynamic random access memory device comprising: a memory cell array; a first set of input/output terminals, each terminal configured to receive a first command/address bit; and a second set of input/output terminals, each terminal configured to receive a first data bit and a third command/address bit;

a plurality of nonvolatile memory devices coupled to the plurality of dynamic random access memory devices, each nonvolatile memory device comprising: a memory cell array; a third set of input/output terminals, each terminal configured to receive a second command/address bit; and a fourth set of input/output terminals, each terminal configured to receive a second data bit;

A nonvolatile dual in-line memory module controller configured to output first command/address bits to the first input/output terminal group and configured to output second command/address bits to the third input/output terminal group; and

a plurality of processing data buffers respectively coupled to the plurality of dynamic random access memory devices, each processing data buffer configured to switch between a data buffer functioning as its respective dynamic random access memory device and a processor functioning to perform processing operations on data received from its respective dynamic random access memory device,

wherein the second input/output terminal set is configured to function as a data terminal during a normal mode of operation of the non-volatile dual in-line memory module such that at least one of the plurality of processing data buffers functions as a data buffer, and

the second set of input/output terminals is configured to serve as command and address terminals during a processor mode of operation of the non-volatile dual in-line memory module such that at least one of the plurality of processing data buffers performs processing operations on data received from its respective dynamic random access memory device.

21. The non-volatile dual in-line memory module of claim 20, the non-volatile dual in-line memory module further comprising:

a memory module terminal group for connecting the memory module to an external device and located on one edge of the memory module,

wherein the plurality of processing data buffers are located between the plurality of dynamic random access memory devices and a memory module terminal set.

22. The non-volatile dual in-line memory module of claim 21, wherein,

the non-volatile dual in-line memory module controller is located between the first subset of dynamic random access memory devices and the second subset of dynamic random access memory devices.

23. The non-volatile dual in-line memory module of claim 22, wherein,

there are an equal number of dynamic random access memory devices on either side of the nonvolatile dual inline memory module controller.