CN101122887A - Flash-memory card for caching a hard disk drive with data-area toggling of pointers - Google Patents
Flash-memory card for caching a hard disk drive with data-area toggling of pointers Download PDFInfo
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Abstract
The invention discloses a flash memory buffer card used for buffering the data write-in the HD driver by the host computer, comprising: a flash memory array for distributing the flash memory physical block to the first and second data area with M blocks and an average read and write counter pool. A module M maps one input logic sector address to one entrance among M entrances. A RAM entrance memorizes a mapping to a physical block in the front background area of neither a first nor a second digital area. Pages of the physical block are read by a matching logic sector address. When another digital area becomes the front background area, the empty pages are written back to the hardware and are erased in the background area. A new physical block with a low average read-write counting is selected from the blocks in the new front background.
Description
Technical field
The present invention relates to a kind of hard disk non-volatile cache, be meant a kind of flash memory (flash-memory) cache controller that uses flash memory foreground and back-end data regional development and technology specifically.
Background technology
Hard disk is widely used in the electronic equipment that is used for the high capacity storage of PC, server, video cassette recorder and many other kinds at present.High capacity storage is commonly used to store lot of data, and the random-access memory (ram) that is copied to usually faster as dynamic RAM (DRAM) to use for processor.Because the DRAM of processor can read arbitrarily, and mass-memory unit reads according to piece, therefore the data that need read from mass-memory unit or write must be monoblocks, RAM then allows to read and write the word of independent byte or 4～8 bytes, and mass-memory unit then needs a sector or 512 bytes even manyly is read together or writes.
When mass-memory unit is used since sector search time of access by the disc physics rotating speed decision of disk, rather than movement of electrons speed, thus their speed compared with the speed of the main DRAM of processor slowly many.Mass data in the sector also can cause the time-delay of access in addition.Mass-memory unit such as hard disk can use buffer memory to improve performance.DRAM or static random-access reservoir (SRAM) can be stored the data that are about to be written in the hard disk, and the data of access recently can be stored in the RAM buffer memory, allow RAM buffer memory rather than slower hard disk to provide and read.
Flash memory (Flash Memory) also can replace hard disk to be used for mass-memory unit.Flash array still has access speed faster also by block access compared with the rotation medium such as hard disk.However, owing to flash chip also addresses rather than reads arbitrarily according to piece, so as if being used for buffer memory as DRAM/RAM and being not easy.
Owing to may cut off the power supply before data are replicated back hard disk, and data in buffer will be lost or be destroyed behind the cache invalidate, so under the situation of outage suddenly, DRAM and SRAM can use reserve battery to provide the enough energy to finish the process that writes back data.Flash memory or other nonvolatile memories just can be used to finish the function of metadata cache like this.
This just needs a kind of buffer memory that uses flash memory to use as hard disk or other rotation mass-memory unit of buffer memory, thereby need a kind of hard disk or other to rotate the flash cache controller of the data cached usefulness of mass-memory unit, and then need a kind of caching technology that distributes flash block to foreground and zone, backstage.
Summary of the invention
The invention provides the flash card that a kind of employing is stored in the data area switching pointer buffering hard disk drive of RAM question blank.
A kind of flash cache subsystem (flash-memory cache sub-system) comprising:
One by physical block address (physical-block address, be called for short PBA)) the flash memory physical block flash array of identification, each physical block comprises a plurality of pages or leaves, and each page comprises a data sector that only can write an arbitrary data before physical block is wiped; Wherein, data sector is piece addressing rather than randow addressing, and all bytes can not must be that unit is together by access individually with the piece with byte access in the data sector;
First data area is made of first physical block of flash memory in the flash array;
Second data area is made of second physical block of flash memory in the flash array;
Wherein, each page in first physical block and second physical block will be from the host data and logical sector address (the logical-sector address of main frame, be called for short LSA)) be stored in the data sector of this page, this logical sector address from main frame is the host address of host data;
Switching device shifter (toggle means), when need being stored in a physical block that does not completely have a blank page, host data is activated, be used for by having expired physical block write data sector from first to outside mass-memory unit and wipe this piece, first is expired physical block switched to the zone, backstage, and selected second empty physical block to receive host data;
Simultaneously, also be used for having expired physical block with second and having switched to the zone, backstage, and first physical block of having selected receives host data by having expired physical block write data sector to outside mass-memory unit and wipe this piece from second.
Described flash cache subsystem also comprises:
One volatibility question blank (volatile lookup table) has M inlet, and wherein, each inlet of M inlet can be stored a physical block address that is mapped to first physical block or second physical block;
One mould generator (modulo generator), reception is from the logical sector address of main frame, be used for logical sector address is carried out the remainder that can determine the selected inlet of volatibility question blank of operation generation of mould M, selected inlet is used to store a physical block address mapping (mapping), and a physical block address that is used to store by the host data of logical sector address identification is represented in this mapping;
Wherein, switching device shifter also is used for, and in the selected inlet of volatibility question blank, uses the physical block address mapping of physical block address mapping replacement first physical block of second physical block; With,
In the selected inlet of volatibility question blank, use the physical block address mapping of physical block address mapping replacement second physical block of first physical block;
The host data of host requests is stored in the data sector of first physical block that the physical block address mapping of selected inlet in the selected volatibility question blank of mould remainder (modulo remainder) by the host requests logical sector address selects or second physical block.
Described flash cache subsystem also comprises:
Average read-write counter pond (wear-leveling-counter pool) is made of physical block flash memory average read-write counter in the flash array;
Wherein, each page of physical block average read-write counter has a large amount of average read-write counters in the data sector of this page, comprise,
The average read-write counter of per first physical block, second physical block, each average read-write counter physical block, the degree of average read-write counter keeps track flash memory physical block loss.
Described flash cache subsystem also comprises:
Average read-write selector installation (wear-level selector means) is used for selecting the first empty physical block by first average read-write counter of checking first physical block;
Also be used for selecting the second empty physical block by second average read-write counter checking second physical block;
Wherein, the first average read-write counter and the second average read-write counter are the average read-write counter that is stored in current average read-write counter block in the average read-write counter pond.
Described flash cache subsystem also comprises:
Be stored in the historical counter (history counter) in each average read-write counter block, be used for representing the up-to-date average read-write counter block in average read-write counter pond, wherein, up-to-date average read-write counter block is current average read-write counter block.
Described flash cache subsystem also comprises:
Replacement device (replacement means), be used for working as all pages or leaves of current average read-write counter block with the average read-write count value, and physical block address is wiped free of and average read-write counter need be updated the time, in average read-write counter pond, use new current average read-write counter block to substitute current average read-write counter block, current thus average read-write counter block is replaced.
Described flash cache subsystem also comprises:
Read miss device (read-miss means), be used for being read by main frame when external data from outside mass-memory unit, and external data need be stored in one do not have blank page expire physical block the time, by reading miss activation switching device shifter, switch through reading miss activation in the zone thus.
Described average read-write selector installation also comprises:
First selecting arrangement (first select means), be used to the empty piece of the first average read-write counter select to have minimum average read-write count value the first empty physical block and
Second selecting arrangement (second select means) is used to the empty piece of the second average read-write counter to select the second empty physical block with minimum average read-write count value;
During outage, the described physical block address mapping that is stored in the volatibility question blank will be lost, and the data in the physical block of flash memory still are saved, thus,
It is selecteed that the empty piece of first and second data areas is based on the minimum average read-write count value of sky piece.
Described flash cache subsystem also comprises:
The PCIE interface of a corresponding PCIE bus, the host requests that has LSA and host data receives by the PCIE bus;
Wherein, outside mass-memory unit is the rotating disk that is connected to the PCIE bus by IDE bus or SATA bus through an I/O processor;
Wherein, the host requests of outside mass-memory unit on IDE or the SATA bus is tackled by the PCIE interface of flash cache subsystem, thus, outside mass-memory unit is connected on another bus.
Described flash cache subsystem also comprises:
The USB interface of one corresponding usb bus, the host requests that has LSA and host data is to receive by usb bus;
Wherein, outside mass-memory unit is the rotating disk that is connected to usb bus by IDE bus or SATA bus through an I/O processor;
Wherein, the host requests of outside mass-memory unit on IDE or the SATA bus is tackled by the USB interface of flash cache subsystem.
Described flash cache subsystem also comprises:
One external address comparer (external address comparator), be used for the address realm of outside mass-memory unit on comparison IDE or the SATA bus and the address of PCIE bus, wherein, flash cache subsystem interception is to the host requests of outside mass-memory unit, come buffer memory from or be written to outside mass-memory unit data.
Described flash cache subsystem wherein, by first data area that the first flash memory physical block in the flash array constitutes, comprises M first physical block,
Wherein,, comprise M second physical block by second data area that the second flash memory physical block in the flash array constitutes, thus,
Some inlets mate some first physical blocks in the volatibility question blank, also mate some second physical blocks.
A kind ofly be used for adopting the volatibility question blank, comprise from the data cached method of the rotating disk of non-volatile flash memory:
Interception has the host requests of corresponding stored logical sector address of host data in rotating disk;
The remainder of inquiry host logic sevtor address mould M, wherein, the volatibility question blank has M inlet;
Remainder by mould M is selected a selected inlet in the volatibility question blank;
In non-volatile flash memory, read the selected physical block address of selected physical block by selected inlet;
Come query page coupling (page-match) by the logical sector address that reads in each page storage, relatively this logical sector address and host logic sevtor address, but show in the significance bit of this page and logical sector address time spent of storage to send a page or leaf matched signal;
From have selected physical block address produce the page or leaf coupling deposit reading of data sector in the logical sector address, and data sector is sent to main frame, when host requests is read request, forbid rotating disk is carried out access;
When not having page matched signal, activate rotating disk and will read to coil data and return to main frame, and will read to coil data and from rotating disk, be written in the non-volatile flash memory; With,
When host requests is write request, blank page of inquiry and host data write in this blank page in selected physical block address perhaps, when host requests is a read request and when not having the page or leaf coupling, will be read to coil data and be written to this blank page from rotating disk;
When not finding blank page in the selected physical block, activate a toggle path (toggle routine), the data sector of storing in the selected physical block page or leaf is copied to rotating disk, and wipe selected physical block, and select the physical block of a new band blank page, write the host data of autorotation disk or read to coil data, thus
When selecting a new selected physical block by toggle path, the data area is switched and is taken place.
Described toggle path also comprises:
When host requests is write request, in the blank page of new selected physical block, write host data; Perhaps, when host requests is read request and does not have when coupling page or leaf, data are written to the blank page of new selected physical block from rotating disk; With
The physical block of non-volatile flash memory is divided into first data area and second data area;
When the selected physical block of no blank page is present in first data area, wherein, toggle path will be selected a new selected physical block in second data area; When the selected physical block of no blank page was present in second data area, wherein, toggle path will be selected a new selected physical block in first data area;
Thus, when new selected physical block was switched the path and chooses, two data zones were switched.
Described method also comprises:
When toggle path was activated, the new selected inlet that is used for storing the new selected physical block address of the new selected physical block of non-volatile flash memory covered original selected inlet in the volatibility question blank, thus,
Selected inlet is realized replacing by toggle path in the volatibility question blank.
Described method also comprises:
When selected physical block is wiped free of, upgrade the average read-write counter of this selected physical block;
Inquire about and compare the average read-write counter of the empty physical block in first or second data area, find out a new selected physical block, thus,
The average read-write counter assists to select new selected physical block.
Described method also comprises:
By reading, increase the historical counter of selected physical block, upgrade the historical counter of new selected physical block, thus, when toggle path is activated, historical counter can be updated.
Described method also comprises:
When selected physical block is wiped free of, activate more new route of average read-write counter, comprising:
By reading and compare the history counting of counting implements reason piece in the physical block average read-write counter pond of non-volatile flash memory, find the historical counter of a recent renewal; Wherein, current counter physical block has up-to-date historical counter in the average read-write counter pond;
When selected average read-write counter never is written into, increase the selected average read-write counter of selected physical block.
In current counter physical block, seek the counter page or leaf (counter page) of a sky, average read-write counter last counter page or leaf from current counter physical block is duplicated the counter page or leaf of a sky, and increase selected average read-write counter, selected average read-write counter is write in the empty counter page or leaf;
When in current counter physical block, not having empty counter page or leaf, by checking the average read-write counter of current counter physical block in the average read-write counter pond, in average read-write counter pond, seek new current counter physical block, find out the new current counter physical block that has minimum average read-write Counter Value in the average read-write counter pond; And,
The average read-write counter is copied to new current counter physical block from the last counter page or leaf of current counter physical block, and increase selected average read-write counter, then selected average read-write counter is write in the current counter physical block;
Thus, the average read-write counter duplicates between the page or leaf of current counter physical block, and under all full situation of all pages, the average read-write counter is copied in the new current counter physical block.
Described method also comprises:
When there is not empty counter page or leaf in current counter physical block, wipe current counter physical block, the average read-write counter is copied in the new current counter physical block.
A kind of method that is used for the volatibility question blank of recovery after power cut rotating disk (rotating disk) non-volatile cache comprises:
From M inlet of volatibility question blank, choose current inlet;
(a) read in flash array first data area first logical sector address of each first physical block, find out the first mould M remainder of first logical sector address, when the identifier match of current inlet in the first mould M remainder and the volatibility question blank, read the first historical counter from this physical block;
Read second logical sector address of each second physical block in flash array second data area, find out the second mould M remainder of second logical sector address, when the identifier match of current inlet in the second mould M remainder and the volatibility question blank, read the second historical counter from this physical block;
The first historical counter and the second historical counter are compared;
When the count value of the first historical counter is upgraded than the count value of the second historical counter, current inlet in the volatibility question blank is write the mapping of first physical block;
When the count value of the second historical counter is upgraded than the count value of the first historical counter, current inlet in the volatibility question blank is write the mapping of second physical block;
Select another current inlet from the M inlet of volatibility question blank, repeating step (a) all M inlets in the volatibility question blank are all processed, thus,
The volatibility question blank is recovered from the flash array of non-volatile cache.
Described method also comprises:
Interception has the host requests of corresponding stored host logic sevtor address of host data in rotating disk;
Inquire about the mould M remainder of this host logic sevtor address, wherein, the volatibility question blank has M inlet;
Use mould M remainder in the volatibility question blank, to select a selected inlet; Non-volatile flash memory, read the selected physical block address of a selected physical block from selected inlet.
Description of drawings
Fig. 1 is the structural representation block diagram of the computer system of use flash cache hard disk;
Fig. 2 is the structural representation block diagram of flash cache card;
Fig. 3 is the arranged distribution synoptic diagram of physical block in the buffer memory flash array;
Fig. 4 A-C finds out physical block address for query logic sevtor address in the RAM question blank, and has expired the synoptic diagram of handover data region under the situation at physical block address;
Fig. 5 A-E has described access Foreground Data zone and Zone switched process in detail;
Fig. 6 is the process flow diagram of main frame read operation;
Fig. 7 A-B is that main frame is got the process flow diagram of configuration at the write or read that reads under the miss situation;
Fig. 8 is the process flow diagram of average read-write;
Fig. 9 A-D is outstanding to have showed that the average read-write counter is updated, is moving between the page or leaf and the wiping in advance of piece in average read-write counter pond;
The process flow diagram that Figure 10 recovers for the routine under the powering-off state.
Embodiment
The present invention is to the improvement based on the buffer memory of flash memory.Described subsequently detailed applications and condition can be made or produce to realize the present invention for those skilled in the art.Consider that technical ability in the art can make various modifications based on the embodiment of first-selection, Ding Yi general principle can be applied to other embodiment herein.Therefore, the present invention is not limited to cited embodiment, and principle that can disclose according to this paper and novelty are in the range applications of broad sense.
Fig. 1 comes the structural representation block diagram of the computer system of buffer memory hard disk for adopting flash memory.Host CPU 10 is carried out the instruction from DRAM12, reads and writes data from DRAM12, will be in processor cache 22 from the instruction of DRAM12 or metadata cache, and processor cache 22 adopts sram caches usually.
When the memory address from host CPU 10 is sent to DRAM12 by rambus, I/O Address (I/O Address) is sent to I/O processor (I/O Processor) 14 from host CPU 10 via bus 26, is the part of peripheral bus chipset.I/O processor 14 may contain controller and some input/output bus interfaces, include the integrated electronics interface (IDE) or the serial hi-tech configuration interface (Serial ATA, abbreviate SAT A) that are connected to hard disk drive 16 by IDE/SATA bus 28.By IDE/SATA bus 28, piece or sector data are read out or write in the mass-memory unit, usually directly by random access memory access (DMA), or execute instruction by host CPU 10 indirectly and are transferred to DRAM12 or transmit from DRAM12.
I/O processor 14 has the USB (universal serial bus) (USB interface) of adapting universal serial bus (USB) 32, can connect multiclass plug-in unit or non-volatile USB device, as USB flash memory card 18.I/O processor 14 also has the quick interconnecting interface of peripheral assembly (PCIE interface) of the quick interconnecting interface bus of adaptive peripheral assembly (PCIE) 30.In the present embodiment, flash cache card 20 is installed on the PCIE bus 30, but also can be installed on usb bus 32, on IDE/SATA bus 28 or other bus.
Detect through flash cache card 20 from the I/O Address of I/O processor 14 and to decide when access hard disk driver 16 of these addresses.The data that are written into or read hard disk drive 16 are by 20 interceptions of flash cache card, and are stored in the flash cache by 20 controls of flash cache card, or the flash chip of flash cache card 20, or such as the external flash of USB flash memory card 18.
Fig. 2 is the structural representation block diagram of flash cache card.Flash cache card 20 is connected to main frame by PCIE bus 30 through an outside I/O processor.PCIE interface 42 generates the data encapsulation bag, handles from the handshake communication of the order of PCIE bus 30 receptions.Decode through I/O Address demoder 48 from the I/O Address that PCIE bus 30 receives.When the I/O Address coupling is stored or is programmed the I/O scope that writes flash cache card in the I/O Address latch 49, activate a card and select signal.
IDE address comparator 46 is relatively from the used I/O scope of the I/O address of PCIE bus 30 and hard disk drive 16.When I/O address mates the I/O scope of hard disk drive 16, IDE address comparator 46 will activate an IDE hiting signal, make 42 these orders of interception of PCIE interface, make 16 pairs of these orders of hard disk drive no longer respond.
Sevtor address can extract from the order that transmits through PCIE bus 30.The sevtor address of hard disk or other mass storages is logical sector address (Logical-Sector Address is called for short LSA), is the logical address from host CPU 10, rather than physical address; The LSA sevtor address can find its physical block address (Physical-Block Address is called for short PBA) from random access memory question blank (RAM Lookup Table is called for short the RAM question blank) 40.PBA is the physical address of flash block among flash array (the Flash-Memory Array) 50, this PBA is stored in data cached in hard disk drive (Hard-Disk Drive) 16 1 sectors, and its uses the hard disk mapping (Mapping) of the logical sector address of himself to locate physical sector on the hard disk drive.
RAM question blank 40 stored logic sevtor address are to the mapping that is buffered in physical block address in the flash array 50.Which physical block that RAM question blank 40 provides a kind of fast method to judge and reads in the flash array 50 determines whether data cached.Each physical block address is divided into a plurality of page or leaf, as 4,8,64 or other quantity.Each page or leaf is preserved a sectors of data, and stores the logical sector address and the significance bit (valid bit is called for short VAL) of these data.
Flash controller (Flash memory controller) 44 can read the physical block of this physical block address to find the corresponding physical block address by the query logic sevtor address again from flash array 50 in RAM question blank 40.The logical sector address of each page is read in this physical block address, and compares with logical sector address from host requests and to have judged whether that coupling takes place.Whether flash controller 44 is verified to mate and produce a hiting signal by the significance bit that detects this page and is given main frame.This hiting signal can send by the form of PCIE bus 30 with order or packet.
Fig. 3 is the distribution schematic diagram of physical block in the flash array of buffer memory.Flash array 50 comprises the flash chip of one or more addressable blocks.Data can all be erased to 1 simultaneously in the piece, are written into 0 then.But under the situation of not wiping monoblock, it is 1 that data can't write back from 0.
In more practical application, although may contain the page or leaf of bigger quantity in each piece,, yet be simplified illustration as 64 pages, adopt each piece to comprise 4 pages or leaves in the present embodiment.Data cachedly be stored in two data zones: first data area 52 and second data area 54 also are called as data area 0 and data area 1 respectively.They have the physical block of equal number, are 10 as what adopt in the present embodiment, but also can adopt bigger as quantity such as 32,64,256.These physical blocks in first data area 52, be flagged as PBA0, PBA1, PBA2 ... PBA9, in second data area 54, be denoted as PBA10, PBA11, PBA12 ... PBA19.Each physical block has 4 pages or leaves, the logical sector address and the significance bit of data cached, this page data of a sector of each page storage.
In addition, each physical block is also being stored a block identifier (piece ID) or other block message.The piece ID of each piece is changed to EEEE in first data area 52, and the piece ID of all pieces is changed to DDDD in second data area 54.Therefore piece ID has represented the affiliated data area of physical block.
The 3rd zone is used to store average read-write (wear-leveling, this paper abbreviates WL as) information in the flash array 50.Physical block PBA21 to PBA30 in average read-write counter pond (wear-leveling counter pool) 56.The piece ID of all pieces is set to 9999 in the average read-write counter pond 56, to distinguish the data block of they and first data area 52 and second data area 54.
Each physical block comprises 4 pages or leaves in the average read-write counter pond 56, and each page or leaf comprises nearly 127 average read-write counters (wear-leveling counter, this paper abbreviates WLC as).Each physical block in data area 52,54 and the average read-write counter pond 56 all has an average read-write counter.These average read-write counters be marked as PBA0_WL, PBA1_WL, PBA2_WL ... PBA126_WL, PBA127_WL.
For the page or leaf of one 512 byte, each counter of 127 counters is 4 bytes, can calculate 4G.When having piece to be wiped free of, just have an average read-write counter automatically to increase by 1 time, so each piece support wipe for maximum 4G time, these 100000 times of being far longer than common support repeat to wipe.
Each page or leaf of each piece comprises 127 average read-write counters altogether in the average read-write counter pond 56.In the average read-write counter pond 56 only page or leaf comprised whole caching system recently and current effective average read-write counter.Other pages all are redundant, comprise old average read-write counter, or empty counter is standby.
When physical block is wiped free of, the average read-write counter of this piece can add 1, may need a position of average read-write counter to be replaced by 1 by 0, and this only occurs over just under the whole situation about being wiped free of that comprises the average read-write counter.Because the average read-write counter will be damaged after wiping, all average read-write counters can be copied in the average read-write counter pond 56 in the old last blank block.The average read-write Counter Value will can not lost, and only be to transfer in the new piece in average read-write counter pond 56.Old that has old average read-write counter will be wiped free of, and be recycled in the average read-write counter pond 56.
Fig. 4 A-C has highlighted in the RAM question blank inquiry input logic sevtor address and has found physical block address, and the process that has expired handover data region under the situation at all pages of physical block address.In Fig. 4 A, main frame sends a write request to flash cache card (Fig. 1 20).This request comprises the logical sector address of one 512 byte logic sector on the sign hard disk, and this request is tackled and extraction logic sevtor address from request command by the flash cache card.
An inlet that uses mould generator (modulo generator) 58 to select in the RAM question blank 40, logical sector address is by hash.When data area and physical block quantity equated, the mould that mould generator 58 adopts was half of data physical block total quantity, also equals the physical block quantity of each data area as first data area 52 or second data area 54.
Have in the simple example of 20 or 10 physical blocks in each data area, the mould that mould generator 58 adopts is 10.With 22,32,2 grades are the same, No. 2 inlets of 12 logical sector address mapping RAM question blank 40.In this simple example, logical sector address is that decimal number and mould are 10, RAM question blank 40 go into the last digit that slogan just is exactly a logical sector address.May use 2 index under the more actual conditions, for example 2 index table 8,16,32,64 etc.
The value that is stored in each inlet in the RAM question blank 40 all is the foreground piece, and the foreground piece is current addressable.When a full piece need be written into the data of another page, this full piece can be switched to the backstage, was used for data and write back hard disk and wipe.Switch to the data that the foreground receives new page or leaf and another piece on backstage is selected.Backstage piece inaccessible can only be write back hard disk, or the wait of being cleared switches to the foreground.
In Fig. 4 A institute example,, be mapped to No. 2 inlets in the RAM question blank 40 from the logical sector address of 12 main frames by mould generator 58.No. 2 inlet expression PBA4 are mapped to generate 2 physical blocks as all logic sectors of the remainder of mould generator 58 in the RAM question blank 40, and logical sector address is 12 only can be stored among the piece PBA4 of foreground.
Because PBA=4 is in first data area 52, PBA=4 will be read from first data area 52 of flash array 50.Each physical block address has four data pages, the sector data of each page storage 512 bytes, the logical sector address and the significance bit of this sector data.The logical sector address of each page is read in four data pages, and compares with logical sector address from main frame.If the matching addresses of this page or leaf, and significance bit is effective, and then data can return to main frame through reading from this page or leaf, and hard disk need not accessed.Because the hard disk access speed is slow, can greatly improve performance so read sector data from flash array 50.
Read miss generation when one, data are removed and return to main frame from hard disk.Come into force when reading miss allocation strategy, the sector data of hard disk will be written to the blank page of the physical block address pointed of inlet in the RAM question blank, or new physical block described later address.
For write operation: when effective coupling took place, old sector data lost efficacy and will be replaced by new sector data from main frame in the data page of coupling.Because hard disk is that piece reads rather than reads at random, so whole sector is covered by new sector data.Matched data page or leaf in this physical block address is disabled.
No matter whether logical sector address mates inlet physical block address pointed in the RAM question blank, new sector data (from the write operation of main frame or miss from reading of hard disk) can be written into a blank page in this physical block address, the page or leaf 3 as shown in Fig. 4-A.The input logic sevtor address is also write in this blank page in the lump, and the significance bit of this page is set.
In Fig. 4 B, another logical sector address that is mapped to the same physical block address write or read operation miss.For example, LSA=22 has from the same remainder 2 of mould generator 58, has also selected to point in the RAM question blank No. 2 inlets of physical block PBA4.Yet because PBA4 is full and do not have blank page, new sector data can not be written into this Physical Page.Because this is a flash memory that does not allow to write position from 0 to 1, not wipe under the whole situation, old sector data can't be rewritten.
Old PBA4 is switched to the backstage from the foreground, and the data area 0 that comprises PBA4 is the zone, backstage of using for current accessed.Sector data old among the PBA4 is written into hard disk.Owing to exist another to have the page or leaf of more current datas, all invalid pages or leaves are not written into hard disk.After writing back hard disk and finishing, old is wiped free of, and PBA4 can be recovered and reuse.Therefore this write-back and wiping the cost plenty of time can replace old PBA4 make write-back finish with wiping on the backstage as new foreground piece with a new piece.
Because old PBA4 is in first data area 52, then second data area 54 is switching to new zone, foreground.One in second data area 54 in 10 physical blocks is selected to replace old.In second data area 54 the average read-write counter of free piece can be examined, the empty piece with minimum average read-write will be selected to new foreground piece, non-empty block then can be not selected in second data area 54.Part piece in second data area 54 may be used as other inlet uses for the RAM question blank of foreground piece, and part may be not finish the backstage piece of wiping as yet, and part perhaps is a bad piece.
For example, be used separately as inlet in the RAM question blank 40 3,8, No. 0 owing to appeared at, piece 11,12 and 17 just is being used as the foreground piece, and piece 10,13 may not wiped as yet and finished, so only be that piece 14,15,16,18 and 19 can be used.Check the average read-write counter of available block 14,15,16,18 and 19, find that the average read-write counting of piece 14 is minimum, so piece 14 is selected.
The mapping of No. 2 inlets becomes PBA=14 from PBA=4 in the RAM question blank 40.Switch the old piece PBA4 that expires and be used to the backstage write back and wipe, and switch empty piece PBA14 to the foreground.Four pages or leaves of on the PBA14 all are wiped free of and have been ready for the reception sector data.
Because old PBA4 do not had blank page among Fig. 4 B, in Fig. 4 C, new mapping is used for the logical sector address LSA22 that can't find out blank page again from old PBA4 and selects PBA14 in the RAM question blank 40, first of PBA14 page is empty, so the new sector data from main frame is written into this page or leaf, the input logic sevtor address also be written into this first the page or leaf, the significance bit in this page also is provided.Under the miss situation of the write or read of back, PBA14 can also receive more sector data for the input logic sevtor address that has from the remainder 2 of mould generator 58.Write that old sector data will continue for some time as background process among the PBA4.
Fig. 5 A-E illustrates access Foreground Data zone and Zone switched process in more detail.In Fig. 5 A, main frame sends one, and to have value be that the sector data write request of D31Q is to LSA31.LSA31 to 10 deliverys after remainder be 1, therefore choose No. 1 inlet in the RAM question blank.This inlet has shone upon LSA31 (LSA1, LSA11, LSA21 or the like) to PBA12.
PBA12 is in the data area 1, promptly in second data area 54.For this visit, second data area 54 is zones, foreground, and first data area 52 is zones, backstage.Foreground and zone, backstage can be switched for each visit.For example, be mapped to the logical sector address of PBA1 by No. 0 inlet in the RAM question blank 40, its Foreground Data zone be an area 0, and be mapped to PBA12 by entering the mouth for 1, No. 2 in the RAM question blank 40, other logical sector address of 15, its zone, foreground is regional 1.
Be compared to input logic sevtor address LSA31 from the flash array PBA12 that reads and each page or leaf that is stored in logical sector address.The logical sector address 31 of a coupling input LSA12 is arranged in the page or leaf 0, and significance bit is changed to 0,1, i.e. available state.Data D31 in the page or leaf 0 is substituted by the data D31Q from main frame, and then page or leaf 0 is by upgrading significance bit to 0, and 0 is that invalid attitude is disabled.If this is to read rather than write operation, then page or leaf 0 data D31 will return main frame and significance bit is constant.
Because the position in the flash memory can only be write as 0 by 1, the menophania of significance bit is erased to 1,1, promptly vacant state; After effective data were written into a page or leaf, the significance bit of this page was changed to 0,1, i.e. available state, and by writing significance bit to 0,1 is invalid attitude, data are disabled.Do not use 1,0 state in the present embodiment.
In PBA12, page or leaf 1 is effectively, but has one and unmatched logical sector address 21.Page or leaf 2 is effectively, also has a unmatched logical sector address 41.Page or leaf 3 is because its significance bit is 1,1, so be a blank page.After wiping last time, page or leaf 3 also is not written into, and all positions of its data and logical sector address field are changed to 1, and random data only can be written into page or leaf 3 once.Because any 0 all can not be rewritten back 1 in the flash memory.
Input LSA31 address is written into the LSA field of page or leaf 3, is the data fields that the new sector data of D31Q is written into 512 bytes with duration, and significance bit is changed to 0,1 to show that data are effective in the page or leaf 3.
In Fig. 5 B, main frame write data D81 to LSA81.This access is mapped to PBA12 again by RAM question blank 40.There is not the blank page that is used to receive new data in any one LSA that stores in four pages or leaves of PBA12 but this new logic sevtor address LSA81 does not match among the PBA12.PBA12 is switched to the backstage, effective sector data D21 in the page or leaf 1,2,3, and D41, D31Q is write back hard disk; 0 page is invalid, is not also write back hard disk.After a period of time, write back finish after, PBA12 is wiped free of (Fig. 5 D).
If host requests is to read, with miss, PBA12 still can be write back hard disk, and another sky piece is switched the reading of data (promptly reading miss distribution) that receives hard disk.
PBA12 belongs to second data area 54 that becomes the back-end data zone, and first data area 52 becomes the zone, foreground.The PBA1 non-NULL can be not selected, and PBA0/2 is that empty possibility is selected.If other PBA3-9 sky also may be selected.The average read-write counter is through identifying, PBA0 is found has minimum average read-write counting, so PBA0 is selected wipes available block as minimum, and becomes the foreground piece.PBA=0 is written into to substitute in No. 1 of RAM question blank inlet and is mapped to old PBA=12.
Because power supply may cut off the power supply at any time, which piece historical counter is used to follow the trail of is the foreground piece, and which piece is the backstage piece.Recover software or firmware and can read these historical counters, be used for having same remainder when two pieces, therefore when being mapped in the RAM question blank same inlet, judge which piece is older, which piece is newer, the new piece that has how current historical counting is the foreground piece, is the backstage piece and have old of older counting.
Historical counter is to move 0 mode " increase " from right to left.For example the history counting as old PBA12 (1110000) is read, and increases and copy to the history counting field of new piece PBA0 (11000000), as shown in Fig. 5 C.Since 11100000 be one than 11000000 older history counting, so PBA12 is old and PBA0 is new piece.
In Fig. 5 C, be stored in before the new PBA0, historical counter duplicates out from old PBA12 and adds 1 automatically.Page or leaf 1,2,3 keeps vacant, has whole positions 1, but page or leaf 0 is written into host data D81, input LSA81, and significance bit is changed to 0,1.PBA0 remains with 3 blank pages, and old PBA12 still just write back hard disk.
In Fig. 5 D, a new host requests arrives.This is that the value of writing is the operation of the sector data of D70 to LSA70.To 10 deliverys, No. 0 inlet of RAM question blank 40 is selected by LSA70.Mapping is PBA=1 in No. 0 inlet.PBA1 is full, so it does not have the space of memory sector data D70.Owing to there not be the logical sector address of mating in four pages or leaves, so there is not the operation that need allow piece invalid.
PBA1 is switched to the backstage, and its sector data writes back hard disk.Another data area, promptly second data area 54 becomes the zone, foreground.One has the available empty piece of minimum average read-write counting by the new foreground piece of selected conduct in second data area 54.
In second data area 54, with PBA10,11 the same, old PBA12 now finished and write back hard disk and wipe, and is available.PBA10 is selected because having minimum average read-write counting.PBA=10 is written into the new map addresses of RAM question blank 40 as No. 0 inlet.
In Fig. 5 E, host data D70 is written into the data sector field of new first page of piece PBA10, and input LSA70 is written into, and significance bit also is changed to 0,1.The historical counter that is used as old PBA1 of RAM index is replicated, increases and be written to new piece PBA10.Old historical Counter Value is increased to 11111000 by 11111100.After still being write back hard disk, wipe old PBA1.
Flow process is shown in Fig. 6-8.
Fig. 6 is the process flow diagram of main frame read operation.Main frame sends a read request that has the logical sector address of certain sector on the related hard disk.Main frame can at first be checked the card presence bit by a register that reads flash cache card (not shown).If the flash cache card does not exist, the card presence bit will point out main frame not have flash cache to exist, can the direct access hard disk.
In step 202, by the inlet quantity delivery to the RAM question blank, the logical sector address in the host requests is by hash, with the internal memory index (RAM Index) that distributes selected inlet.The physical block address selected inlet from the RAM question blank that is mapped to this logical sector address reads out, and first page or leaf of the physical block address of the selected inlet of sensing RAM question blank is by access.In the step 204, the logical sector address and the significance bit of this physical block address are read.When depositing logical sector address coupling, and significance bit put available state at promptly 0,1 o'clock, and shown in step 206, a hit in tag is set up in the flash cache card, as step 208, and returned to main frame as the read data of reading the sector data field from hard disk.
When the physical block address current page input logic sevtor address or invalid that do not match, as step 206, and when having a plurality of pages in this physical block address, step 214, then next page or leaf is by access, step 210,204.The logical sector address and the significance bit of next page or leaf are examined whether hit step 206.Other page or leaf (214,210,204,206) in a similar manner is examined, up to finding one to hit and return data, and step 212,208, or be examined up to all pages or leaves and finish step 214.In not having effective logical sector address coupling physical block address, during any one page, a miss sign then is set, step 206.Main frame directly reads sector data, step 218 from hard disk then.When the data that read from hard disk are assigned to new physical block address and are written to flash array, read to distribute and take place, step 222 beginning from Fig. 7 A.
Fig. 7 A-B is the process flow diagram that reads distribution under the main frame write or read miss situation.Main frame sends a write request that has logical sector address, and checks the card presence bit of flash cache card (not shown).
Logical sector address in the host requests by to the inlet quantity delivery of RAM question blank by hash, to locate the corresponding RAM index of selected inlet, step 220.The physical block address selected inlet from the RAM question blank that shines upon this logical sector address is read out.
For reading distribution (map interlinking 6) under the main frame write or read miss situation, first page or leaf of the physical block address that selected inlet points in the RAM question blank is by access.The logical sector address and the significance bit of this first page of physical block address are read step 222.When depositing logical sector address coupling, significance bit was changed to available state at promptly 0,1 o'clock, and it is 0,0 that step 224, the significance bit of this matching logic sevtor address are eliminated, and it is invalid to make that the legacy data of this page becomes, step 230.
When the significance bit of current page was changed to 1,1 o'clock, this page or leaf is empty, step 226.The write data of main frame or hard disk read the data fields that miss data is written to this blank page, step 232.The significance bit of this page is changed to 0,1, and step 232 stores valid data to show it, step 234, and so far, accessing operation finishes.
When the current page non-NULL of PBA, step 226, and when having more a plurality of pages among the PBA, step 236, then next page or leaf is accessed, and whether step 238,222, the LSA of this next one page or leaf and significance bit are examined hits, step 224, and whether be empty, step 226.
Other page or leaf is examined through step 236,238,224,226 in a similar manner, and be found and be written into up to a blank page, step 226,232,234, or all be examined up to all pages or leaves and finish.When all pages or leaves are examined when not having blank page, physical block address is full.Then the write or read miss data can't dispose this physical block address, must distribute a new empty reason block address to receive new data.
Fig. 7 B is the operational circumstances of physical block address miss distribution of main frame write or read when having expired.All active page sector datas from old physical block address are write back hard disk, step 240.After data are successfully write back hard disk or after confirming, old physical block address is wiped free of step 242.Write back and wipe and to finish for a long time, but can be in the zone, foreground change it over to background process during by access.Step 246 and other can be worked as step 240, and 242 etc. processed when pending.In case physical block address is wiped free of, its average read-write counter can increase step 244.
Old physical block address is assigned to the backstage, and another data area becomes zone, foreground, step 246.New physical block address empty, that have minimum average read-write counting is selected from the physical block address in zone, foreground, step 248.The new sector data of main frame (main frame is read) or hard disk (reading miss distribution) is written into first page or leaf of this new physical block address, step 250.
The significance bit of this first page is changed to 0,1, and is effective with the data of representing this page, step 252.After being read, increasing, the historical counter of old physical block address is written to new physical block address, step 254, and so far, the miss operation of write or read is finished.
Fig. 8 is the process flow diagram of average read-write management.A physical block is whenever wiped once, and its average read-write counter can increase once.After electronics erasable programmable ROM (read-only memory) (EEPROM) unit access times exhausted in the flash chip, as after erasable operation, the electronics that embeds or be enclosed in oxide or other insulation course in the flash memory finally can be depleted and no longer reliably available.Average read-write is to be used for the frequency of utilization of balanced flash array, and other piece is scrapped too soon to avoid some pieces not used by appropriateness.Under the perfect condition, make as much as possible to keep available in the long as far as possible time, these pieces are scrapped in identical life cycle.Discarded piece removes from the available block group after differentiating.
No matter be that physical block in data area or the average read-write counter pond is wiped free of, its average read-write counter flow process as shown in Figure 8 increases.A physical block pond is to be specifically designed to storage average read-write counter, average read-write counting chamber 56 as shown in Figure 3, rather than is used for storing the sector data from hard disk cache, and the piece in the average read-write counter pond 56 all only is used to store the average read-write counter.
The page or leaf of all system's average read-write counters in can a corresponding piece.Can deposit the average read-write counter of 128 4 bytes as the page or leaf of one 512 byte.In the average read-write counter pond 56 only a piece comprise current average read-write counter, other piece may comprise older, old average read-write counter, or has been wiped free of stand-by.
Even in current average read-write piece, only there is a page or leaf to comprise current average read-write counter.Other page comprises old average read-write counter in the current average read-write piece, or is sky (wiping).For example, page or leaf 2 comprises current average read-write counter, and page or leaf 1 comprises old no longer valid average read-write counter, and page or leaf 3 also is not used after being wiped free of.When the average read-write counter is updated, new average read-write counter is written in the page or leaf 3, and the old counter in the page or leaf 0,1,2 all wears.
Each average read-write piece all has a historical counter that is used to show its average read-write counter age, and the piece that has up-to-date historical counter in the average read-write counter pond 56 is updated by current, and preserves up-to-date average read-write counter.The piece that has up-to-date average read-write counter is found in step 302.The historical counter of all pieces is read and comparison in the average read-write counter pond 56, and the physical block address of recent renewal piece is stored in internal memory or the system register so that software reads.
Because flash memory can only be written as 0 by 1, and can not be written as 1 by 0, if its unique variation is that the position is written as at 0 o'clock from 1, the average read-write counter increases (write flash memory rather than wipe), for example, all is 1 after the average read-write counter is wiped, it can increase to 11111110 and do not need to wipe once more by 111111111, but, do not wipe or be copied into one wipe in advance the page or leaf situation under, but can not be increased to 11111101 from 11111110.An order of putting upside down has been used in attention " increase " herein, and it can be taken as reduces rather than real increase.In the average read-write counter, bigger binary value is upgrade rather than the older count value of expression.
May also have other to finish increases and need not the position is become 1 method from 0, for example increases to 11110000 from 11110001, can check in the step 306 that these need not the position is become 1 increment of finishing from 0, rather than seek all first kind of situations.Yet if flash cell can only write once in the process of wiping for twice, step 306 can only be sought first kind of situation.
When step 306 judges that the average read-write counter that need be updated only requires to be written as 0 with 1, as first kind of situation.Then current page can only be rewritten into the new value of average read-write counter.Current page is to write page or leaf recently in the current block, and as a rule this page is exactly the last empty pages of piece.The currency of all average read-write counters reads from the current page of current average read-write piece, and the average read-write counter of the piece that just has been wiped free of increases, and new numerical value is written back to same, step 312.The historical counter of current block can be updated step 314.
When the average read-write counter upgrade to need with the position when 0 is written as 1 step 306 failure.A simple write operation can't be realized, if this piece is not taken fully, then need find out the new page or leaf that the next one is used to deposit newly-increased average read-write (WL) value.Equally, all average read-write counters are copied to a pre-erase block, when there is blank page in same current block, distribute a new page or leaf, step 308 for this reason.Then the currency of all average read-write counters is read from the current page of current average read-write piece, and the average read-write counter of the piece that just has been wiped free of increases.New value is write back following one page of current page in the same current block, step 316.The historical counter of this current block can be updated.
If there is not blank page in the current block, step 308, current block is full, then must find out a new piece in average read-write counter pond.In the average read-write counter pond 56, be wiped free of and not conform to the piece of any data found, as by these type of piece row are got inventory, or read the piece ID of all pieces in the average read-write counter pond.By checking the average read-write counter of current page, in these erased blocks, find out minimum average read-write counting, have the new average read-write counter block of the selected conduct of piece of minimum average read-write counting, step 310.
The currency of all average read-write counters reads out from the current page (promptly last page or leaf) of full current average read-write piece.The average read-write counter of the piece that just has been wiped free of increases, and new value is written in first page or leaf of a new average read-write count block, step 304.The historical counter of old average read-write counter is read, increases, and is written back to new average read-write counter block, step 305.
Fig. 9 A-D emphasis is described in the average read-write counter pond, page or leaf and the average read-write counter process that is updated and identifies of wiping page or leaf in advance.Among this figure, only shown three physical block address: PBA21, PBA22 and the PBA23 in average read-write counter pond.Each piece has 4 pages or leaves, and each page all contains the data capacity that is used to comprise the average read-write counter of 512 bytes, and each page or leaf can be stored 128 average read-write counters at the most.Example shows among Fig. 9 is that the scale-of-two of average read-write counter just increases, and is not negative increase shown in Figure 8.
WLC_PBA0 is the average read-write counter of physical block address PBA0 in first data area 52, WLC_PBA10 is the average read-write counter of physical block address PBA10 in second data area 54, WLC_PBA20 is the average read-write counter of physical block PBA20 in the average read-write counter pond 56, by that analogy.Some average read-write counter may not be used as yet, and in simple embodiment, when system only had 30 physical block address, some average read-write counters such as WLC_PBA130 were not used to WLC_PBA1127.
In the example of Fig. 9 A, piece PBA22 and PBA23 are empty and wipe in advance that have the piece ID that value is FFFF, all data are changed to 1.Piece PBA22 and PBA23 are standby in the average read-write counter pond 56.The historical counter of piece PBA22 and PBA23 is changed to 11111111, represents that this piece is empty piece.
Because the historical counter of piece PBA21 is minimum, institute thinks current block.At first, page or leaf 1,2,3 is empty, and page or leaf 0 is a current page.The average read-write counter of data block PBA0 is 1, and the average read-write counter of data block PBA2 also is 1, and this expression PBA0 and PBA2 were wiped free of once.All other pieces have the Counter Value of all 1 ' s, represent that they were not wiped free of as yet.The historical counter of page or leaf 0 is 11111110, and it upgrades than 11111111.
Among Fig. 9 A, PBA2 is wiped free of 4 times, and PBA3 is wiped free of 2 times.In Fig. 9 A, PBA2 is wiped free of for the first time, and its average read-write counter will be increased to 2 from 1, and the average read-write counter of other data block will still remain unchanged.New average read-write Counter Value is written in the page or leaf 1 of PBA21, and its historical counter is updated to 11111100 from 11111110.
Next, PBA2 is wiped free of again, and PBA3 also is wiped free of.The average read-write counter of PBA2 is increased to 3 from 2, and 1 (also promptly counting 0) is increased to counting 1 and the average read-write counter of PBA3 is from the position, and other piece remains unchanged.New average read-write Counter Value is written in the page or leaf 2 of PBA21, and historical counter is updated to 11111000 from 11111100.
At last, PBA2 and PBA3 are wiped free of together once more, and the average read-write counter of PBA2 is increased to 4 by 3, and the average read-write counter of PBA3 is by being increased to 2 by 1, and the counter of other piece remains unchanged.New average read-write counter is written in the page or leaf 3 of PBA21, and historical counter is updated to 11110000 from 11111000.
In Fig. 9 B, PBA3 is wiped free of once more, and its average read-write counter is updated to 3 by 2.Yet current average read-write counter block PBA21 is full, has not had more blank page.The next current average read-write counter block of a selected conduct of empty piece in average read-write counter pond 56.In the average read-write counter pond, PBA23 is selected because of the minimum average read-write counting that has available block.
The average read-write counter of last page or leaf 3 is copied among the new current block PBA23 among the old current block PBA21, and the average read-write counter of PBA3 is increased to 3 from 2.The average read-write counter of other piece still remains unchanged.New average read-write counter is written in the page or leaf 1 of PBA23, and historical counter is updated to 11100000 from 11110000, and old average read-write counter PBA21 is wiped free of.
Among Fig. 9 C, in case PBA21 is wiped free of, its average read-write counter also need be updated, and 1 (promptly counting 0) is increased to counting 1 to the average read-write counter WLC_PBA21 of PBA21 correspondence from the position, and promptly binary zero 0000001.Because this only needs from 1 to be written as 0, therefore do not need the average read-write counter copied in the next page or leaf of PBA23 and just can finish.In case the PBA21 of average read-write counter 56 is wiped free of, it will be recovered for future use.
In Fig. 9 D, PBA19 is wiped free of altogether 4 times.When wiping for the first time, the average read-write counter becomes counting 1 from all positions 1 (counting 0), or becomes 00000001 from 11111111.Because this only needs to be written as 0 with 1, the new page or leaf that does not therefore need to copy to PBA23 just can be finished.The average read-write counter WLC_PBA19 of PBA19 is updated at the page or leaf 0 of current block PBA32.
PBA19 is wiped free of for the second time, and current average read-write counter is updated to 2 from 1, the position need be written as 1 from 0.The average read-write counter of PBA19 becomes 2 from 1, and the counter of other piece then remains unchanged.New average read-write counter is written in the page or leaf 1 of PBA23, and historical counter becomes 11000000 by 11100000.
PBA19 is wiped free of for the third time, and its average read-write counter is increased to 3 by 2, and the counter of other piece remains unchanged.New average read-write counter is written into the page or leaf 2 of PBA23, and historical counter becomes 10000000 from 11000000.
At last, PBA19 is wiped free of for the 4th time, and its average read-write counter is increased to 4 from 3, and the counter of other piece remains unchanged.New average read-write counter is written to the page or leaf 3 among the PBA23, and historical counter is updated to 00000000 from 10000000.
Figure 10 is the process flow diagram of recovery routine under the powering-off state.After the outage, the mapping of RAM question blank 40 all can be lost, and the inlet of this RAM question blank needs to be reconstructed according to the physical block information that is stored in the non-volatile flash memory array 50.
Start in the power supply process, the RAM question blank all is empty at first.Index is changed to 0 and point to first inlet, step 352 at first in the RAM question blank.Two data zones are that data area 52 and data area 54 are by diagram or in regular turn by parallel processing.For data area 0 is that data area 52, the first physical block address are taken as current physical block address by access, step 360.The logical sector address that this first page of piece is stored is read, step 262, and the RAM inlet of the logical sector address mapping of storage obtains step 366 by logical sector address to RAM inlet quantity delivery.If the RAM index that the mould of logical sector address coupling is current, step 336, physical block address can be stored this logical sector address, and its historical counter goes on record and relatively uses for the back.Otherwise the next physical block address of data area will be by access, and step 370, its logical sector address are examined the RAM inlet that whether belongs to current, step 362,366.Because same physical block address has identical RAM index, thus in the physical block address only first page need be examined.Significance bit also can be examined, and makes blank page to be left in the basket, and also can be examined even have first page or leaf of invalid data.
Next RAM index is selected, and step 380 repeats said process, searches the physical block address that has logical sector address that is mapped to the RAM index, from step 360,354, continues step 376,378 then.Final all RAM index are processed intact, and all inlets are all by reconstruct, step 380 in the RAM question blank.
The inventor has also conceived some other embodiment.For example the quantity of page or leaf can be other quantity than more than 4 in each piece, as 8,16,32,64 or the like.The quantity of physical block can increase in the system, and the piece in data and the average read-write counter pond is dynamic partition in several ways.The size of sector also can be different with described 512 bytes.For example in multi-level flash, the size of page or leaf can be 512 bytes, 2K, 4K or more, but reason owing to capacity, the sector-size of adopting as heir hard disk drive still remains 512 bytes, the position that each page or each piece may be stored other, as the LRU position, management or consistent position, bad piece position and other counter or the like.
In the present embodiment, flash card is to be located on the PCIE bus that has the PCIE interface, but also can use USB interface to be connected to usb bus.
Different flash memories may be erased to 0 and only can write 1, and can not be written as 0 from 1.Some flash memory may allow to wipe page or leaf, and does not require that monoblock is wiped free of.Compared with present embodiment, need not to select to have the PBA of minimum average read-write counting, and can select lower but not necessarily require the physical block address of minimum average read-write counting.The counter increase may be exactly takes place wiping preceding or wipe the back according to the average read-write counter of describing in the present embodiment, perhaps near this time, for example wipe, before the practical operation such as switching or take place afterwards.Use methods such as streamline, buffering and the switching of other time possibly.As when wiping very slowly, the waiting status that postpones foregrounding need be introduced into.
Also can use other increase process or algorithm, change 0 mode from right cut, can also use and for example use binary code account form, Gray code backward, or use by 2 polishing methods with respect to using.Can also use subtraction, also can put upside down the mode of a state or polarization by use except being changed to 1, the position can be changed to 0, or 1, or to be eliminated be 1,1.
Except using the remainder of delivery, also can use the ashing technique of other kinds to shine upon the logical sector address inlet of RAM question blank 40.The RAM inlet also can be preserved out of Memory, and additional internal memory or register can be used to store flash cache card or spendable state of its software-driven or program variable.
Historical counter or other counter can use other method of counting for example scale-of-two or Gray code.For example, historical counter may switch 0 from the right, switches from the right one by one then.For example sequence 11111110,11111100,11111000,11110000 ... etc.Some value in this sequence may be left in the basket, and for example is increased to 1111110 from 01111111 and will ignores erasure values 11111111.Many in addition sequences and variation all may be used.
Historical counter may comprise more position, and for example 32 rather than 8 is can calculate 32 times under 1 the situation not wiping 0.May use to be reduced to and change one and come the sequence of calculation, after using new piece, will have a position to change into 1 and take place, perhaps can ignore other value in the sequence from 0.Because old average read-write counter block is wiped free of, and counter can be reset by the cycle after all pieces are wiped free of, so a big Counter Value may not need to use yet yet.
The page or leaf ordering has various ways, for example at first checks page or leaf 1,3, and then checks page or leaf 0,2.Many other sequences can substitute.The step of many other verification msgs may be added into.Except the above-mentioned hard disk of buffer memory, can also come other mass-memory unit of buffer memory by multiple bus and agreement.The flash cache card can use the flash array that carries, and also can use the flash memory on other bus, for example the USB flash memory card.Some cachings or load can be handled such as I/O processor by main frame or other, and are shared by software, firmware and hardware.The flash cache card can be a printed circuit board (PCB) (PCB), and one is inserted card apparatus, a peripheral frame, plate or small rack on main equipment, or integrated other parts on the main frame.The hard disc data that is stored in buffer memory may be from one or more main frames, peripherals, bus manager or other sources.
It is also conceivable that other multiple standards when selecting piece, for example when the location cuts apart these pieces between bus, physics setting or card.Can also increase some added limitations when selecting next piece, for example restriction can be mapped to the quantity or the location of special RAM index physical block.For example, all logical sector address are shown only can shine upon a physical block address, and the RAM question blank has in the embodiment of shining upon restriction and may not need to use at some.Remove in this simplifications embodiment 10 power, 2 power also may be used as the quantity that RAM enters the mouth.
When system had 128 above physical blocks, current block may need two or more average read-write counter blocks.For example current block comprises the average read-write counter of physical block 0～127, and second current block then stored the average read-write counter of physical block 128～255.Piece ID represent can displaying block the average read-write counter in which piece, for example allow the piece ID of average read-write counter 0～127 be 9999, the piece ID of average read-write counter 128～255 is 7777.
May not be that all described advantage or benefits all are embodied in the specific embodiment of the invention.When speech " device (means) " when being introduced into claim, this claim of applicant is observed the 6th section at the 35th the 112nd joint of United States code.Usually have the sign of one or more described " device ".The restriction that the word of mentioned claim described " device " or phrase are not limited to structure.The claim that this device adds function not only comprises herein for finishing described structure of corresponding function and equivalent structure, has also comprised approximate structure.For example, although nail has different structures with screw, because they all are used for fixing, so they are approximate constructions.The claim of operative installations need not observed the 6th section at the 35th code of the U.S. the 112nd joint.Signal all is classical electric signal, also may be one can be by the optical signalling of Optical Fiber Transmission.
Aforementioned concrete enforcement Fang Jun of the present invention is the needs for example and description, and it is not limited only to the detailed content that discloses in the literary composition.According to above-mentioned guidance, can make various modifications and variations.Scope of the present invention is not limited to the description of details, but according to additional herein statement.
Claims (21)
1. flash cache subsystem is characterized in that comprising:
Flash memory physical block flash array by physical block address identification, each physical block comprise a plurality of pages or leaves, and each page comprises a data sector that only can write an arbitrary data before physical block is wiped; Wherein, data sector is piece addressing rather than randow addressing, and all bytes can not must be that unit is together by access individually with the piece with byte access in the data sector;
First data area is made of first physical block of flash memory in the flash array;
Second data area is made of second physical block of flash memory in the flash array;
Wherein, the data sector that each page in first physical block and second physical block will be stored in this page from the host data and the logical sector address of main frame, this logical sector address from main frame is the host address of host data;
Switching device shifter, when need being stored in a physical block that does not completely have a blank page, host data is activated, be used for by having expired physical block write data sector from first to outside mass-memory unit and wipe this piece, first is expired physical block switched to the zone, backstage, and selected second empty physical block to receive host data;
Simultaneously, also be used for having expired physical block with second and having switched to the zone, backstage, and first physical block of having selected receives host data by having expired physical block write data sector to outside mass-memory unit and wipe this piece from second.
2. flash cache subsystem as claimed in claim 1 is characterized in that also comprising:
One volatibility question blank has M inlet, and wherein, each inlet of M inlet can be stored a physical block address that is mapped to first physical block or second physical block;
One mould generator, reception is from the logical sector address of main frame, be used for logical sector address is carried out the remainder that can determine the selected inlet of volatibility question blank of operation generation of mould M, selected inlet is used to store a physical block address mapping, and a physical block address that is used to store by the host data of logical sector address identification is represented in this mapping;
Wherein, switching device shifter also is used for, and in the selected inlet of volatibility question blank, uses the physical block address mapping of physical block address mapping replacement first physical block of second physical block; With,
In the selected inlet of volatibility question blank, use the physical block address mapping of physical block address mapping replacement second physical block of first physical block;
The host data of host requests is stored in the data sector of first physical block that the physical block address mapping by selected inlet in the selected volatibility question blank of the mould remainder of host requests logical sector address selects or second physical block.
3. flash cache subsystem as claimed in claim 2 is characterized in that also comprising:
Average read-write counter pond is made of physical block flash memory average read-write counter in the flash array;
Wherein, each page of physical block average read-write counter has a large amount of average read-write counters in the data sector of this page, comprise,
The average read-write counter of per first physical block, second physical block, each average read-write counter physical block, the degree of average read-write counter keeps track flash memory physical block loss.
4. flash cache subsystem as claimed in claim 3 is characterized in that also comprising:
The average read-write selector installation is used for selecting the first empty physical block by first average read-write counter of checking first physical block;
Also be used for selecting the second empty physical block by second average read-write counter checking second physical block;
Wherein, the first average read-write counter and the second average read-write counter are the average read-write counter that is stored in current average read-write counter block in the average read-write counter pond.
5. flash cache subsystem as claimed in claim 4 is characterized in that also comprising:
Be stored in the historical counter in each average read-write counter block, be used for representing the up-to-date average read-write counter block in average read-write counter pond, wherein, up-to-date average read-write counter block is current average read-write counter block.
6. flash cache subsystem as claimed in claim 5 is characterized in that also comprising:
Replacement device, be used for working as all pages or leaves of current average read-write counter block with the average read-write count value, and physical block address is wiped free of and average read-write counter need be updated the time, in average read-write counter pond, use new current average read-write counter block to substitute current average read-write counter block, current thus average read-write counter block is replaced.
7. flash cache subsystem as claimed in claim 6 is characterized in that also comprising:
Read miss device, be used for being read by main frame when external data from outside mass-memory unit, and external data need be stored in one do not have blank page expire physical block the time, by reading miss activation switching device shifter, switch through reading miss activation in the zone thus.
8. flash cache subsystem as claimed in claim 7 is characterized in that described average read-write selector installation also comprises:
First selecting arrangement, be used to the empty piece of the first average read-write counter select to have minimum average read-write count value the first empty physical block and
Second selecting arrangement is used to the empty piece of the second average read-write counter to select the second empty physical block with minimum average read-write count value;
During outage, the described physical block address mapping that is stored in the volatibility question blank will be lost, and the data in the physical block of flash memory still are saved, thus,
It is selecteed that the empty piece of first and second data areas is based on the minimum average read-write count value of sky piece.
9. flash cache subsystem as claimed in claim 5 is characterized in that also comprising:
The PCIE interface of a corresponding PCIE bus, the host requests that has LSA and host data receives by the PCIE bus;
Wherein, outside mass-memory unit is the rotating disk that is connected to the PCIE bus by IDE bus or SATA bus through an I/O processor;
Wherein, the host requests of outside mass-memory unit on IDE or the SATA bus is tackled by the PCIE interface of flash cache subsystem, thus, outside mass-memory unit is connected on another bus.
10. flash cache subsystem as claimed in claim 5 is characterized in that also comprising:
The USB interface of one corresponding usb bus, the host requests that has LSA and host data is to receive by usb bus;
Wherein, outside mass-memory unit is the rotating disk that is connected to usb bus by IDE bus or SATA bus through an I/O processor;
Wherein, the host requests of outside mass-memory unit on IDE or the SATA bus is tackled by the USB interface of flash cache subsystem.
11. flash cache subsystem as claimed in claim 9 is characterized in that also comprising:
One external address comparer, be used for the address realm of outside mass-memory unit on comparison IDE or the SATA bus and the address of PCIE bus, wherein, flash cache subsystem interception is to the host requests of outside mass-memory unit, come buffer memory from or be written to outside mass-memory unit data.
12. flash cache subsystem as claimed in claim 6 wherein, by first data area that the first flash memory physical block in the flash array constitutes, comprises M first physical block,
Wherein,, comprise M second physical block by second data area that the second flash memory physical block in the flash array constitutes, thus,
Some inlets mate some first physical blocks in the volatibility question blank, also mate some second physical blocks.
13. one kind is used for adopting the volatibility question blank from the data cached method of the rotating disk of non-volatile flash memory, it is characterized in that comprising:
Interception has the host requests of corresponding stored logical sector address of host data in rotating disk;
The remainder of inquiry host logic sevtor address mould M, wherein, the volatibility question blank has M inlet;
Remainder by mould M is selected a selected inlet in the volatibility question blank;
In non-volatile flash memory, read the selected physical block address of selected physical block by selected inlet;
Come the query page coupling by the logical sector address that reads in each page storage, relatively this logical sector address and host logic sevtor address, but show in the significance bit of this page and logical sector address time spent of storage to send a page or leaf matched signal;
From have selected physical block address produce the page or leaf coupling deposit reading of data sector in the logical sector address, and data sector is sent to main frame, when host requests is read request, forbid rotating disk is carried out access;
When not having page matched signal, activate rotating disk and will read to coil data and return to main frame, and will read to coil data and from rotating disk, be written in the non-volatile flash memory; With,
When host requests is write request, blank page of inquiry and host data write in this blank page in selected physical block address perhaps, when host requests is a read request and when not having the page or leaf coupling, will be read to coil data and be written to this blank page from rotating disk;
When not finding blank page in the selected physical block, activate a toggle path, the data sector of storing in the selected physical block page or leaf is copied to rotating disk, and wipe selected physical block, and select the physical block of a new band blank page, write the host data of autorotation disk or read to coil data, thus
When selecting a new selected physical block by toggle path, the data area is switched and is taken place.
14. method as claimed in claim 13 is characterized in that described toggle path also comprises:
When host requests is write request, in the blank page of new selected physical block, write host data; Perhaps, when host requests is read request and does not have when coupling page or leaf, data are written to the blank page of new selected physical block from rotating disk; With
The physical block of non-volatile flash memory is divided into first data area and second data area;
When the selected physical block of no blank page is present in first data area, wherein, toggle path will be selected a new selected physical block in second data area; When the selected physical block of no blank page was present in second data area, wherein, toggle path will be selected a new selected physical block in first data area;
Thus, when new selected physical block was switched the path and chooses, two data zones were switched.
15. method as claimed in claim 14 is characterized in that also comprising:
When toggle path was activated, the new selected inlet that is used for storing the new selected physical block address of the new selected physical block of non-volatile flash memory covered original selected inlet in the volatibility question blank, thus,
Selected inlet is realized replacing by toggle path in the volatibility question blank.
16. method as claimed in claim 15 is characterized in that also comprising:
When selected physical block is wiped free of, upgrade the average read-write counter of this selected physical block;
Inquire about and compare the average read-write counter of the empty physical block in first or second data area, find out a new selected physical block, thus,
The average read-write counter assists to select new selected physical block.
17. method as claimed in claim 15 is characterized in that also comprising:
By reading, increase the historical counter of selected physical block, upgrade the historical counter of new selected physical block, thus, when toggle path is activated, historical counter can be updated.
18. method as claimed in claim 15 is characterized in that also comprising:
When selected physical block is wiped free of, activate more new route of average read-write counter, comprising:
By reading and compare the history counting of counting implements reason piece in the physical block average read-write counter pond of non-volatile flash memory, find the historical counter of a recent renewal; Wherein, current counter physical block has up-to-date historical counter in the average read-write counter pond;
When selected average read-write counter never is written into, increase the selected average read-write counter of selected physical block.
In current counter physical block, seek the counter page or leaf of a sky, average read-write counter last counter page or leaf from current counter physical block is duplicated the counter page or leaf of a sky, and increase selected average read-write counter, selected average read-write counter is write in the empty counter page or leaf;
When in current counter physical block, not having empty counter page or leaf, by checking the average read-write counter of current counter physical block in the average read-write counter pond, in average read-write counter pond, seek new current counter physical block, find out the new current counter physical block that has minimum average read-write Counter Value in the average read-write counter pond; And,
The average read-write counter is copied to new current counter physical block from the last counter page or leaf of current counter physical block, and increase selected average read-write counter, then selected average read-write counter is write in the current counter physical block;
Thus, the average read-write counter duplicates between the page or leaf of current counter physical block, and under all full situation of all pages, the average read-write counter is copied in the new current counter physical block.
19. method as claimed in claim 18 is characterized in that also comprising:
When there is not empty counter page or leaf in current counter physical block, wipe current counter physical block, the average read-write counter is copied in the new current counter physical block.
20. a method that is used for the volatibility question blank of recovery after power cut rotating disk non-volatile cache is characterized in that comprising:
From the M inlet of volatibility question blank, choose current inlet;
(a) read in flash array first data area first logical sector address of each first physical block, find out the first mould M remainder of first logical sector address, when the identifier match of current inlet in the first mould M remainder and the volatibility question blank, read the first historical counter from this physical block;
Read second logical sector address of each second physical block in flash array second data area, find out the second mould M remainder of second logical sector address, when the identifier match of current inlet in the second mould M remainder and the volatibility question blank, read the second historical counter from this physical block;
The first historical counter and the second historical counter are compared;
When the count value of the first historical counter is upgraded than the count value of the second historical counter, current inlet in the volatibility question blank is write the mapping of first physical block;
When the count value of the second historical counter is upgraded than the count value of the first historical counter, current inlet in the volatibility question blank is write the mapping of second physical block;
Select another current inlet from the M inlet of volatibility question blank, repeating step (a) all M inlets in the volatibility question blank are all processed, thus,
The volatibility question blank is recovered from the flash array of non-volatile cache.
21. method as claimed in claim 20 is characterized in that also comprising:
Interception has the host requests of corresponding stored host logic sevtor address of host data in rotating disk;
Inquire about the mould M remainder of this host logic sevtor address, wherein, the volatibility question blank has M inlet;
Use mould M remainder in the volatibility question blank, to select a selected inlet; Non-volatile flash memory, read the selected physical block address of a selected physical block from selected inlet.
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| US11/623860 | 2007-01-17 | ||
| US11623860 | 2007-01-17 | ||
| US11/623,860 US7610438B2 (en) | 2000-01-06 | 2007-01-17 | Flash-memory card for caching a hard disk drive with data-area toggling of pointers stored in a RAM lookup table |
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| CN101122887A true CN101122887A (en) | 2008-02-13 |
| CN100501702C CN100501702C (en) | 2009-06-17 |
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