CN107947781B - Active diode of self-adaptation on resistance - Google Patents

Active diode of self-adaptation on resistance Download PDF

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Publication number
CN107947781B
CN107947781B CN201711137122.5A CN201711137122A CN107947781B CN 107947781 B CN107947781 B CN 107947781B CN 201711137122 A CN201711137122 A CN 201711137122A CN 107947781 B CN107947781 B CN 107947781B
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pmos transistor
electrically connected
module
driving circuit
comparator
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CN107947781A (en
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刘帘曦
成江伟
华天源
朱樟明
杨银堂
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

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Abstract

The invention belongs to the technical field of integrated circuit design, and relates to an active diode with a self-adaptive on-resistance. The active diode of the self-adaptive on-resistance comprises a switching tube module, a comparator module and a logic and control unit module; the output end of the switch tube module is electrically connected with the input end of the comparator module; the output end of the comparator module is electrically connected with the input end of the logic and control unit module; and the output end of the logic and control unit module is electrically connected with the input end of the switch tube module. The self-adaptive change of the conduction resistance of the active diode can improve the detection precision of the current zero crossing point of the active diode, broaden the input range of the active diode and realize the active diode with low conduction voltage drop, high-precision current zero crossing point detection and wide input range.

Description

Active diode of self-adaptation on resistance
Technical Field
The invention belongs to the technical field of integrated circuit design, and relates to an active diode with a self-adaptive on-resistance.
Background
In recent years, wireless sensor network nodes and biomedical electronic devices have become the subject of intense research, and the traditional battery power supply is limited by the battery volume and the battery life, so that the miniaturization development of the electronic devices is restricted, and the cruising ability of the electronic devices is limited. Self-powering of electronic devices, i.e., capturing energy in the environment and converting it into electrical energy for power supply, is almost the best choice for future sustainable power supply technologies. Abundant energy sources exist in nature, such as: the energy acquisition device comprises a thermoelectric power supply, a radio frequency power supply, a photovoltaic power supply, a piezoelectric power supply and the like, wherein the piezoelectric power supply is less limited by natural conditions compared with other energy sources, has higher energy density and is easy to expand, so that an energy acquisition technical scheme based on the piezoelectric power supply is favored.
Generally, the piezoelectric sensor captures vibration energy of the surrounding environment and converts the vibration energy into electric energy, but the output electric energy of the piezoelectric sensor is usually an alternating current source and cannot directly supply power to the electronic device, so a rectifying interface circuit is required before the electronic device is supplied with power. The rectifying interface circuit mainly utilizes the unidirectional conductivity of the diode, so the performance of the adopted diode is very important to influence the performance of the rectifier. The traditional Schottky diode has higher conduction voltage drop and larger conduction loss, so that the rectification efficiency is seriously influenced, and the larger diode conduction voltage drop also limits the input range of the rectification interface circuit.
Therefore, an active diode based on a comparator is provided, the conduction voltage drop of the active diode is reduced, the rectification efficiency is improved to some extent, but the input precision of the comparator is limited, the zero crossing point detection precision of the current of the active diode is low, and therefore the input range of a rectification interface circuit based on the active diode is still limited to a certain extent.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an active diode with a self-adaptive on-resistance.
Specifically, one embodiment of the present invention provides an adaptive on-resistance active diode, including:
a switch tube module 101, a comparator module 102 and a logic and control unit module 103; wherein the content of the first and second substances,
the output end of the switch tube module 101 is electrically connected with the input end of the comparator module 102;
the output end of the comparator module 102 is electrically connected with the input end of the logic and control unit module 103;
the output end of the logic and control unit module 103 is electrically connected with the input end of the switch tube module 101.
In one embodiment of the present invention, the switching transistor module 101 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a seventh PMOS transistor MP 7; wherein the content of the first and second substances,
the source of the first PMOS transistor MP1 is electrically connected to the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7, respectively;
the drain of the first PMOS transistor MP1 is electrically connected to the drain of the second PMOS transistor MP2, the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4, the drain of the fifth PMOS transistor MP5, the drain of the seventh PMOS transistor MP7 and the gate of the sixth PMOS transistor MP6, respectively;
the substrate of the first PMOS transistor MP1 is electrically connected to the substrate of the second PMOS transistor MP2, the substrate of the third PMOS transistor MP3, the substrate of the fourth PMOS transistor MP4, the substrate of the fifth PMOS transistor MP5, the drain and substrate of the sixth PMOS transistor MP6, and the source and substrate of the seventh PMOS transistor MP7, respectively;
the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP5 are electrically connected to the output terminal of the logic and control unit module 103, respectively;
the source of the first PMOS transistor MP1 is electrically connected to the positive input terminal of the comparator module 102 as the ANODE terminal ANODE of the switch tube module 101, and the drain of the first PMOS transistor MP1 is electrically connected to the negative input terminal of the comparator module 102 as the CATHODE terminal CATHODE of the switch tube module 101.
In one embodiment of the present invention, the comparator module 102 comprises a first comparator COMP1 and a second comparator COMP 2; wherein the content of the first and second substances,
a positive input end of the first comparator COMP1 is electrically connected to an ANODE end ANODE of the switch tube module 101, a negative input end is electrically connected to a CATHODE end CATHODE of the switch tube module 101, and an output end is electrically connected to a first input end of the logic and control unit module 103;
a positive input end of the second comparator COMP2 is electrically connected to the ANODE end ANODE of the switch tube module 101, a negative input end thereof is electrically connected to the CATHODE end CATHODE of the switch tube module 101, and an output end thereof is electrically connected to the second input end of the logic and control unit module 103.
In one embodiment of the present invention, the logic and control unit module 103 includes a clock signal logic circuit I1, a counter I2, a decoder I3, a driving circuit module I4; wherein the content of the first and second substances,
the input end of the clock signal logic circuit I1 is electrically connected with the output end of the comparator module 102; the input end of the counter I2 is electrically connected with the output end of the clock signal logic circuit I1; the input end of the decoder I3 is electrically connected with the output end of the counter I2; the input end of the driving circuit module I4 is electrically connected with the output end of the decoder I3, and the output end of the driving circuit module I4 is electrically connected with the input end of the switch tube module 101.
In one embodiment of the present invention, the clock signal logic circuit I1 has a first input terminal VO1 electrically connected to the first output terminal of the comparator module 102, and a second input terminal VO2 electrically connected to the second output terminal of the comparator module 102.
In one embodiment of the invention, the clock signal input terminal CLK2 of the counter I2 is electrically connected with the clock signal output terminal CLK1 of the clock signal logic circuit I1, and the count-up and count-down control terminal V of the counter I2ADDSUB2An addition and subtraction counting control output end V electrically connected with the clock signal logic circuit I1ADDSUB1The clear input RST2 of the counter I2 is electrically connected with the clear output RST1 of the clock signal logic circuit I1.
In one embodiment of the present invention, the counter I2 is a 3-bit counter and the decoder I3 is a 3_5 decoder; the first output QA1 of the 3-bit counter is electrically connected with the first input QA2 of the 3_5 decoder; a second output end QB1 of the 3-bit counter is electrically connected with a second input end QB2 of the 3_5 decoder; and a third output QC1 of the 3-bit counter is electrically connected with a third input QC2 of the 3_5 decoder.
In one embodiment of the present invention, the driving circuit module I4 includes a first driving circuit D1, a second driving circuit D2, a third driving circuit D3, a fourth driving circuit D4, a fifth driving circuit D5; the input ends of the first driving circuit D1, the second driving circuit D2, the third driving circuit D3, the fourth driving circuit D4 and the fifth driving circuit D5 are electrically connected to 5 output ends of the 3_5 decoder, respectively, and the output ends of the first driving circuit D1, the second driving circuit D2, the third driving circuit D3, the fourth driving circuit D4 and the fifth driving circuit D5 are electrically connected to the input end of the switching transistor module 101, respectively.
Compared with the prior art, the invention has the beneficial effects that:
1. under a wide input current range, the dynamic change of the on-resistance of the active diode is realized by utilizing the comparator module and the logic and control unit module, and the on-voltage drop of the active diode can be effectively controlled and reduced, so that the on-loss of the active diode is reduced.
2. The active diode of the self-adaptive on-resistance can effectively improve the zero crossing point detection precision of the current of the active diode in advance without improving the input precision of the comparator.
3. The improvement of the current zero crossing point detection precision of the active diode of the self-adaptive on-resistance effectively widens the input range of the active diode.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a logic diagram of an active diode with adaptive on-resistance according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a switch tube module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a comparator module according to an embodiment of the present invention;
FIG. 4 is a block diagram of a logic and control unit according to an embodiment of the present invention;
fig. 5 is a circuit diagram of an active diode with adaptive on-resistance according to an embodiment of the present invention;
fig. 6 is a schematic diagram of the operation of an adaptive on-resistance active diode according to an embodiment of the present invention in a wide input current variation range;
fig. 7 is an explanatory diagram of operating states of the switch tube corresponding to each stage of the active diode with the adaptive on-resistance according to the embodiment of the invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following detailed description is made with reference to the accompanying drawings and specific embodiments.
The first embodiment is as follows:
referring to fig. 1, fig. 1 is a logic diagram of an active diode with adaptive on-resistance according to an embodiment of the present invention. The active diode of self-adaptation on-resistance includes: a switch tube module 101, a comparator module 102 and a logic and control unit module 103; wherein the content of the first and second substances,
the output end of the switch tube module 101 is electrically connected with the input end of the comparator module 102, and is used for changing a conduction path and limiting the current flowing direction according to the output signal of the logic and control unit module 103;
the output end of the comparator module 102 is electrically connected to the input end of the logic and control unit module 103, and is configured to generate a driving signal acting on the logic and control unit module 103;
the output end of the logic and control unit module 103 is electrically connected to the switching tube module 101, and is used for controlling the operating state of each transistor in the switching tube module 101 through the output signal thereof.
Further, referring to fig. 2, fig. 2 is a circuit schematic diagram of a switch tube module according to an embodiment of the present invention. The switching transistor module 101 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a seventh PMOS transistor MP 7; wherein the content of the first and second substances,
the source of the first PMOS transistor MP1 is electrically connected to the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, and the gate of the seventh PMOS transistor MP7, respectively;
the drain of the first PMOS transistor MP1 is electrically connected to the drain of the second PMOS transistor MP2, the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4, the drain of the fifth PMOS transistor MP5, the drain of the seventh PMOS transistor MP7, and the gate of the sixth PMOS transistor MP6, respectively;
the substrate of the first PMOS transistor MP1 is electrically connected to the substrate of the second PMOS transistor MP2, the substrate of the third PMOS transistor MP3, the substrate of the fourth PMOS transistor MP4, the substrate of the fifth PMOS transistor MP5, the drain and the substrate of the sixth PMOS transistor MP6, and the source and the substrate of the seventh PMOS transistor MP7, respectively;
the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4, and the gate of the fifth PMOS transistor MP5 are electrically connected to the output terminal of the logic and control unit module 103, respectively;
the source of the first PMOS transistor MP1 is used as the ANODE terminal ANODE of the switch module 101 and is electrically connected to the positive input terminal of the comparator module 102, and the drain of the first PMOS transistor MP1 is used as the CATHODE terminal CATHODE of the switch module 101 and is electrically connected to the negative input terminal of the comparator module 102.
In this embodiment, the comparator module 102 is used to detect the voltage drop at the two ends of the switching tube module 101, and the number of switching tubes connected to the current path is dynamically adjusted by the logic and control unit module 103, so as to dynamically adjust the on-resistance of the active diode, thereby ensuring that the on-voltage drop of the active diode is limited in a small range within a wide input current range, and effectively controlling the on-voltage drop of the active diode.
Example two:
in order to facilitate understanding of the working principle of the present invention, the present embodiment will explain the circuit structure of the comparator module 102 and the logic and control unit module 103 in detail on the basis of the above embodiments.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a comparator module according to an embodiment of the present invention. The comparator module 102 comprises a first comparator COMP1 and a second comparator COMP2, wherein,
a positive input end of the first comparator COMP1 is electrically connected to the ANODE end ANODE of the switch tube module 101, a negative input end is electrically connected to the CATHODE end CATHODE of the switch tube module 101, and an output end is electrically connected to the first input end of the logic and control unit module 103;
a positive input end of the second comparator COMP2 is electrically connected to the ANODE end ANODE of the switch tube module 101, a negative input end thereof is electrically connected to the CATHODE end CATHODE of the switch tube module 101, and an output end thereof is electrically connected to the second input end of the logic and control unit module 103.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a logic and control unit module according to an embodiment of the present invention. The logic and control unit module 103 comprises a clock signal logic circuit I1, a counter I2, a decoder I3 and a driving circuit module I4; wherein:
the input end of the clock signal logic circuit I1 is electrically connected with the output end of the comparator module 102; the input end of the counter I2 is electrically connected with the output end of the clock signal logic circuit I1; the input end of the decoder I3 is electrically connected with the output end of the counter I2; the input end of the driving circuit module I4 is electrically connected to the output end of the decoder I3, and the output end of the driving circuit module I4 is electrically connected to the switch tube module 101.
Further, the first input terminal VO1 of the clock signal logic circuit I1 is electrically connected to the first output terminal of the comparator module 102, and the second input terminal VO2 is electrically connected to the second output terminal of the comparator module 102.
In this embodiment, the two comparators 102 are used to detect voltage drops at two ends of the switching tube module 101, and the number of switching tubes connected to the current path is dynamically adjusted by the logic and control unit module 103, so as to dynamically adjust the on-resistance of the active diode, effectively improve the detection accuracy of the current zero crossing point of the active diode, and widen the input range of the active diode.
Example three:
referring to fig. 5, fig. 5 is a circuit schematic diagram of an active diode with adaptive on-resistance according to an embodiment of the present invention. As shown, when the clock signal input terminal CLK2 of the counter I2 is electrically connectedThe clock signal output terminal CLK1 of the clock signal logic circuit I1, which is the up-down count control terminal VADDSUB2An addition and subtraction counting control output end V electrically connected with the clock signal logic circuit I1ADDSUB1The clear input RST2 is electrically connected with the clear output RST1 of the clock signal logic circuit I1.
Further, the counter I2 is a 3-bit counter and the decoder I3 is a 3_5 decoder, wherein the first output QA1 of the 3-bit counter is electrically connected to the first input QA2 of the 3_5 decoder; the second output end QB1 of the 3-bit counter is electrically connected with the second input end QB2 of the 3_5 decoder; the third output QC1 of the 3-bit counter is electrically connected to the third input QC2 of the 3_5 decoder.
Further, the driving circuit module I4 includes a first driving circuit D1, a second driving circuit D2, a third driving circuit D3, a fourth driving circuit D4 and a fifth driving circuit D5, wherein input terminals of the first driving circuit D1, the second driving circuit D2, the third driving circuit D3, the fourth driving circuit D4 and the fifth driving circuit D5 are electrically connected to 5 output terminals of the 3_5 decoder, respectively, and output terminals of the first driving circuit D1, the second driving circuit D2, the third driving circuit D3, the fourth driving circuit D4 and the fifth driving circuit D5 are electrically connected to a gate of a first PMOS transistor MP1, a gate of a second PMOS transistor MP2, a gate of a third PMOS transistor MP3, a gate of a fourth PMOS transistor MP4 and a gate of a fifth PMOS transistor MP5 of the switching transistor module 101, respectively.
Referring now to fig. 6, fig. 6 is a schematic diagram illustrating an operation of an adaptive on-resistance active diode according to an embodiment of the present invention in a wide input current variation range. When the current flowing through the active diode changes, the voltage drop across the active diode is detected by the two comparators COMP1 and COMP2, and when the voltage drop across the active diode exceeds a set voltage drop range, the two comparators COMP1 and COMP2 output signals VO1 and VO2, and the two output signals drive the logic and control unit module to dynamically change the conduction state of the transistors in the switching tube module, so that the dynamic change of the conduction resistance of the active diode is realized.
Specifically, in the stage of increasing the input current ip, the active diode of the self-adaptive on-resistance is initially in an off state, that is, in the first stage Φ 1, at this time, all five PMOS transistors of the switching transistor module 101 are in an off state; with the increase of the input current ip, the voltage drop across the switching tube module 101 increases, when the voltage drop across the switching tube module 101 is greater than the upper limit value of the set voltage drop range, the output signal of the comparator module 102 drives the logic and control unit module 103, the logic and control module 103 generates a control signal and drives the first PMOS transistor MP1 of the switching tube module 101 to be turned on, that is, the second stage Φ 2 is entered; when the voltage drop across the switching tube module 101 is again larger than the upper limit value of the set voltage drop range along with the increase of the input current ip, the output signal of the comparator module 102 drives the logic and control unit module 103, and the logic and control module 103 generates a control signal and drives the second PMOS transistor MP2 of the switching tube module 101 to be turned on, that is, to enter a third stage Φ 3; the conduction of the second PMOS transistor MP2 reduces the on-resistance of the switching transistor module 101, so that the voltage of the active diode falls within a limited voltage drop range; as the input current signal ip continues to increase, when the voltage drop at the two ends of the switching tube module 101 is larger than the upper limit value of the set voltage drop range again, the third PMOS transistor MP3 is immediately turned on to work, that is, the fourth stage Φ 4 is entered, and the voltage drop at the two ends of the switching tube module 101 is reduced to the limited voltage drop range again; as the input current ip increases, the fourth PMOS transistor MP4 is turned on, i.e., enters the fifth phase Φ 5, and the fifth PMOS transistor MP5 is turned on, i.e., enters the sixth phase Φ 6; after that, the input current ip starts to decrease, the voltage drop across the switching tube module 101 also decreases, when the voltage drop across the switching tube module 101 decreases to the lower limit value of the set voltage drop range, the comparator module 102 generates an output signal to drive the logic and control circuit module 103 to generate a control signal, the control signal will make the fifth PMOS transistor MP5 of the active diode return to the off state, i.e. return to the fifth stage Φ 5, the on resistance of the active diode will be increased by turning off the fifth PMOS transistor MP5, so the voltage drop across the switching tube module 101 immediately increases to the set voltage drop range; the input current ip is reduced again, the voltage drop at the two ends of the switching tube module 101 is reduced along with the reduction of the input current, when the voltage drop at the two ends of the switching tube module 101 is reduced to the lower limit value of the set voltage drop range again, the comparator module 102 outputs a signal again and drives the logic and control unit module 103, the control signal enables the fourth PMOS transistor MP4 to return to the off state, namely return to the fourth stage Φ 4, the on-resistance of the switching tube module 101 is increased immediately, and the voltage drop at the two ends of the switching tube module 101 is increased immediately within the set voltage drop range; as the input current continues to decrease, the third PMOS transistor MP3 of the switch transistor module 101 returns to the off state, i.e., to the third phase Φ 3, and the second PMOS transistor MP2 of the switch transistor module 101 returns to the off state, i.e., to the second phase Φ 2, until all the PMOS transistors of the switch transistor module 101 are turned off back to the off state of the active diode, i.e., the first phase Φ 1. With the change of the input current, the on-resistance of the active diode realizes dynamic change, namely the active diode with the self-adaptive on-resistance is formed.
In this embodiment, the first phase Φ 1 corresponds to the input current range: 0-0.05 ip; the second phase Φ 2 corresponds to the input current range: 0.05 ip-0.3 ip; the third phase Φ 3 corresponds to the input current range: 0.3 ip-0.5 ip; the fourth phase Φ 4 corresponds to the input current range: 0.5 ip-0.7 ip; the fifth phase Φ 5 corresponds to the input current range: 0.7 ip-0.9 ip; the sixth phase Φ 6 corresponds to the input current range: 0.9 ip-1 ip, where ip represents the maximum value of the input current range. Different input current variation ranges correspond to different operating phases.
Referring to fig. 7, fig. 7 is an explanatory diagram of operating states of a switch tube corresponding to each stage of an active diode with adaptive on-resistance according to an embodiment of the present invention. As shown, the first phase Φ 1: the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are all in an off state; second phase Φ 2: the first PMOS transistor MP1 is turned on, and the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are all turned off; third stage Φ 3: the first PMOS transistor MP1 and the second PMOS transistor MP2 are in an on state, and the third PMOS transistor MP3, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are in an off state; fourth phase Φ 4: the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are in an on state, and the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are in an off state; fifth phase Φ 5: the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all in an on state, and the fifth PMOS transistor MP5 is in an off state; sixth phase Φ 6: the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are all in a conducting state; in the phase of increasing the input current, the voltage drop of the active diode rises along with the increase of the input current, and once the voltage drop increases to the limited voltage drop upper limit value, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are sequentially changed from the off state to the on state, so that the on resistance of the active diode is reduced, and the on voltage drop of the active diode is effectively reduced; in the input current reduction phase, the voltage drop of the active diode decreases with the reduction of the input current, once the voltage drops to the limited voltage drop lower limit value, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are sequentially changed from the on state to the off state, thereby increasing the on-resistance of the active diode, effectively improving the detection precision of the current zero crossing point of the active diode, increasing the on-resistance of the active diode, maintaining the on-voltage drop of the active diode within a limited voltage drop range, the conduction loss of the self-adaptive on-resistance active diode can be smaller than that of the traditional active diode, the input range of the rectification interface circuit is indirectly widened, and the rectification efficiency of the piezoelectric energy acquisition rectification interface circuit is favorably improved.
The foregoing is a more detailed description of the present invention that is presented in connection with preferred embodiments and is not intended to limit the practice of the invention to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (7)

1. An adaptive on-resistance active diode, comprising:
the device comprises a switch tube module (101), a comparator module (102) and a logic and control unit module (103); wherein the content of the first and second substances,
the output end of the switch tube module (101) is electrically connected with the input end of the comparator module (102);
the output end of the comparator module (102) is electrically connected with the input end of the logic and control unit module (103);
the output end of the logic and control unit module (103) is electrically connected with the input end of the switch tube module (101),
the switching tube module (101) comprises a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6) and a seventh PMOS transistor (MP 7); wherein the content of the first and second substances,
a source of the first PMOS transistor (MP1) is electrically connected to a source of the second PMOS transistor (MP2), a source of the third PMOS transistor (MP3), a source of the fourth PMOS transistor (MP4), a source of the fifth PMOS transistor (MP5), a source of the sixth PMOS transistor (MP6), and a gate of the seventh PMOS transistor (MP7), respectively;
the drain of the first PMOS transistor (MP1) is electrically connected to the drain of the second PMOS transistor (MP2), the drain of the third PMOS transistor (MP3), the drain of the fourth PMOS transistor (MP4), the drain of the fifth PMOS transistor (MP5), the drain of the seventh PMOS transistor (MP7), and the gate of the sixth PMOS transistor (MP6), respectively;
the substrate of the first PMOS transistor (MP1) is electrically connected to the substrate of the second PMOS transistor (MP2), the substrate of the third PMOS transistor (MP3), the substrate of the fourth PMOS transistor (MP4), the substrate of the fifth PMOS transistor (MP5), the drain and substrate of the sixth PMOS transistor (MP6), and the source and substrate of the seventh PMOS transistor (MP7), respectively;
the gate of the first PMOS transistor (MP1), the gate of the second PMOS transistor (MP2), the gate of the third PMOS transistor (MP3), the gate of the fourth PMOS transistor (MP4) and the gate of the fifth PMOS transistor (MP5) are respectively and electrically connected with the output end of the logic and control unit module (103);
the source of the first PMOS transistor (MP1) is electrically connected to the positive input terminal of the comparator module (102) as the ANODE terminal (ANODE) of the switch tube module (101), and the drain of the first PMOS transistor (MP1) is electrically connected to the negative input terminal of the comparator module (102) as the CATHODE terminal (CATHODE) of the switch tube module (101).
2. The adaptive on-resistance active diode of claim 1, wherein the comparator module (102) comprises a first comparator (COMP1) and a second comparator (COMP 2); wherein the content of the first and second substances,
a positive input end of the first comparator (COMP1) is electrically connected with an ANODE end (ANODE) of the switch tube module (101), a negative input end of the first comparator is electrically connected with a CATHODE end (CATHODE) of the switch tube module (101), and an output end of the first comparator is electrically connected with a first input end of the logic and control unit module (103);
the positive input end of the second comparator (COMP2) is electrically connected with the ANODE end (ANODE) of the switch tube module (101), the negative input end of the second comparator is electrically connected with the CATHODE end (CATHODE) of the switch tube module (101), and the output end of the second comparator is electrically connected with the second input end of the logic and control unit module (103).
3. The adaptive on-resistance active diode according to claim 1, wherein the logic and control unit module (103) comprises a clock signal logic circuit (I1), a counter (I2), a decoder (I3), a driving circuit module (I4); wherein:
the input end of the clock signal logic circuit (I1) is electrically connected with the output end of the comparator module (102); the input end of the counter (I2) is electrically connected with the output end of the clock signal logic circuit (I1); the input end of the decoder (I3) is electrically connected with the output end of the counter (I2); the input end of the driving circuit module (I4) is electrically connected with the output end of the decoder (I3), and the output end of the driving circuit module (I4) is electrically connected with the input end of the switch tube module (101).
4. The adaptive on-resistance active diode according to claim 3, wherein the clock signal logic circuit (I1) has a first input terminal (VO1) electrically connected to the first output terminal of the comparator block (102) and a second input terminal (VO2) electrically connected to the second output terminal of the comparator block (102).
5. The adaptive on-resistance active diode according to claim 3, wherein the clock signal input terminal (CLK2) of the counter (I2) is electrically connected to the clock signal output terminal (CLK1) of the clock signal logic circuit (I1), and the up-down count control terminal (V) of the counter (I2)ADDSUB2) An up-down counting control output end (V) electrically connected with the clock signal logic circuit (I1)ADDSUB1) The clear input end (RST2) of the counter (I2) is electrically connected with the clear output end (RST1) of the clock signal logic circuit (I1).
6. The adaptive on-resistance active diode of claim 3, wherein the counter (I2) is a 3-bit counter and the decoder (I3) is a 3_5 decoder; wherein a first output terminal (QA1) of the 3-bit counter is electrically connected to a first input terminal (QA2) of the 3_5 decoder; a second output end (QB1) of the 3-bit counter is electrically connected with a second input end (QB2) of the 3_5 decoder; and a third output end (QC1) of the 3-bit counter is electrically connected with a third input end (QC2) of the 3_5 decoder.
7. The adaptive on-resistance active diode according to claim 6, wherein the driving circuit module (I4) comprises a first driving circuit (D1), a second driving circuit (D2), a third driving circuit (D3), a fourth driving circuit (D4), a fifth driving circuit (D5); wherein, the input terminals of the first driving circuit (D1), the second driving circuit (D2), the third driving circuit (D3), the fourth driving circuit (D4) and the fifth driving circuit (D5) are electrically connected to 5 output terminals of the 3_5 decoder, respectively; the output ends of the first driving circuit (D1), the second driving circuit (D2), the third driving circuit (D3), the fourth driving circuit (D4) and the fifth driving circuit (D5) are respectively electrically connected with the input end of the switch tube module (101).
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