CN107946192B - Tray mechanism for annealing silicon wafer - Google Patents
Tray mechanism for annealing silicon wafer Download PDFInfo
- Publication number
- CN107946192B CN107946192B CN201711339806.3A CN201711339806A CN107946192B CN 107946192 B CN107946192 B CN 107946192B CN 201711339806 A CN201711339806 A CN 201711339806A CN 107946192 B CN107946192 B CN 107946192B
- Authority
- CN
- China
- Prior art keywords
- tray
- silicon wafer
- plate
- conducting
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 82
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 81
- 239000010703 silicon Substances 0.000 title claims abstract description 81
- 238000000137 annealing Methods 0.000 title claims abstract description 28
- 230000007246 mechanism Effects 0.000 title claims abstract description 19
- 235000012431 wafers Nutrition 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000010445 mica Substances 0.000 claims abstract description 4
- 229910052618 mica group Inorganic materials 0.000 claims abstract description 4
- 238000003780 insertion Methods 0.000 claims description 8
- 230000037431 insertion Effects 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68785—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67103—Apparatus for thermal treatment mainly by conduction
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a tray mechanism for annealing silicon wafers, which comprises a plurality of trays stacked together, wherein each tray comprises a silicon wafer positioning plate made of mica, the silicon wafer positioning plate defines a cavity for storing the silicon wafer, a first conductive plate is fixed in the cavity, a conductive column is fixedly connected to the bottom of each metal conductive plate, the other end of each conductive column is fixedly connected with a second conductive plate, and the second conductive plates are used for being in contact conduction with the silicon wafers in the lower trays. The invention can carry out electrifying treatment on the silicon wafer while annealing the silicon wafer, improves the annealing effect, further improves the performance of the silicon wafer and prolongs the service life of the silicon wafer.
Description
Technical Field
The invention relates to the technical field of silicon wafer processing, in particular to a tray mechanism for annealing a silicon wafer.
Background
The silicon wafer contains oxygen, the oxygen has the function of absorbing impurities, the silicon wafer is annealed, the oxygen remained in the silicon can be promoted to diffuse outwards, and a low-oxygen environment (clean area) is formed on the surface of the silicon wafer, so that the crystal defect caused by the oxygen can be reduced or even eliminated, the later device manufacturing is facilitated, and in addition, the resistivity and minority carrier lifetime of the silicon wafer can be influenced by the annealing of the silicon wafer.
It has been found that during the annealing process of the silicon wafer, if the silicon wafer is kept in an electrified state, the annealing effect of the silicon wafer is better, and the silicon wafer has better performance, but no corresponding device is manufactured by the silicon wafer annealing equipment at present, so that the silicon wafer annealing equipment is urgently needed to solve the problem.
Disclosure of Invention
The invention aims to provide a tray mechanism for silicon wafer annealing, which can be used for carrying out electrifying treatment on a silicon wafer while annealing the silicon wafer, so that the annealing effect is improved, the performance of the silicon wafer is further improved, and the service life of the silicon wafer is prolonged.
In order to solve the problems in the prior art, the technical scheme provided by the invention is as follows:
the utility model provides a tray mechanism for silicon chip annealing, includes the tray that a plurality of pile was put together, the tray includes the silicon chip locating plate that the mica was made, and the silicon chip locating plate prescribes a limit to the cavity that is used for depositing the silicon chip be fixed with first conducting plate in the cavity, be fixedly connected with conductive column in the bottom of metal conducting plate, the other end fixedly connected with second conducting plate of conductive column, the second conducting plate is used for switching on with the silicon chip contact in the lower floor's tray.
For the above technical solutions, the inventors have further optimization measures.
Further, the conductive column comprises a bushing, a connecting pin and a spring, wherein the bushing is fixed below the first conductive plate, the connecting pin is in sliding fit with the bushing, the bottom end of the connecting pin is fixedly connected with the second conductive plate, and the spring for providing tension is sleeved on the outer side of the connecting pin.
Further, a plurality of independent cavities for storing silicon chips are arranged in the tray, through holes penetrating up and down are formed in the silicon chip locating plate beside each cavity, conductive metal electrically connected with the first conductive plate in the adjacent cavity is arranged in the through holes of the tray at the bottom to form conductive holes, the tray mechanism further comprises a plurality of electrode connecting rods, each electrode connecting rod vertically penetrates through the through holes in the plurality of upper-layer trays and is finally inserted into the conductive holes, and each electrode connecting rod is electrically connected with the first conductive plate in one cavity in the tray at the bottom to form an independent power-on loop.
Further, the silicon chip in the upper tray at the top is electrically connected with the outside, and the silicon chip, the first conductive plate, the conductive column, the second conductive plate and the electrode connecting rod in the corresponding cavity on each tray form an independent power-on loop.
Further, the tray comprises a bottom tray and a plurality of upper trays stacked on the bottom tray, wherein the lower part of the bottom tray is a flat plate base, jacks are arranged at four corners of the bottom tray, positioning columns capable of being inserted into the jacks are arranged at the lower part of the upper tray corresponding to the positions of the jacks, and the jacks are also arranged at four corners of the upper tray.
Still further, the tray mechanism also includes a workpiece cover plate that is pressed against the silicon wafer in the tray at the top layer.
Compared with the solutions in the prior art, the invention has the advantages that:
according to the invention, the silicon wafers placed between the layers are connected in series through the conductive plates on the trays of each layer, and then the electrode connecting rods communicated with the conductive plates of the tray at the bottommost are combined to form the power-on loop communicated with an external power supply, so that the silicon wafers can be annealed while keeping the power-on state, the annealing effect of the silicon wafers is improved, the performance of the silicon wafers is improved, and the product competitiveness is improved.
In addition, the conductive columns and the second conductive plates arranged at the bottom of the upper tray can be tightly connected with the silicon wafers on the two adjacent trays in series, so that the connection reliability is improved, and the device is applicable to silicon wafers with different numbers and different thicknesses and has strong adaptability.
Drawings
The invention is further described below with reference to the accompanying drawings and examples:
FIG. 1 is a schematic view showing the overall structure of a tray mechanism for annealing a silicon wafer according to an embodiment of the present invention;
FIG. 2 is a schematic view of the structure of a bottom tray in the tray mechanism for annealing silicon wafers shown in FIG. 1;
FIG. 3 is a schematic cross-sectional view of the bottom tray of FIG. 2;
FIG. 4 is a schematic view of the structure of the upper tray in the tray mechanism for annealing silicon wafers shown in FIG. 1;
fig. 5 is a schematic cross-sectional view of the bottom tray of fig. 2.
Wherein:
1. a tray; 11. a jack; 12. positioning columns; 2. a bottom tray; 21. conductive holes for fixing the electrode connecting rods; 3. an upper tray; 31. a through hole for penetrating the electrode connecting rod; 4. a silicon wafer; 5. a first conductive plate; 6. a conductive post; 61. a bushing; 62. a connecting pin; 63. a spring; 7. a second conductive plate; 8. an electrode connecting rod; 9. a silicon wafer positioning plate; 10. and a workpiece cover plate.
Detailed Description
The above-described aspects are further described below in conjunction with specific embodiments. It should be understood that these examples are illustrative of the present invention and are not intended to limit the scope of the present invention. The implementation conditions used in the examples may be further adjusted according to the conditions of the specific manufacturer, and the implementation conditions not specified are generally those in routine experiments.
Examples:
this embodiment describes a tray mechanism for annealing silicon wafers, as shown in fig. 1, which may generally include a plurality of trays 1 stacked together, where the trays 1 include a silicon wafer positioning plate 9 made of mica, the silicon wafer positioning plate 9 defines a cavity for storing the silicon wafer 4, a first conductive plate 5 is fixed in the cavity, a conductive column 6 is fixedly connected to the bottom of the metal conductive plate, and a second conductive plate 7 is fixedly connected to the other end of the conductive column 6, where the second conductive plate 7 is used for contact conduction with the silicon wafer 4 in the lower tray.
Specifically, the tray 1 includes a bottom tray 2 and a plurality of upper trays 3 stacked on the bottom tray 2, a flat plate base is disposed below the bottom tray 2, as shown in fig. 2 and 3, insertion holes 11 are disposed at four corners of the bottom tray 2, positioning columns 12 capable of being inserted into the insertion holes 11 are disposed at positions, corresponding to the insertion holes 11, below the upper trays 3, as shown in fig. 4 and 5, and insertion holes 11 are also disposed at four corners above the upper trays 3.
Each tray 1 is provided with a plurality of independent cavities for storing silicon wafers 4, and a silicon wafer positioning plate 9 beside each cavity is provided with a through hole 31 penetrating up and down. As shown in fig. 2 and 3, the through holes 31 of the bottom tray 2 at the lowest layer are provided with conductive holes 21 formed by conductive metal electrically connected with the first conductive plates 5 in the adjacent cavities, the tray mechanism further comprises a plurality of electrode connecting rods 8, each electrode connecting rod 8 vertically passes through the through holes 31 on the plurality of upper trays 3 and finally is inserted into the conductive holes 21, wherein each electrode connecting rod 8 is electrically connected with the first conductive plate 5 in one cavity in the bottom tray 2, the silicon wafer 4 in the upper tray 3 at the top is electrically connected with the outside, and the silicon wafer 4, the first conductive plate 5, the conductive posts 6, the second conductive plate 7 and the electrode connecting rods 8 in the corresponding cavities (in the same vertical plane) on each tray 1 form independent power-on circuits
That is, a plurality of independent energizing loops can be constructed in the tray mechanism, namely, silicon wafers 4 placed between layers are connected in series through corresponding conductive plates on each layer of tray 1, current is accessed from the silicon wafers 4 to be processed on the top layer, and finally, the current is led out from an electrode connecting rod 8 communicated with the conductive plate of the bottom tray 2 on the lowest layer to form an energizing loop which is conducted, so that the annealing of the silicon wafers 4 can be kept in the energizing state, the annealing effect of the silicon wafers is improved, the performance of the silicon wafers is improved, and finally, the improvement of the product quality is realized. The arrangement of the multi-cavity structure in the tray 1 enables a large number of silicon wafers to be annealed and electrified at one time, improves the processing efficiency and saves the production cost.
The structure of the conductive posts 6 is also specially designed in order to enable the silicon wafers 4 placed between two adjacent trays 1 to be tightly connected. The conductive post 6 comprises a bushing 61, a connecting pin 62 and a spring 63, the bushing 61 is fixed below the first conductive plate 5, the connecting pin 62 is in sliding fit with the bushing 61, the bottom end of the connecting pin 62 is fixedly connected with the second conductive plate 7, the spring 63 for providing tension is sleeved on the outer side of the connecting pin 62, one end of the spring 63 abuts against the second conductive plate 7, and the other end abuts against the bushing 61. Through using spring 63 to press the second current-conducting plate 7 of upper tray 3 bottom on lower floor's silicon chip 4, guarantee not shift in the silicon chip annealing and the stability of whole return circuit when circular telegram, but overlap joint formula structural design for can carry out the stack equipment of multilayer tray 1, improve work efficiency.
The conductive column 6 and the second conductive plate 7 arranged at the bottom of the upper tray 3 can be tightly connected with the silicon wafers 4 on the two adjacent trays 1 in series, so that the connection reliability is improved, and the device is applicable to silicon wafers 4 with different numbers and different thicknesses and has strong adaptability and adjustability
In order to ensure the smoothness of the annealing process and prevent the silicon wafer 4 from falling off, the tray mechanism further comprises a workpiece cover plate 10, wherein the workpiece cover plate 10 is pressed on the silicon wafer 4 in the tray positioned on the top layer.
The above examples are provided for illustrating the technical concept and features of the present invention and are intended to enable those skilled in the art to understand the contents of the present invention and to implement the same, and are not intended to limit the scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be included in the scope of the present invention.
Claims (4)
1. The tray mechanism for annealing the silicon wafers comprises a plurality of trays stacked together, wherein each tray comprises a bottom tray and a plurality of upper trays stacked on the bottom tray, and is characterized in that each tray comprises a silicon wafer positioning plate made of mica, the silicon wafer positioning plates define a cavity for storing the silicon wafers, a first conducting plate is fixed in the cavity, a conducting column is fixedly connected to the bottom of the first conducting plate of the upper tray, the other end of the conducting column is fixedly connected with a second conducting plate, the second conducting plate is used for being in contact conduction with the silicon wafers in the lower tray, a plurality of independent cavities for storing the silicon wafers are arranged in the trays, through holes penetrating up and down are formed in the silicon wafer positioning plates beside each cavity, conducting metal electrically connected with the first conducting plates in the adjacent cavities form conducting holes in the through holes of the tray at the bottom, each electrode connecting rod vertically penetrates through the through holes in the upper trays and is finally inserted in the conducting holes, and each electrode connecting rod is electrically connected with the corresponding electrode connecting rod in the corresponding to the first conducting plate, the electrode connecting rod and the upper tray, and the electrode connecting rod is electrically connected with the electrode connecting rod in the corresponding to the cavity in the cavity.
2. The tray mechanism for annealing silicon wafers according to claim 1, wherein the conductive column comprises a bushing, a connecting pin and a spring, the bushing is fixed below the first conductive plate, the connecting pin is in sliding fit with the bushing, the bottom end of the connecting pin is fixedly connected with the second conductive plate, and the spring for providing tension is sleeved outside the connecting pin.
3. The tray mechanism for annealing silicon wafers according to any one of claims 1 to 2, wherein the tray comprises a bottom tray and a plurality of upper trays stacked on the bottom tray, wherein the lower part of the bottom tray is a flat plate base, the four corners of the bottom tray are provided with insertion holes, the lower part of the upper tray is provided with positioning columns which can be inserted into the insertion holes corresponding to the insertion holes, and the four corners above the upper tray are also provided with insertion holes.
4. A wafer annealing tray mechanism according to claim 3, further comprising a workpiece cover plate that is pressed against the wafer in the tray at the top layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711339806.3A CN107946192B (en) | 2017-12-14 | 2017-12-14 | Tray mechanism for annealing silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711339806.3A CN107946192B (en) | 2017-12-14 | 2017-12-14 | Tray mechanism for annealing silicon wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107946192A CN107946192A (en) | 2018-04-20 |
| CN107946192B true CN107946192B (en) | 2024-03-12 |
Family
ID=61944119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711339806.3A Active CN107946192B (en) | 2017-12-14 | 2017-12-14 | Tray mechanism for annealing silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107946192B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110018279A (en) * | 2019-04-26 | 2019-07-16 | 西安奕斯伟硅片技术有限公司 | A kind of detection method and device of Defect |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003113421A (en) * | 2001-10-03 | 2003-04-18 | Hitachi Ltd | Excitation annealing system, tray for transportation and excitation annealing furnace |
| CN104071972A (en) * | 2014-07-24 | 2014-10-01 | 景丽 | Quartz glass annealing furnace |
| CN207542198U (en) * | 2017-12-14 | 2018-06-26 | 苏州晶洲装备科技有限公司 | Wafer anneal pallet body |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI509698B (en) * | 2013-12-25 | 2015-11-21 | Ind Tech Res Inst | Sample holder for annealing apparatus and electrically assisted annealing apparatus using the same |
-
2017
- 2017-12-14 CN CN201711339806.3A patent/CN107946192B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003113421A (en) * | 2001-10-03 | 2003-04-18 | Hitachi Ltd | Excitation annealing system, tray for transportation and excitation annealing furnace |
| CN104071972A (en) * | 2014-07-24 | 2014-10-01 | 景丽 | Quartz glass annealing furnace |
| CN207542198U (en) * | 2017-12-14 | 2018-06-26 | 苏州晶洲装备科技有限公司 | Wafer anneal pallet body |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107946192A (en) | 2018-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8546938B2 (en) | Stacked package including spacers and method of manufacturing the same | |
| US20140144676A1 (en) | Electronic component embedded substrate and manufacturing method thereof | |
| JP6195372B2 (en) | socket | |
| CN105826306A (en) | Chip package, package substrate and manufacturing method | |
| TW200503064A (en) | Method for manufacturing semiconductor package | |
| CN107946192B (en) | Tray mechanism for annealing silicon wafer | |
| US8928150B2 (en) | Multi-chip package and method of manufacturing the same | |
| KR20130020629A (en) | Presspin, power semiconducter module and semiconducter module assembly with multiple power semiconducter modules | |
| US8659383B2 (en) | Magnetic member | |
| CN207542198U (en) | Wafer anneal pallet body | |
| EP1961043B1 (en) | Universal pad arrangement for surface mounted semiconductor devices | |
| CN103325712B (en) | IGBT module welded encapsulation servicing unit and system | |
| US11112452B2 (en) | IC tray and test jig | |
| CN206764057U (en) | A kind of circuit board soldering tin fixture | |
| CN205984937U (en) | Hold diode that increases chip | |
| CN102468196A (en) | Discrete circuit component having copper block electrodes and method of fabrication | |
| CN215511009U (en) | Tray for semiconductor integrated circuit in small household appliance | |
| CN219979516U (en) | Material pouring jig | |
| US10371719B2 (en) | Printed circuit board circuit test fixture with adjustable density of test probes mounted thereon | |
| JP3781575B2 (en) | Conductive ball mounting apparatus and mounting method | |
| US20090284266A1 (en) | Test method and device for land grid array components | |
| CN210325535U (en) | Laminated ceramic capacitor | |
| US11887976B2 (en) | Land-side silicon capacitor design and semiconductor package using the same | |
| CN214011298U (en) | Supporting mechanism and inductance testing device | |
| KR101578599B1 (en) | Table for receiving semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |