CN107944112A - A kind of method and system of RES(rapid evaluation system) high-speed link risk point - Google Patents
A kind of method and system of RES(rapid evaluation system) high-speed link risk point Download PDFInfo
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- CN107944112A CN107944112A CN201711140363.5A CN201711140363A CN107944112A CN 107944112 A CN107944112 A CN 107944112A CN 201711140363 A CN201711140363 A CN 201711140363A CN 107944112 A CN107944112 A CN 107944112A
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- speed link
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q10/00—Administration; Management
- G06Q10/06—Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
- G06Q10/063—Operations research, analysis or management
- G06Q10/0635—Risk analysis of enterprise or organisation activities
Abstract
The invention discloses a kind of method and system of RES(rapid evaluation system) high-speed link risk point, including the interconnection model of high-speed link is created, and the configuration information of link is imported in knot interconnection model, form the interconnection topological structure of high-speed link；The insertion loss of each subassembly unit of high-speed link is extracted from interconnection topological structure, calculates full link channel total losses；Compared with the full link channel total losses are estimated Insertion Loss value with link, the full link risk class of design link is obtained.The present invention is capable of the risk class of rapid evaluation high-speed link, improves link evaluation risk accuracy, excludes the link design risk hidden danger only brought with subjective experience assessment, improves the success rate of product design and development.
Description
Technical field
The present invention relates to field of computer technology, specifically a kind of side of RES(rapid evaluation system) high-speed link risk point
Method and system.
Background technology
In Server product system designs, because mainboard and supporting attached daughter board exploitation quantity are more, there are outer on mainboard
The high-speed I/O bus type of expansion is more and alignment system interconnects the problems such as more complicated.
In mainboard high speed cabling SI designing quality risk assessment, the method for generally use is：Signal simulation simulation assessment
Or use for reference and developed the progress high-speed link risk assessment of similar products case test data.But set in Purley platform products
During meter exploitation, because project development progress itself is more nervous, when can not meet current project progress using signal simulation analogy method
Between require, for 3.5x4SATA backpanel links design of being arranged in pairs or groups to mainboard by 750mm cable, use for reference previous generation Grantley and put down
Similar interconnecting link designs on platform, and the testing SA TA3.0 eye diagram quality Pass data that re-pack.
Thus, subjectivity thinks that current ink risk is controllable.But each board of this product plate of drawing a design back carries out SIV (Signal
Integration Validation, measuring signal integrality) test when, find mainboard collocation 3.5x4 backboards SATA3.0 test
Eye pattern fail, excludes through debug, and it is the cable components that two platforms use to determine question classification, though track lengths are the same, rule
Lattice are different, its loss differs 1.5dB under 3GHz frequency points.When thus explanation project is designed and developed, limited in some condition elements
And when uncertain, for the assessment of high speed alignment system link, continuing to use Traditional measurements means can not preferably walk at a high speed in management and control
Wired link risk, can bring uncertain influence to product development cycle and designing quality.
The content of the invention
It is an object of the invention to provide a kind of method and system of RES(rapid evaluation system) high-speed link risk point, for solving
Certainly in research and development of products, can not preferably management and control high speed inter-connection links risk the problem of.
The technical solution adopted by the present invention to solve the technical problems is：A kind of RES(rapid evaluation system) high-speed link risk
Method, comprises the following steps：
The interconnection model of high-speed link is created, and the configuration information of link is imported in knot interconnection model, forms high-speed chain
The interconnection topological structure on road；
The insertion loss of each subassembly unit of high-speed link is extracted from interconnection topological structure, full link channel is calculated and always damages
Consumption；
Compared with the full link channel total losses are estimated Insertion Loss value with link, the full chain transportation work style of design link is obtained
Dangerous grade.
Further, the method further includes the step of link high to risk class carries out signal simulation simulation assessment.
Further, the interconnection model of high-speed link described in word processing instrument creation is passed through.
Further, the word processing instrument is Excel.
Further, the interconnection model include be sequentially connected with according to link mainboard, the first cable connectors,
Cable, the 2nd cable connectors, chain channel platform, hard disk connector and hard disk.
Further, the configuration information of the link include chain channel platform, consensus standard, each subassembly unit of link insert
Enter the unit insertion loss of loss, the length of cable and cable.
Further, by summing to the insertion loss of each subassembly unit of high-speed link, full link channel damage is calculated
Consumption.
The embodiment of the present invention additionally provides a kind of system of RES(rapid evaluation system) high-speed link risk, including information is located in advance
Manage module, computing module and comparing module；
Described information pretreatment module is used for the interconnection model for creating high-speed link, and the configuration information of link is imported knot
In interconnection model, the interconnection topological structure of high-speed link is formed；
The computing module is used for from interconnection topological structure the insertion loss for extracting each subassembly unit of high-speed link, meter
Calculate full link channel total losses；
The comparing module is used for compared with the full link channel total losses are estimated Insertion Loss value with link, draws and sets
Count the full link risk class of link.
Further, the system also includes emulation module, the emulation module be used for the link high to risk class into
The simulation assessment of row signal simulation.
The effect provided in the content of the invention is only the effect of embodiment, rather than whole effects that invention is all, above-mentioned
A technical solution in technical solution has the following advantages that or beneficial effect：
1st, by the interconnection topological structure of word processing instrument creation high-speed link, and according to each subassembly unit in link
Insertion loss quickly calculate the total losses of full link, be capable of the risk class of rapid evaluation high-speed link, improve link and comment
Estimate risk accuracy, exclude the link design risk hidden danger only brought with subjective experience assessment, improve product design and development
Success rate.
2nd, signal simulation simulation and the Improving advice that proposes a plan are carried out for excessive risk link, shorten in project development by
The time required to a high-speed link Simulation Evaluation.
Brief description of the drawings
Fig. 1 is the flow chart of the method for the invention embodiment 1；
Fig. 2 is the interconnection topology to Grantley platform motherboards collocation 3.5x4 backpanel links using the method for the invention
Structure diagram；
Fig. 3 is to the interconnection topology to Purley platform motherboards collocation 3.5x4 backpanel links using the method for the invention
Structure diagram；
Fig. 4 is the flow chart of the method for the invention embodiment 2；
Fig. 5 is the system structure diagram of the present invention.
Embodiment
In order to clarify the technical characteristics of the invention, below by embodiment, and its attached drawing is combined, to this hair
It is bright to be described in detail.Following disclosure provides many different embodiments or example is used for realizing the different knots of the present invention
Structure.In order to simplify disclosure of the invention, hereinafter the component and setting of specific examples are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relation between various embodiments are discussed and/or are set.It should be noted that illustrated component is not necessarily to scale in the accompanying drawings
Draw.Present invention omits the description to known assemblies and treatment technology and process to avoid the present invention is unnecessarily limiting.
As shown in Figure 1, a kind of method of RES(rapid evaluation system) high-speed link risk of the present invention, comprises the following steps：
S1, creates the interconnection model of high-speed link, and the configuration information of link is imported in knot interconnection model, is formed at a high speed
The interconnection topological structure of link；
S2, the insertion loss of each subassembly unit of high-speed link is extracted from interconnection topological structure, calculates full link channel
Total losses；
S3, compared with the full link channel total losses are estimated Insertion Loss value with link, obtains the full chain of design link
Road risk class.
In step S1, by the interconnection model of word processing instrument creation high-speed link, interconnection model is included according to design
Mainboard that the link of product is sequentially connected with, the first cable connectors, cable, the 2nd cable connectors, chain channel platform,
Hard disk connector and hard disk.The configuration information of link includes the insertion damage of chain channel platform, consensus standard, each subassembly unit of link
The unit insertion loss of consumption, the length of cable and cable.
In step S2, by summing to the insertion loss of each subassembly unit of high-speed link, it is total to calculate full link channel
Loss.
In step S3, compared with the full link channel total losses calculated in step S2 are estimated loss with link, if
Loss is estimated less than link, then the risk class of design link is low, and loss is estimated if more than link, then designs risk etc. of link
Level is high, and high outgoing link estimates that loss is more, then the risk class for designing link is higher.
As shown in Fig. 2, utilize the method for above-described embodiment, the 3.5x4 backboards of arranging in pairs or groups to Grantley platform motherboards of establishment
The interconnection topological structure of link, including sequentially connected MB (main board, mainboard), HD minisas connector cables
Connector, specification for HD minisas interface 30awg line footpaths, the cable of 750mm length, HD minisas connector,
Grantley platforms, SMT SAS connector hard disk connectors and HDD hard disks, and in the correspondence position of each subassembly unit
Corresponding attribute information is imported, such as the impedance (impedance) of cable is 100ohm, whole cable waste (total
Loss) PCB CONN VIA loss (PCB, the Printed Circuit for being 2.932, HD minisas connector
Board, printed circuit board；CONN, connector, connector；VIA, via；Loss, loss) it is 0.2.And list design chain
The correspondence consensus standard on road, require loss (loss requirements), design loss (design channel loss), be
It is no to meet standard requirement and risk class, facilitate tester quickly to know the information of design link.
As shown in figure 3, utilize the method for above-described embodiment, the 3.5x4 backboard chains of arranging in pairs or groups to Purley platform motherboards of establishment
The interconnection topological structure on road, it is similar with Fig. 2 contents, no longer this figure is described in detail herein.By shown in Fig. 2 and Fig. 3
Interconnection topological structure can be seen that the mainboard for being directed to different platform in time, can be used the method progress of the embodiment of the present invention high
The assessment of speed chain circuit risk point, universality is strong, and operating personnel are easy to use, compensate for being limited by some conditions and uncertain factor
Influence the accuracy of high-speed link risk assessment.
As shown in figure 4, on the basis of above-described embodiment, step is further included：S4, the link higher to risk class carry out
Signal simulation simulation assessment.The assessment of signal simulation simulation herein can be achieved using emulation mode of the prior art.But upper
On the basis of stating embodiment, the link higher to risk, which wakes up with a start analogue simulation assessment, can accurately obtain the design link a certain
The loss of frequency, has more accurate control to design link, and shortens in project development high-speed link Simulation Evaluation one by one
Required time.
As shown in figure 5, the invention also discloses a kind of system of RES(rapid evaluation system) high-speed link risk, including connect successively
Information pre-processing module 1, computing module 2, comparing module 3 and the emulation module 4 connect.
Information pre-processing module 1 is used for the interconnection model for creating high-speed link, and the configuration information of link is imported knot mutually
In gang mould type, the interconnection topological structure of high-speed link is formed；Computing module 2 is used to extract high-speed link from interconnection topological structure
The insertion loss of each subassembly unit, calculates full link channel total losses；Comparing module 3 is used to always damage the full link channel
Compared with consumption estimates Insertion Loss value with link, the full link risk class of design link is drawn；Emulation module 4 is used for risk etc.
The high link of level carries out signal simulation simulation assessment.
The above is the preferred embodiment of the present invention, for those skilled in the art,
Without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications are also regarded as this hair
Bright protection domain.
Claims (9)
1. a kind of method of RES(rapid evaluation system) high-speed link risk, it is characterized in that：Comprise the following steps：
The interconnection model of high-speed link is created, and the configuration information of link is imported in knot interconnection model, forms high-speed link
Interconnect topological structure；
The insertion loss of each subassembly unit of high-speed link is extracted from interconnection topological structure, calculates full link channel total losses；
Compared with the full link channel total losses are estimated Insertion Loss value with link, full link risk of design link etc. is obtained
Level.
2. according to the method described in claim 1, it is characterized in that：The method further includes the link high to risk class and carries out letter
The step of number analogue simulation assessment.
3. method according to claim 1 or 2, it is characterized in that：Pass through high-speed link described in word processing instrument creation
Interconnection model.
4. according to the method described in claim 3, it is characterized in that：The word processing instrument is Excel.
5. method according to claim 1 or 2, it is characterized in that：The interconnection model includes successively connecting according to link order
Mainboard, the first cable connectors, cable, the 2nd cable connectors, chain channel platform, hard disk connector and the hard disk connect.
6. method according to claim 1 or 2, it is characterized in that：The configuration information of the link includes chain channel platform, agreement
Insertion loss, the length of cable and the unit insertion loss of cable of each subassembly unit of standard, link.
7. method according to claim 1 or 2, it is characterized in that：Damaged by the insertion to each subassembly unit of high-speed link
Consumption summation, calculates full link channel loss.
8. a kind of system of RES(rapid evaluation system) high-speed link risk, it is characterized in that：Including information pre-processing module, computing module
And comparing module；
Described information pretreatment module is used for the interconnection model for creating high-speed link, and the configuration information of link is imported knot interconnection
In model, the interconnection topological structure of high-speed link is formed；
The computing module is used for from interconnection topological structure the insertion loss for extracting each subassembly unit of high-speed link, calculates complete
Link channel total losses；
The comparing module is used for compared with the full link channel total losses are estimated Insertion Loss value with link, draws design chain
The full link risk class on road.
9. system according to claim 8, it is characterized in that：The system also includes emulation module, the emulation module is used
Assessed in carrying out signal simulation simulation to the high link of risk class.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711140363.5A CN107944112A (en) | 2017-11-16 | 2017-11-16 | A kind of method and system of RES(rapid evaluation system) high-speed link risk point |
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| CN201711140363.5A CN107944112A (en) | 2017-11-16 | 2017-11-16 | A kind of method and system of RES(rapid evaluation system) high-speed link risk point |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109085489A (en) * | 2018-07-26 | 2018-12-25 | 烽火通信科技股份有限公司 | A kind of backboard function test system, design method and test method |
| CN109086546A (en) * | 2018-08-22 | 2018-12-25 | 郑州云海信息技术有限公司 | Signal link signal quality evaluating method, device, equipment and readable storage medium storing program for executing |
| CN111475355A (en) * | 2020-03-20 | 2020-07-31 | 苏州浪潮智能科技有限公司 | High-speed link signal integrity evaluation method, system, terminal and storage medium |
| CN113626824A (en) * | 2021-06-30 | 2021-11-09 | 苏州浪潮智能科技有限公司 | Whole machine system link risk assessment method, device, equipment and readable medium |
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| CN113626824A (en) * | 2021-06-30 | 2021-11-09 | 苏州浪潮智能科技有限公司 | Whole machine system link risk assessment method, device, equipment and readable medium |
| CN113626824B (en) * | 2021-06-30 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Whole machine system link risk assessment method, device, equipment and readable medium |
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