CN106202824B - The determination method of line impedence is walked in a kind of PCIE link - Google Patents
The determination method of line impedence is walked in a kind of PCIE link Download PDFInfo
- Publication number
- CN106202824B CN106202824B CN201610607012.XA CN201610607012A CN106202824B CN 106202824 B CN106202824 B CN 106202824B CN 201610607012 A CN201610607012 A CN 201610607012A CN 106202824 B CN106202824 B CN 106202824B
- Authority
- CN
- China
- Prior art keywords
- impedance
- line impedence
- target
- standard
- walked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 230000005540 biological transmission Effects 0.000 claims abstract description 76
- 230000008054 signal transmission Effects 0.000 claims description 8
- 235000007164 Oryza sativa Nutrition 0.000 claims description 6
- 235000009566 rice Nutrition 0.000 claims description 6
- 241000208340 Araliaceae Species 0.000 claims description 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims description 2
- 235000003140 Panax quinquefolius Nutrition 0.000 claims description 2
- 235000008434 ginseng Nutrition 0.000 claims description 2
- 240000007594 Oryza sativa Species 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 241000209094 Oryza Species 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The present invention provides a kind of determination methods that line impedence is walked in PCIE link, this method comprises: determining that PCIE link Plays walk line impedence and standard connector impedance；According to the standard trace impedance and the standard connector impedance, at least one standard transmission parameter of PCIE signal is obtained；It determines target connector impedance, and determines that line impedence is walked at least one reference according to the target connector impedance and the standard trace impedance；According to each with reference to line impedence and the target connector impedance is walked, the corresponding reference transmission parameter of PCIE signal is obtained respectively；According at least one reference transmission parameter and the standard transmission parameter, and according to described at least one with reference to line impedence is walked, determines and final walk line impedence.This programme can effectively guarantee the integrality of PCIE signal in link.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of PCIE (newest bus and interface standard) link
In walk the determination method of line impedence.
Background technique
Along with the arrival of cloud computing, server quickly grows emergence, in the board design of server, signal rate
Higher and higher, demand of the high speed signal to signal integrity is also constantly being promoted.
In existing PCIE link design, generally PCIE signal and SAS signal common connector can be subjected to signal
Transmission.Under normal conditions, what PCIE signal used walks line impedence, from SAS signal use to walk line impedence different, due to SAS letter
Number speed ratio PCIE signal rate is high, uses the connector of 100ohm impedance, generally in the prior art to guarantee in PCIE link
The integrality of middle SAS signal.
However, causing the difference for walking line impedence Yu connector impedance of PCIE signal, therefore, the prior art is possibly can not
Guarantee the integrality of PCIE signal.
Summary of the invention
The embodiment of the invention provides a kind of determination methods that line impedence is walked in PCIE link, can effectively ensure that PCIE
The integrality of signal.
The determination method of line impedence is walked in a kind of PCIE link, comprising:
Determine that PCIE link Plays walk line impedence and standard connector impedance；
According to the standard trace impedance and the standard connector impedance, the standard transmission parameter of PCIE signal is obtained；
It determines target connector impedance, and is determined according to the target connector impedance and the standard trace impedance
Line impedence is walked at least one reference；
According to each with reference to line impedence and the target connector impedance is walked, PCIE signal is obtained respectively and is referred to accordingly
Configured transmission；
It is walked according at least one reference transmission parameter and the standard transmission parameter, and according at least one reference
Line impedence determines and finally walks line impedence.
Preferably, described to determine that at least one reference is walked according to the target connector impedance and the standard trace impedance
Line impedence, comprising:
At least one impedance value between the target connector impedance and the standard trace impedance is selected, it will be every
One impedance value is determined as each reference and walks line impedence.
Preferably, described according at least one reference transmission parameter and the standard transmission parameter, and according to it is described extremely
It is few a kind of with reference to line impedence is walked, it determines and finally walks line impedence, comprising:
Each reference transmission parameter is compared with the standard transmission parameter respectively；
According to comparison result determination and the smallest object reference configured transmission of the standard transmission parameter error；
Line impedence is walked according at least one reference, determines target ginseng corresponding with the object reference configured transmission
Number walks line impedence；
Preferably, further comprise: determining error threshold；
Further comprise: walking line impedence for each target, perform the following operations respectively: calculating the target cabling resistance
Resist at least one corresponding error impedance, the target is walked into line impedence and the target walks at least one corresponding mistake of line impedence
Poor impedance is grouped as one；Wherein, it includes the standard trace impedance and/or described with reference to cabling that the target, which walks line impedence,
Impedance.
Preferably, the standard transmission parameter for obtaining PCIE signal, comprising: for where the standard trace impedance points
Each normal impedance for including in group obtains each normal impedance artificial eye corresponding with the standard connector impedance
Peye；
It is described that line impedence and the target connector impedance are walked according to each reference, it is corresponding that PCIE signal is obtained respectively
Reference transmission parameter, comprising: walk line impedence for each current reference and perform the following operations respectively: it is directed to the current reference
Each reference impedance for including in grouping where walking line impedence, obtains each reference impedance and the target connector impedance
Corresponding Peye.
Preferably, Peye is calculated by the first formula:
First formula includes:
Wherein, P is grouped corresponding Peye for characterizing where the target walks line impedence；PnIt is walked for characterizing the target
Line impedence the corresponding Peye of n-th of impedance in a packet；xnFor characterizing PnWeight.
Preferably, further comprise: grouping with reference to where walking line impedence for each is determined and is wrapped in each grouping
The corresponding signal integrity rate of each impedance included is hindered the corresponding impedance of peak signal percentage of head rice as the final cabling
It is anti-；
Wherein, the corresponding signal integrity rate of each impedance included in each grouping is determined by the second formula；
Second formula includes:
Wherein, ω is for characterizing signal integrity rate；PMarkIt is corresponding for grouping where characterizing the standard trace impedance
Peye。
Preferably, described each normal impedance of drafting is executed using Hspice and the standard connector impedance is right respectively
The standard signal transmitted waveform answered；And/or described each reference impedance of drafting is executed using Hspice and is connect with the target
The corresponding reference signal transmission waveform of device impedance.
Preferably, the error threshold includes: 10%；
And/or
The calculating target walks at least one corresponding error impedance of line impedence, comprising: determine target zone, it is described
Target zone includes first end and second end；Selected in the target zone at least one impedance value as it is described at least one
Error impedance；It does not include that the target walks line impedence at least one described error impedance.
The embodiment of the invention provides a kind of determination methods that line impedence is walked in PCIE link, and this method is in PCIE link
In on the basis of standard trace impedance and standard connector impedance, walk line impedence and standard connector by obtaining respective standard and hinder
Standard transmission parameter in anti-situation.Then in PCIE link, by changing connector impedance and determining at least one reference
Line impedence is walked, and is obtained at least one with reference to biography under the impedance of respective objects connector and at least one impedance conditions with reference to cabling
Defeated parameter.Finally according to standard transmission parameter and reference transmission parameter, determines and final walk line impedence.Therefore, it is emulated by this
What link determined walks line impedence, can effectively ensure that the integrality of PCIE signal.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is the flow chart that the determination method of line impedence is walked in a kind of PCIE link provided by one embodiment of the present invention；
Fig. 2 is the process that the determination method of line impedence is walked in another kind PCIE link provided by one embodiment of the present invention
Figure；
Fig. 3 is a kind of biography obtained under standard trace impedance and standard connector impedance provided by one embodiment of the present invention
Defeated parameter schematic diagram；
Fig. 4 is the another kind obtained under standard trace impedance and standard connector impedance provided by one embodiment of the present invention
Configured transmission schematic diagram；
Fig. 5 is a kind of PCIE link schematic diagram provided by one embodiment of the present invention
Fig. 6 is that 100ohm target connector impedance provided by one embodiment of the present invention and 85ohm reference are walked under line impedence
A kind of configured transmission schematic diagram obtained.
Fig. 7 is that 100ohm target connector impedance provided by one embodiment of the present invention and 90ohm reference are walked under line impedence
A kind of configured transmission schematic diagram obtained.
Fig. 8 is that 100ohm target connector impedance provided by one embodiment of the present invention and 100ohm reference are walked under line impedence
A kind of configured transmission schematic diagram obtained.
Fig. 9 is that 100ohm target connector impedance provided by one embodiment of the present invention and 85ohm reference are walked under line impedence
Another configured transmission schematic diagram of acquisition.
Figure 10 is that 100ohm target connector impedance provided by one embodiment of the present invention and 90ohm reference are walked under line impedence
Another configured transmission schematic diagram of acquisition.
Figure 11 is that line impedence is walked in 100ohm target connector impedance provided by one embodiment of the present invention and 100ohm reference
Another configured transmission schematic diagram of lower acquisition.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments, based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As shown in Figure 1, this method can the embodiment of the invention provides a kind of determination method for walking line impedence in PCIE link
To include:
Step 101: determining that PCIE link Plays walk line impedence and standard connector impedance；
Step 102: according to the standard trace impedance and the standard connector impedance, the standard for obtaining PCIE signal is passed
Defeated parameter；
Step 103: determining target connector impedance, and hindered according to the target connector impedance and the standard trace
Line impedence is walked in anti-determining at least one reference；
Step 104: according to each with reference to line impedence and the target connector impedance is walked, obtaining PCIE signal phase respectively
The reference transmission parameter answered；
Step 105: according at least one reference transmission parameter and the standard transmission parameter, and according to described at least one
Kind refers to cabling impedance, determines and finally walks line impedence.
In the above-described embodiments, to pass through on the basis of standard trace impedance and standard connector impedance in PCIE link
It obtains respective standard and walks the standard transmission parameter under line impedence and standard connector impedance conditions.Then in PCIE link, lead to
It crosses the impedance of change connector and determines that line impedence is walked at least one reference, and obtain the impedance of respective objects connector and at least one
Kind is with reference at least one reference transmission parameter under cabling impedance conditions.Finally by standard transmission parameter and reference transmission parameter into
Row comparison and analysis, determine it is final it is optimal walk line impedence.Therefore, line impedence, Neng Gouyou are walked by what this emulation link determined
The integrality of the guarantee PCIE signal of effect.
In an embodiment of the invention, described to be determined according to the target connector impedance and the standard trace impedance
Line impedence is walked at least one reference, comprising:
At least one impedance value between the target connector impedance and the standard trace impedance is selected, it will be every
One impedance value is determined as each reference and walks line impedence.
For example, standard trace impedance is 85ohm, it is 100ohm that target, which connects impedance,.It can be determined with reference to line impedence is walked then
For a certain impedance in 85-100ohm.It can be 90ohm, be also possible to 95ohm, can also be 100ohm, etc..
In an alternative embodiment of the invention, further comprise: determining error threshold；Further comprise: being walked for each
Line impedence performs the following operations respectively: the corresponding error impedance of line impedence is walked described in calculating, by it is described walk line impedence and it is described walk
The corresponding error impedance of line impedence is grouped as one；Wherein the impedance includes standard trace impedance and hinders with reference to cabling
It is anti-.
In embodiments of the present invention, the error threshold walks the 10% of line impedence for described in.
For example, it is 85ohm that one kind, which walks line impedence, due to the presence of 10% error threshold, make it is described walk line impedence generate pair
The error answered walks line impedence.Such as: error at this time, which walks line impedence, can be 76.5ohm, 93.5ohm etc..Therefore these are walked
Line impedence is grouped as one.
In an alternative embodiment of the invention, the standard transmission parameter for obtaining PCIE signal, comprising: be directed to the standard
Each normal impedance for including in grouping where walking line impedence, obtains each normal impedance and the standard connector impedance
Corresponding artificial eye Peye；
It is described that line impedence and the target connector impedance are walked according to each reference, it is corresponding that PCIE signal is obtained respectively
Reference transmission parameter, comprising: walk line impedence for each current reference and perform the following operations respectively: it is directed to the current reference
Each reference impedance for including in grouping where walking line impedence, obtains each reference impedance and the target connector impedance
Corresponding Peye.
For example, standard trace impedance includes 85ohm, 76.5ohm, 93.5ohm tri- in a packet in the present embodiment
Normal impedance.Therefore, each normal impedance and the standard connector impedance can respectively correspond respective Peye value.
In still another embodiment of the process, Peye is calculated by the first formula:
First formula includes:
Wherein, P is grouped corresponding Peye for characterizing where the target walks line impedence；PnIt is walked for characterizing the target
Line impedence the corresponding Peye of n-th of impedance in a packet；xnFor characterizing PnWeight.
For example, standard trace impedance includes 85ohm, 76.5ohm, 93.5ohm tri- marks in a packet in the present embodiment
Quasi- impedance, respective corresponding Peye are 26.9686,23.5592,26.8276.And 85ohm, 76.5ohm, 93.5ohm tri-
The corresponding weight of a normal impedance is followed successively by 0.8,0.1,0.1.
Therefore, the calculating of the Peye of this standard impedance group are as follows:
In another embodiment of the invention, further comprise: grouping with reference to where walking line impedence for each determines
The included corresponding signal integrity rate of each impedance in each grouping, using the corresponding impedance of peak signal percentage of head rice as
It is described finally to walk line impedence；
Wherein, the corresponding signal integrity rate of each impedance included in each grouping is determined by the second formula；
Second formula includes:
Wherein, ω is for characterizing signal integrity rate；PMarkIt is corresponding for grouping where characterizing the standard trace impedance
Peye。
In the present embodiment, it can determine that each impedance included in each grouping is corresponding using the calculation formula
Signal integrity rate, the influence for referring to away line impedence to link can effectively be judged according to the size of percentage of head rice, thus really
It is fixed finally to walk line impedence.
For example, referring to away the calculating for the ω that line impedence is 90ohm in PCIE link under target connector impedance.
By above-mentioned cabling impedance error threshold value, it is known that with reference to walk line impedence be 90ohm when, include three different impedances
Value, respectively 81ohm, 90ohm, 99ohm.Therefore, corresponding that there are three Peye and three different different ω.Wherein walk
Line impedence is the calculating of 81ohm are as follows:
Walking the ω that line impedence is 90ohm and 99ohm accordingly is 91.74% and 96.97% respectively.From calculated result we
It can significantly see with reference to signal integrity rate maximum when line impedence is 99ohm is walked, illustrate that this is more satisfactory with reference to line impedence is walked.
In another embodiment of the invention, the standard transmission parameter for obtaining PCIE signal, comprising: be directed to the mark
Each normal impedance for including in grouping where standard walks line impedence, draws each normal impedance and the standard connector hinders
Resist corresponding standard signal transmitted waveform；
It is described that line impedence and the target connector impedance are walked according to each reference, it is corresponding that PCIE signal is obtained respectively
Reference transmission parameter, comprising: walk line impedence for each current reference and perform the following operations respectively: it is directed to the current reference
Each reference impedance for including in grouping where walking line impedence, draws each reference impedance and the target connector impedance
Corresponding reference signal transmission waveform.
Below by PCIE link with SAS common connector for, cabling in the PCIE link of the embodiment of the present invention is hindered
Anti- determination method is described in detail.
As shown in Fig. 2, the embodiment of the invention provides a kind of determination method for walking line impedence in PCIE link, this method packet
It includes following:
Step 200: determining that PCIE link Plays walk line impedence and standard connector impedance；
It is worth noting that chip internal resistance and encapsulation impedance are 85ohm in PCIE link, therefore it is same to walk line impedence
For 85ohm, so standard trace impedance and standard connector impedance are 85ohm.
Step 201: determining error threshold；
Error is inevitably generated when to cabling resistor change, and error can only control within the scope of some.This
Determine that cabling impedance error threshold value is 10% in embodiment.
Step 202: walking line impedence for each, perform the following operations respectively: walking the corresponding mistake of line impedence described in calculating
Poor impedance, using it is described walk line impedence and it is described walk the corresponding error impedance of line impedence as one be grouped；The wherein impedance
Line impedence is walked including standard trace impedance and/or the reference；
Tellable to be, the calculating target walks at least one corresponding error impedance of line impedence, comprising: determines mesh
Range is marked, the target zone includes first end and second end；Selected in the target zone at least one impedance value as
At least one described error impedance；It does not include that the target walks line impedence at least one described error impedance；
Wherein, the first end is that the target walks line impedence and subtract the target to walk line impedence and the error threshold
Product, the second end are the product that the target walks that line impedence walks line impedence Yu the error threshold plus the target.
For example, the standard trace impedance determined in the present embodiment is 85ohm, so the first segment of the target zone is
76.5ohm, the second segment of the target zone are 93.5ohm.Therefore, the target zone of standard trace impedance is 76.5-
93.5ohm.Desirable error impedance is other impedances other than the target walks line impedence.For example determine 76.5ohm,
93.5ohm is the two error impedances chosen.These three are walked into line impedence and is considered as one group, referred to as Case1.Wherein, NNN, NLN,
NHN successively indicate target walk line impedence, line impedence is walked with the target small error impedance of corresponding impedance and with the mesh
Mark walks the big impedance of the corresponding impedance of line impedence.Please refer to table 1.
Table 1
| Case1NNN | 85ohm |
| Case1NLN | 76.5ohm |
| Case1NHN | 93.5ohm |
Step 203: according to the standard trace impedance and the standard connector impedance, obtaining at least the one of PCIE signal
Kind standard transmission parameter；
In the present embodiment, it can at least be passed by following two mode to obtain at least one standard of PCIE signal
Defeated parameter:
Mode 1: being monitored the transmission of PCIE signal using Intel CCT tool, is obtained by Intel CCT tool
Emulate time domain Metric.
Referring to FIG. 3, for emulation time domain Metric configured transmission figure, the reference datas such as including iSig, iISI, Peye.
Wherein iSig is for characterizing input signal size, and Iisi is for characterizing link impedance continuity, and Peye is for characterizing
Link quality degree.It is worth noting that the bigger link of Peye value is better, link signal is more complete.
Mode 2: the transmission of PCIE signal is monitored using Hspice analogue system, is obtained by Hspice analogue system
Obtain time domain model waveform diagram.
Referring to FIG. 4, being time domain model waveform diagram, this figure ordinate indicates impedance magnitude, and abscissa indicates the time.Region
The smoothness of interior lines indicates the continuity degree of signal, has the resonance of protrusion or recess to indicate impedance discontinuity.
It is worth noting that from signal transmitted waveform figure, it can be seen that the stability and continuity of signal, to judging signal
Integrality has beneficial help.
For example, the standard trace impedance determined in the present embodiment is 85ohm, error resistance corresponding with standard trace impedance
Resist for 76.5ohm, 93.5ohm.So NNN is for characterizing 85ohm, NLN is for characterizing 76.5ohm, and NHN is for characterizing
93.5ohm。
Step 204: walking line impedence described in determining as PCIE link dorsulum and walk line impedence.
For example, in a PCIE link, including mainboard and hard disk.Please refer to Fig. 5.Line impedence is modified away for mainboard
Required cost is much higher compared with backboard change cabling.And hard disk is then existing product, and line impedence cannot be changed away to it, so only
Backboard can be changed and walk line impedence.
Step 205: determining target connector impedance, and hindered according to the target connector impedance and the standard trace
Line impedence is walked in anti-determining at least one reference；
In embodiments of the present invention, because and SAS need to use impedance with SAS common connector in PCIE link
The connector of 100ohm, so the target connector impedance determined is 100ohm.Meanwhile PCIE link Plays walk line impedence and are
85ohm will affect link transmission speed if impedance is lower than 85ohm.So can be 85-100ohm with reference to line impedence is walked.Below
For selecting three references to walk line impedence, the present embodiment is illustrated.For example, this three can be with reference to line impedence is walked
85ohm, 90ohm, 100ohm.And three kinds determined are successively known as Case2, Case3, Case4 with reference to cabling impedance.
Wherein, it is 85ohm, NLN 76.5ohm, NHN 93.5ohm that Case2, which may include: NNN,.
Case3 may include: that NNN is 90ohm, NLN 81ohm, NHN 99ohm.
Case4 may include: that NNN is 100ohm, NLN 90ohm, NHN 110ohm.
Step 206: according to each normal impedance and the standard connector impedance, it is corresponding to obtain PCIE signal respectively
Reference transmission parameter；
In this step, each normal impedance for including in a packet primarily directed to the standard trace impedance,
Obtain each normal impedance artificial eye Peye corresponding with the standard connector impedance.Wherein Peye is to pass through Intel
CCT tool obtains a parameter in emulation time domain Metric configured transmission, for determining that link quality, this value are the bigger the better.
Step 207: according to each with reference to line impedence and the target connector impedance is walked, obtaining PCIE signal phase respectively
The reference transmission parameter answered；
In this step, each for including in grouping where walking line impedence primarily directed to the current reference is with reference to resistance
It is anti-, obtain each reference impedance Peye corresponding with the target connector impedance.Such as above-mentioned Case2, Case3,
Case4 reference transmission parameter obtained, please with this refer to Fig. 6,7,8.
Step 208: calculating Peye；
In the present embodiment, Peye can be calculated by formula (1):
Wherein, P is grouped corresponding Peye for characterizing where the target walks line impedence；PnIt is walked for characterizing the target
Line impedence the corresponding Peye of n-th of impedance in a packet；xnFor characterizing PnWeight.
For example, in the present embodiment, PCIE link Plays walk the calculating of the Peye of line impedence.
Wherein P1、P2、P3It is followed successively by 26.9686,23.5592,26.8276.x1、x2、x3It is followed successively by 0.8,0.1,0.1.Institute
It is with this standard trace impedance Peye:
Step 209: determining the corresponding signal integrity rate of each impedance included in each grouping；
In the present embodiment, the signal integrity rate in PCIE link can be determined by formula (2).
Wherein, ω is for characterizing signal integrity rate；PMarkIt is corresponding for grouping where characterizing the standard trace impedance
Peye。
For example, referring to away the calculating for the ω that line impedence is 90ohm in PCIE link under target connector impedance.
By above-mentioned cabling impedance error threshold value, it is known that with reference to walk line impedence be 90ohm when, may include three different resistances
Anti- value, respectively 81ohm, 90ohm, 99ohm.Therefore, corresponding that there are three Peye and three different different ω.Wherein
Walk the calculating that line impedence is 81ohm are as follows:
Walking the ω that line impedence is 90ohm and 99ohm accordingly is 91.74% and 96.97% respectively.Wherein institute's value is got over
Greatly, illustrate that the percentage of head rice of signal is bigger, i.e., the integrality of signal is better.
Step 210: executing described each normal impedance of drafting using Hspice and the standard connector impedance is distinguished
Corresponding standard signal transmitted waveform；
In this step, each normal impedance standard letter corresponding with the standard connector impedance is mainly obtained
Number transmitted waveform figure.This figure ordinate indicates impedance magnitude, and abscissa indicates the time.The smoothness of lines in region indicates
The continuity degree of signal has the resonance of protrusion or recess to indicate impedance discontinuity.According to the only backboard cabling of above-mentioned change
Impedance, signal are existed by the period of backboard
1.1n-2.5n.So passing through the smoothness of observation lines within time 1.1n-2.5n section.
Step 211: executing described each reference impedance of drafting using Hspice and the target connector impedance is distinguished
Corresponding reference signal transmission waveform；
In this step, it is corresponding with the target connector impedance with reference to letter mainly to obtain each reference impedance
Number transmitted waveform figure.Fig. 9,10,11 are please successively referred to, waveform when reference impedance is 85ohm, 90ohm, 100ohm is respectively indicated
Figure.It can be seen from the above, this figure ordinate indicates impedance magnitude, abscissa indicates the time.The flatness of lines in region indicates
The continuity degree of signal has the resonance of protrusion or recess to indicate impedance discontinuity.According to the only backboard cabling of above-mentioned change
Impedance, signal is by the period of backboard in 1.1n-2.5n.So by observation within the time 1.1n-2.5n section lines put down
Slippage degree.
Step 212: according at least one reference transmission parameter and the standard transmission parameter, and according to described at least one
Kind cabling impedance is referred to, determines and final walk line impedence.
In the present embodiment, configured transmission is referred to using two kinds, obtains signal transmission percentage of head rice, numerical value using Peye is calculated
Bigger signal is more complete.And the flatness that waveform is propagated by comparing signal, has the resonance of protrusion or recess to indicate impedance
Discontinuously.Accordingly, it is determined that it is 99ohm that backboard, which walks line impedence,.Configured transmission is referred to using two kinds in the embodiment, according to specific number
Value carries out comprehensive descision with waveform flatness, can be determined more accurately and final walk line impedence.
According to above scheme, various embodiments of the present invention are at least had the following beneficial effects:
1. this method is in PCIE link to pass through at least one on the basis of standard trace impedance and standard connector impedance
Configured transmission obtains tool, obtains respective standard and walks at least one standard transmission under line impedence and standard connector impedance conditions
Parameter.Then in PCIE link, by changing connector impedance and determining that line impedence is walked at least one reference, and by described
At least one configured transmission obtains tool, obtains the impedance of respective objects connector and with reference at least one under cabling impedance conditions
Reference transmission parameter.Finally standard transmission parameter and reference transmission parameter are compared and are analyzed, determine it is final it is optimal walk
Line impedence.Therefore, line impedence is walked by what this emulation link determined, can effectively ensure that the integrality of PCIE signal.
2. this method in PCIE link by the basis of standard trace impedance and standard connector impedance, i.e., in link not with
SAS common connector, the Hspice for obtaining signal in PCIE link by the CCT tool of Hspice analogue system and Intel are imitative
The CCT tool of true link time domain model waveform diagram and Intel emulate two kinds of standard transmission parameters of time domain Metric.And in PCIE and
In the link of SAS common connector, by changing connector and the method for walking line impedence, and using Hspice analogue system and
The Hspice that the CCT tool of Intel obtains signal in the link of PCIE and SAS common connector emulates link time domain model waveform
The CCT tool of figure and Intel emulate two kinds of time domain Metric and refer to configured transmission.By to standard transmission parameter and reference transmission
Parameter is compared and is analyzed, determine it is final it is optimal walk line impedence.Therefore, it can effectively ensure that the complete of PCIE signal
Property.
3. carrying out discussion research by using analog simulation link pair link, not only economizing on resources reduces cost, and also
Characteristic with simple and effective.
4. determining line impedence by emulation link, it ensure that the integrality of PCIE signal, may be implemented to adopt in the design
With the idea of PCIE and SAS common connector.Therefore the connector that impedance 100ohm can be used in a link, realizes system mould
The design of blockization and low cost.
It should be noted that, in this document, such as first and second etc relational terms are used merely to an entity
Or operation is distinguished with another entity or operation, is existed without necessarily requiring or implying between these entities or operation
Any actual relationship or order.Moreover, the terms "include", "comprise" or its any other variant be intended to it is non-
It is exclusive to include, so that the process, method, article or equipment for including a series of elements not only includes those elements,
It but also including other elements that are not explicitly listed, or further include solid by this process, method, article or equipment
Some elements.In the absence of more restrictions, the element limited by sentence " including one ", is not arranged
Except there is also other identical factors in the process, method, article or apparatus that includes the element.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can store in computer-readable storage medium, the program
When being executed, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes: ROM, RAM, magnetic disk or light
In the various media that can store program code such as disk.
Finally, it should be noted that the foregoing is merely presently preferred embodiments of the present invention, it is merely to illustrate skill of the invention
Art scheme, is not intended to limit the scope of the present invention.Any modification for being made all within the spirits and principles of the present invention,
Equivalent replacement, improvement etc., are included within the scope of protection of the present invention.
Claims (5)
1. walking the determination method of line impedence in a kind of PCIE link, which is characterized in that the described method includes:
Determine that PCIE link Plays walk line impedence and standard connector impedance；
According to the standard trace impedance and the standard connector impedance, the standard transmission parameter of PCIE signal is obtained, it is described
Obtain the standard transmission parameter of PCIE signal, comprising: each mark for including in a packet for the standard trace impedance
Quasi- impedance obtains each normal impedance artificial eye Peye corresponding with the standard connector impedance；
It determines target connector impedance, and determines at least one according to the target connector impedance and the standard trace impedance
Kind refers to cabling impedance；
According to each with reference to line impedence and the target connector impedance is walked, the corresponding reference transmission of PCIE signal is obtained respectively
Parameter；
It is described that line impedence and the target connector impedance are walked according to each reference, PCIE signal is obtained respectively to be referred to accordingly
Configured transmission, comprising: walk line impedence for each current reference and perform the following operations respectively: it is directed to the current reference cabling
Each reference impedance that impedance includes in a packet, obtains each reference impedance and the target connector impedance is distinguished
Corresponding Peye；
According at least one reference transmission parameter and the standard transmission parameter, and according to described at least one with reference to cabling resistance
It is anti-, it determines and finally walks line impedence；
According at least one reference transmission parameter and the standard transmission parameter, and according to described at least one with reference to cabling resistance
It is anti-, it determines and finally walks line impedence, comprising:
Each reference transmission parameter is compared with the standard transmission parameter respectively；
According to comparison result determination and the smallest object reference configured transmission of the standard transmission parameter error；
Line impedence is walked according at least one reference, determines that target component corresponding with the object reference configured transmission is walked
Line impedence；
By the target component walk line impedence be determined as it is described finally walk line impedence；
Further comprise: determining error threshold；
Further comprise: walking line impedence for each target, perform the following operations respectively: calculating the target and walk line impedence pair
The target is walked line impedence and the target is walked at least one corresponding error of line impedence and hindered by least one the error impedance answered
It is anti-to be grouped as one；Wherein, it includes that line impedence is walked in the standard trace impedance and the reference that the target, which walks line impedence,；
Peye is calculated by the first formula:
First formula includes:
Wherein, P is grouped corresponding Peye for characterizing where the target walks line impedence；PnFor characterizing the target cabling resistance
Anti- the corresponding Peye of n-th of impedance in a packet；xnFor characterizing PnWeight；
Further comprise: grouping with reference to where walking line impedence for each determines each included in each grouping
The corresponding signal integrity rate of impedance finally walks line impedence using the corresponding impedance of peak signal percentage of head rice as described；
Wherein, the corresponding signal integrity rate of each impedance included in each grouping is determined by the second formula；
Second formula includes:
Wherein, ω is for characterizing signal integrity rate；PMarkFor the corresponding Peye of grouping where characterizing the standard trace impedance.
2. the method according to claim 1, wherein described according to the target connector impedance and the standard
It walks line impedence and determines that line impedence is walked at least one reference, comprising:
At least one impedance value between the target connector impedance and the standard trace impedance is selected, by each
Impedance value is determined as each reference and walks line impedence.
3. according to the method described in claim 2, it is characterized in that,
The standard transmission parameter for obtaining PCIE signal, comprising: include in a packet for the standard trace impedance
Each normal impedance draws each normal impedance standard signal transmission wave corresponding with the standard connector impedance
Shape；
It is described that line impedence and the target connector impedance are walked according to each reference, PCIE signal is obtained respectively to be referred to accordingly
Configured transmission, comprising: walk line impedence for each current reference and perform the following operations respectively: it is directed to the current reference cabling
Each reference impedance that impedance includes in a packet, draws each reference impedance and the target connector impedance is distinguished
Corresponding reference signal transmission waveform.
4. according to the method described in claim 3, it is characterized in that, executing described each normal impedance of drafting using Hspice
Standard signal transmitted waveform corresponding with the standard connector impedance；Each ginseng of the drafting is executed using Hspice
Examine impedance reference signal transmission waveform corresponding with the target connector impedance.
5. according to the method described in claim 4, it is characterized in that,
The error threshold includes: 10%；
The calculating target walks at least one corresponding error impedance of line impedence, comprising: determines target zone, the target
Range includes first end and second end；Select at least one impedance value as at least one described error in the target zone
Impedance；It does not include that the target walks line impedence at least one described error impedance；
Wherein, the first end is that the target walks line impedence and subtract the target to walk multiplying for line impedence and the error threshold
Product, the second end are the product that the target walks that line impedence walks line impedence Yu the error threshold plus the target.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610607012.XA CN106202824B (en) | 2016-07-28 | 2016-07-28 | The determination method of line impedence is walked in a kind of PCIE link |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610607012.XA CN106202824B (en) | 2016-07-28 | 2016-07-28 | The determination method of line impedence is walked in a kind of PCIE link |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106202824A CN106202824A (en) | 2016-12-07 |
| CN106202824B true CN106202824B (en) | 2019-02-15 |
Family
ID=57496721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610607012.XA Active CN106202824B (en) | 2016-07-28 | 2016-07-28 | The determination method of line impedence is walked in a kind of PCIE link |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106202824B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106604550B (en) * | 2016-12-16 | 2018-10-09 | 郑州云海信息技术有限公司 | A kind of line impedance adjusting method and system |
| CN107064675A (en) * | 2017-03-31 | 2017-08-18 | 华为技术有限公司 | Receiving end signal acquisition methods and device |
| CN107506319A (en) * | 2017-08-29 | 2017-12-22 | 郑州云海信息技术有限公司 | A kind of integrated storage system |
| CN108182522A (en) * | 2017-12-25 | 2018-06-19 | 中国电子科技集团公司第二十八研究所 | A kind of navigation channel traffic safety methods of risk assessment based on AHP- entropy assessments |
| CN112004321B (en) * | 2020-08-07 | 2021-12-03 | 北京浪潮数据技术有限公司 | Design method for surface-mounted connector on circuit board and circuit board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203930788U (en) * | 2014-07-09 | 2014-11-05 | 浪潮电子信息产业股份有限公司 | A kind of structure that is applied to server PCIE board, hard disk |
| CN204376132U (en) * | 2015-01-18 | 2015-06-03 | 安费诺东亚电子科技(深圳)有限公司 | A kind of integral connector being applicable to PCI-E SAS |
| US9400763B2 (en) * | 2014-02-24 | 2016-07-26 | Rj Intellectual Properties, Llc | PCI express expansion system |
| CN105812216A (en) * | 2016-05-26 | 2016-07-27 | 上海嘉强自动化技术有限公司 | PBUS (peripheral bus) non-transformer EtherCAT (Ethernet for control automation technology) communication circuit and method of application thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7320083B2 (en) * | 2003-04-23 | 2008-01-15 | Dot Hill Systems Corporation | Apparatus and method for storage controller to deterministically kill one of redundant servers integrated within the storage controller chassis |
-
2016
- 2016-07-28 CN CN201610607012.XA patent/CN106202824B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9400763B2 (en) * | 2014-02-24 | 2016-07-26 | Rj Intellectual Properties, Llc | PCI express expansion system |
| CN203930788U (en) * | 2014-07-09 | 2014-11-05 | 浪潮电子信息产业股份有限公司 | A kind of structure that is applied to server PCIE board, hard disk |
| CN204376132U (en) * | 2015-01-18 | 2015-06-03 | 安费诺东亚电子科技(深圳)有限公司 | A kind of integral connector being applicable to PCI-E SAS |
| CN105812216A (en) * | 2016-05-26 | 2016-07-27 | 上海嘉强自动化技术有限公司 | PBUS (peripheral bus) non-transformer EtherCAT (Ethernet for control automation technology) communication circuit and method of application thereof |
Non-Patent Citations (1)
| Title |
|---|
| Analysis of Signal Integrity/Power Integrity in Multilayer Printed Circuit Board and Two Improving Methods;Hee-do Kang等;《2008 Electrical Design of Advanced Packaging and Systems Symposium》;20081230;第210-213页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106202824A (en) | 2016-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106202824B (en) | The determination method of line impedence is walked in a kind of PCIE link | |
| US7559045B2 (en) | Database-aided circuit design system and method therefor | |
| US10237097B2 (en) | Worst case eye for multi-level pulse amplitude modulated links | |
| CN106055729B (en) | A kind of Fault Tree Analysis based on Monte Carlo simulation | |
| CN104143024B (en) | Quick time-domain simulation method for high-speed parallel link system | |
| RU2015146599A (en) | METHOD AND DEVICE FOR MANAGING A TRANSPORT NETWORK | |
| CN102314522A (en) | Optimizing method of analogue integrated circuit design | |
| US10936781B1 (en) | Method for setting parameters in design of printed circuit board, device employing method, and non-transitory storage medium | |
| CN105488023A (en) | Text similarity assessment method and device | |
| US8060852B1 (en) | Method and system for screening nets in a post-layout environment | |
| CN103984688A (en) | Method and equipment for providing input candidate vocabulary entries based on local word bank | |
| US9330212B2 (en) | Recording medium in which circuit simulator program is stored, and device and method for generating eye pattern | |
| CN103744889A (en) | Method and device for clustering problems | |
| CN110232445A (en) | A kind of historical relic authenticity identification method of knowledge based distillation | |
| CN105653752A (en) | Digital signal impedance match circuit designing method | |
| CN106604550A (en) | Line impedance adjusting method and system | |
| US20180045761A1 (en) | Jitter and eye contour at ber measurements after dfe | |
| WO2018054198A1 (en) | Method and apparatus for selecting integrated circuit device neural network modeling sample | |
| CN107561420A (en) | A kind of cable local discharge signal characteristic vector extracting method based on empirical mode decomposition | |
| Ambasana et al. | Application of artificial neural networks for eye-height/width prediction from S-parameters | |
| US20160154923A1 (en) | Method of analog front end optimization in presence of circuit nonlinearity | |
| Lho et al. | Eye-width and eye-height estimation method based on artificial neural network (ANN) for USB 3.0 | |
| US8863050B1 (en) | Efficient single-run method to determine analog fault coverage versus bridge resistance | |
| US8682621B2 (en) | Simulating the transmission of asymmetric signals in a computer system | |
| Lingambudi et al. | A case study of high-speed serial interface simulation with IBIS-AMI models |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |