CN104143024B - A parallel time-domain simulation fast speed link system - Google Patents

A parallel time-domain simulation fast speed link system Download PDF

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CN104143024B
CN104143024B CN 201410367337 CN201410367337A CN104143024B CN 104143024 B CN104143024 B CN 104143024B CN 201410367337 CN201410367337 CN 201410367337 CN 201410367337 A CN201410367337 A CN 201410367337A CN 104143024 B CN104143024 B CN 104143024B
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CN 201410367337
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CN104143024A (en )
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刘洋
甄江平
赵强
原玉章
林永嘉
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西安电子科技大学
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本发明公开了一种并行高速链路系统的快速时域仿真方法,本发解决现有技术对于脉冲边沿不对称及器件非线性系统驱动器无法得到最坏码型和最坏眼图,对信号抖动参数的计算描述不明确,眼宽的计算精度不高的问题。 The present invention discloses a method for fast time-domain simulation speed link, a parallel system, the present invention is to solve the prior art for asymmetric edge pulse driver device and nonlinear systems can not get the worst and the worst eye pattern, signal jitter calculation parameter description is not clear, the eye width accuracy is not high. 本发明实现步骤是:(1)选用并行高速链路系统;(2)建立SPICE模型;(3)获得边沿响应信号(4)计算仿真阶数;(5)获得上升边和下降边向量(6)获得最坏码型序列向量;(7)获得预估的最坏眼图;(8)用步骤(2)建立的SPICE模型仿真最坏眼图;(9)获得预估精度的绝对误差。 The present invention is implemented steps of: (1) selection of a high-speed parallel link system; (2) establishing SPICE model; (3) obtaining a response signal edge (4) the order of simulation calculation; (5) obtaining rising and falling edge vector (6 ) obtaining a worst pattern vector sequence; (7) to obtain the estimated worst eye; the SPICE model simulation worst eye (8) of step (2) to establish; (9) obtains an absolute error of prediction accuracy. 本发明能够得到精确的眼宽和抖动数据。 The present invention can provide accurate data eye width and jitter.

Description

一种并行高速链路系统的快速时域仿真方法 A parallel time-domain simulation fast speed link system

技术领域 FIELD

[0001] 本发明属于电子技术领域,更进一步涉及高速电路设计的快速时域仿真技术领域中的一种并行高速链路系统的快速时域仿真方法。 [0001] The present invention belongs to the field of electronics, and further relates to a fast time domain simulation method of a fast time-domain simulation BACKGROUND high speed circuit design of parallel high-speed links to the system. 本发明可应用于对并行高速链路系统中最坏系统性能的评估。 The present invention is applicable to a high-speed parallel link system to evaluate the worst performance of the system.

背景技术 Background technique

[0002] 随着电子系统向高速、高密度、低电压和大电流的趋势发展,板级互连的速度也越来越快,反射,串扰,地弹以及码间串扰(intersymbol interference ISI)等信号完整性问题日益凸显,上述问题对并行高速链路系统接收的信号质量有着严重的影响,因此在并行高速链路设计中快速评估这些信号完整性问题对系统性能的影响至关重要。 [0002] With the trend of development of electronic systems to high speed, high density, low voltage and high current, the board-level interconnect faster speed, reflection, cross talk, ground bounce, and ISI (intersymbol interference ISI), etc. signal integrity problems have become increasingly prominent, the above-mentioned problems has serious implications for parallel high-speed link system received signal quality, so essential to quickly evaluate the impact of these issues on system performance signal integrity in high-speed parallel link design. 目前预估并行高速链路系统性能的方法主要有统计域方法和时域方法,而基于统计链路的仿真流程中假设数据模板和抖动频谱是白色的,系统是线性的。 Currently estimated parallel high-speed link system performance methods have major statistical domain method and time domain method, and the simulation process statistical link data based on the assumption template and jitter spectrum is white, the system is linear. 这些假设将导致仿真不够准确。 These assumptions will lead to inaccurate simulation. 而时域快速仿真方法不仅能克服统计域仿真方法的缺陷还可以对并行高速链路系统性能进行准确快速的评估。 Fast time domain simulation method and not only overcome the defects of the count field simulation method may also be rapid and accurate assessment of the performance of high speed parallel link system.

[0003] Casper BK ,Haycok M.and Mooney R发表的"An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes" (IEEE Symposium on VLSI Circuits Digest of Technical Papers.2002,Jun.54_57)论文,文中首次提出峰值失真分析(Peak Distortion Analysis PDA)时域仿真方法,它是真正意义上开创快速时域仿真技术的先河。 [0003] Casper BK, Haycok M.and Mooney R published "An accurate and efficient analysis method for multi-Gb / s chip-to-chip signaling schemes" (IEEE Symposium on VLSI Circuits Digest of Technical Papers.2002, Jun. 54_57) paper, proposed first peak distortion analysis (peak distortion analysis PDA) time-domain simulation method, which is to create a fast time-domain simulation technology in the true sense of its kind. 峰值失真分析(Peak Distortion Analysis PDA)预测最坏码型总体分两部分:第一部分,预测码间串扰(Inter Symbol Interference ISI)影响的码型;第二部分,预测串扰影响的码型。 Peak distortion analysis (Peak Distortion Analysis PDA) predicted worst pattern generally divided into two parts: the first part, the influence of inter-code crosstalk prediction (Inter Symbol Interference ISI) pattern; the second portion pattern, the influence of crosstalk prediction. 串扰影响的预测不需要定主光标,其他步骤和码间串扰(Inter Symbol Interference ISI) 一致。 For no crosstalk prediction of the main cursor, among other steps and ISI (Inter Symbol Interference ISI) consistent. 串扰的操作比码间串扰(Inter Symbol Interference ISI)更简单,只需要依照码间串扰(Inter Symbol Interference ISI)后两个操作步骤即可。 Crosstalk is more simple than the ISI (Inter Symbol Interference ISI), can only two steps in accordance with the ISI (Inter Symbol Interference ISI). 但是,该方法的不足之处在于:对于上升边响应和下降边响应不对称的情况,若采用峰值失真分析(Peak Distortion Analysis PDA)方法,边沿响应连1的情况将预测不准确。 However, the disadvantage of this method is that: in response to the rising edge and falling edge of the case of asymmetric response, when using a peak distortion analysis (Peak Distortion Analysis PDA) method, even where one edge response of the prediction is not accurate. 所以对于边沿不对称的驱动器构成的系统,峰值失真分析(Peak Distortion Analysis PDA) 方法预测的眼高可能会比实际值偏大。 So for edge asymmetrical drive system configuration, the peak distortion analysis (Peak Distortion Analysis PDA) eye height prediction method may be larger than the actual value.

[0004] Rambus Inc.,Los Altos,CA(US)申请的发明专利"TECHNIQUE FOR DETERMINING PERFORMANCE CHARACTERISTICS OF ELECTRONIC SYSTEMS" (United States Patent Application,Appl.No.:10/097133,Patent No.:US 6775809 BI,Date of Patent:Aug, 10,2004)中公开了一种双边沿响应(Double Edge Responses DER)时域仿真方法。 [0004] Rambus Inc., Los Altos, CA (US) patent application "TECHNIQUE FOR DETERMINING PERFORMANCE CHARACTERISTICS OF ELECTRONIC SYSTEMS" (United States Patent Application, Appl.No:. 10/097133, Patent No.:US 6775809 BI , Date of Patent: Aug, 10,2004) discloses a time domain simulation method of a double-edge response (Double edge Responses DER). 该方法主要为两步:第一步,求向量,第二步,解向量。 The method mainly in two steps: first, find the vector, the second step, the solution vector. 该方法的目的是求解出引起边沿脉冲响应中最坏的高电平,最坏的低电平,最好的高电平,最好的低电平的向量。 The purpose of this method is to solve the edge pulses caused by the high level in response to the worst, the worst low, the best high level, a low level of the best vector. 该方法的不足之处在于:对于脉冲边沿不对称及器件非线性系统驱动器有可能无法得到最坏码型和最坏眼图; 虽然双边沿响应(Double Edge Responses DER)时域仿真方法可以仿真非线性系统,但是由于双边沿响应(Double Edge Responses DER)时域仿真方法没有考虑当前位周期(Unit Inerval UI)范围外的驱动器的开关活动,所以该方法不能充分捕获系统的非线性效应对后续码元的影响。 Disadvantage of this method is that: for the pulse edge asymmetry and nonlinear system drive device may not be obtained and the worst pattern worst eye; Although double edge when the response (Double Edge Responses DER) domain simulation method simulates a non- linear systems, but due to the double-edge response (Double edge Responses DER) time domain simulations do not account for the current bit period (unit Inerval UI) switching activity drive out of range, this method can not sufficiently capture the nonlinear effects system for subsequent code the impact of yuan.

[0005] Ren J.and Oh D发表的"Multiple edge responses for fast and accurate system simulations"(IEEE Transactions on Advanced Packaging.2008,Nov,31 (4) .741-748.)论文中提出了多边沿响应(Multiple Edge Responses MER)时域仿真方法。 [0005] Ren J.and Oh D published "Multiple edge responses for fast and accurate system simulations" (IEEE Transactions on Advanced Packaging.2008, Nov, 31 (4) .741-748.) Paper proposes a multi-edge response (Multiple Edge Responses MER) time-domain simulation method. 该方法的具体步骤如下:1、定义多边沿响应(Multiple Edge Responses MER)上升边、下降边;2、求向量;3、确定仿真阶数;4、解向量。 Specific steps of the method are as follows: 1, in response to an edge defining multiple (Multiple Edge Responses MER) rising edge, falling edge; 2, find the vector; 3, determining the order of simulation; 4, solution vector. 该方法的不足之处在于:该方法对信号抖动参数的计算描述不够明确,最后结果验证中仅给出了眼高的对比数据而未给出眼宽的对比数据,并且眼宽的计算精度不高。 Disadvantage of this method is that: the method for calculating jitter parameter description is not clear enough, the final verification result gives only high ocular eye width gives comparative data without comparison data, and calculation accuracy eye width high.

发明内容 SUMMARY

[0006] 本发明的目的在于克服上述已有技术的不足,提出一种并行高速链路系统的快速时域仿真方法(Best Time-Domain Simulation BTDS),以获得脉冲边沿不对称及器件非线性系统驱动器的最坏码型,并且提高了眼宽的仿真精度,进而设计出良好的系统驱动器。 [0006] The object of the present invention is to overcome the disadvantages of the aforementioned prior art, the time domain simulation method proposed fast (Best Time-Domain Simulation BTDS) system, a parallel high speed link, to obtain a pulse edge asymmetric nonlinear systems and devices drive worst pattern, and improves the accuracy of the simulation of eye width, and then design a good system drive.

[0007] 为实现上述目的,本发明的具体步骤包括如下: [0007] To achieve the above object, the present invention specifically includes the following steps:

[0008] (1)选用并行高速链路系统。 [0008] (1) selection of a high-speed parallel link system.

[0009] ⑵建立SPICE模型: [0009] ⑵ establish SPICE model:

[0010] 将并行高速链路系统中的线宽、线间距、介质厚度、介电常数、损耗因子和传输线厚度参数值,赋给通用模拟电路仿真器SPICE模型中对应的参数,完成并行高速链路系统的SPICE模型的建立。 [0010] A high-speed parallel link system in line width, line spacing, dielectric thickness, dielectric constant, loss factor, and the transmission line thickness parameter values, the parameter assigned to general analog circuit simulator SPICE models corresponding to complete high-speed parallel chains SPICE model established road system.

[0011] (3)获得边沿响应信号: [0011] (3) obtaining an edge signal in response to:

[0012] (3a)将基准的上升边信号00000001111加载到通用模拟电路仿真器SPICE模型中进行仿真,得到基准上升边响应信号; [0012] (3a) the rising edge of the reference signal is loaded into a general 00000001111 analog simulator SPICE circuit simulation model, to obtain a reference signal in response to rising edge;

[0013] (3b)将基准的下降边信号11111110000加载到通用模拟电路仿真器SPICE模型中进行仿真,得到基准下降边响应信号; [0013] (3b) of the falling edge of the reference signal 11111110000 loaded into a general analog circuit simulator SPICE models for simulation, to obtain the reference signal in response to a falling edge;

[0014] (3c)将有前导位0101010的上升边信号01010101111和零信号01010100000加载到通用模拟电路仿真器SPICE模型中进行仿真,将这两个信号的仿真结果相减,得到受前导位影响上升边响应信号; [0014] (3c) will have a leading bit rising edge of signal 0101010 01010101111 01010100000 zero signal and loaded into a general analog circuit simulator SPICE model simulation, the simulation result of these two signals are subtracted by the leading bit to give increased impact edge response signal;

[0015] (3d)将有前导位0101010的零信号01010100000加载到通用模拟电路仿真器SPICE 模型中进行仿真,得到受前导位影响下降边响应信号。 [0015] (3d) will have a leading zero signal bit 01010100000 0101010 is loaded into a general analog circuit simulator SPICE model simulation, give a response signal by the falling edge leading bit affected.

[0016] ⑷计算仿真阶数: [0016] ⑷ simulation calculation order:

[0017] 按照下式,计算仿真并行高速链路系统中最坏眼图的阶数; [0017] The order of the following formula, calculated simulation parallel high-speed link system according to the worst eye;

Figure CN104143024BD00071

[0019] 其中:N表示仿真并行高速链路系统中最坏眼图的阶数,T表示基准上升边响应信号和受前导位影响上升边响应信号相减的差值大于〇. 1 %的持续时间,t表示基准上升边响应信号的上升边的上升时间。 [0019] where: N represents the order of the simulation of parallel high-speed links worst eye system, T represents the reference signal in response to the rising edge and the influence by the leading bit in response to the rising edge of the signal subtracting square difference is greater than 1% of the duration. time, t represents the leading edge of the reference signal in response to the rise time of the rising edge.

[0020] (5)获得上升边和下降边向量: [0020] (5) for rising and falling edge vectors:

[0021] (5a)将受前导位影响上升边响应信号值,与逻辑0响应信号值之差超过0.001的第一个点,设定为受前导位影响上升边响应信号的采样起点; [0021] (5a) will be subject to impact the leading rising edge bit response signal, a first point difference between the signal value of more than 0.001 and a logic 0 in response, set by the rising edge of the leading bit of the influence signal in response to the sampling start point;

[0022] (5b)将有前导位0101010的上升边信号01010101111,加载到通用模拟电路仿真器SPICE模型中,对模型中任意一根进攻线进行仿真,获得仅有码间串扰的受前导位影响上升边响应信号; [0022] (5b) will rise from the leading edge of the signal 01010101111 0101010, loaded into a general analog simulator SPICE circuit models, a model of any offensive line simulation, obtaining only affect inter-symbol interference by the leading bit a response signal rising edge;

[0023] (5c)对仅有码间串扰的受前导位影响上升边响应信号,从采样起点处以上升边信号01010101111的一个位宽为间隔进行采样,采样15次,每次采样50个点,获得15组仅有码间串扰的受前导位影响上升边响应信号向量; [0023] (5c) by the leading bit of the rising influence of inter-symbol interference only in response to a signal edge, starting from the sampling signal a rising edge of the bit width impose 01010101111 sampling interval, sample 15 times, 50 points per sample, 15 is obtained only symbol interference between groups receiving side in response to the leading bit of the impact of rising signal vectors;

[0024] (5d)将对进攻线进行仿真时受害线上感应出的串扰噪声,与仅有码间串扰的受前导位影响上升边响应信号相加,获得有串扰噪声时的受前导位影响上升边响应信号; When the victim line [0024] (5d) will offensive line simulation induced crosstalk noise, inter-symbol interference only by the leading edge of the bit in response to the impact of rising signals are summed to obtain a leading position when influenced by crosstalk noise a response signal rising edge;

[0025] (5e)对有串扰噪声时的受前导位影响上升边响应信号,从采样起点处以上升边信号01010101111的一个位宽为间隔进行采样,采样15次,每次采样50个点,,获得15组有串扰噪声时的受前导位影响上升边响应信号向量; [0025] (5e) Position on the crosstalk noise when receiving a preamble signal in response to rising edge, starting from the sampling bit width of a rising edge of the signal imposed 01010101111 sampling interval, sample 15 times, 50 points per sample ,, 15 obtained by the group in response to the rising edge of the leading bit impact signal when the crosstalk noise vector;

[0026] (5f)将受前导位影响下降边响应信号值,与逻辑1响应信号值之差超过0.001的第一个点,设定为受前导位影响下降边响应信号的采样起点; [0026] (5f) by the falling edge of the bit affects the preamble response signal, and a logic 1 in response to the first difference signal point value exceeds 0.001, the leading bit is set by the falling edge of the impact signal in response to the sampling start point;

[0027] (5g)将有前导位0101010的下降边信号01010100000,加载到通用模拟电路仿真器SPICE模型中,对模型中任意一根进攻线进行仿真,获得仅有码间串扰的受前导位影响下降边响应信号; [0027] (5g) will have a leading edge of the signal level drops 01010100000 0101010, and loaded onto a general analog simulator SPICE circuit models, a model of any offensive line simulation, obtaining only affect inter-symbol interference by the leading bit falling edge of the response signal;

[0028] (5h)对仅有码间串扰的受前导位影响下降边响应信号,从采样起点处以下降边信号01010100000的一个位宽为间隔开始采样,采样15次,每次采样50个点,获得15组仅有码间串扰的受前导位影响下降边响应信号向量; [0028] (5h) to decrease the influence by the leading bit of the inter-symbol interference only in response to a signal edge, starting from the sampling signal a falling edge of the bit width impose 01010100000 to begin sampling interval, sample 15 times, 50 points per sample, 15 code groups obtained only in response to a falling edge crosstalk affecting the signal vector by the leading bit;

[0029] (5i)将对进攻线进行仿真时受害线上感应出的串扰噪声,与仅有码间串扰的受前导位影响下降边响应信号相加,获得有串扰噪声时的受前导位影响下降边响应信号; When the victim line [0029] (5i) will offensive line simulation induced crosstalk noise, inter-symbol interference only by the falling edge of the leading bit influence the response signal together to get affected by the leading bit of the crosstalk noise falling edge of the response signal;

[0030] (5 j)对有串扰噪声时的受前导位影响下降边响应信号,从采样起点处以下降边信号01010100000的一个位宽为间隔开始采样,采样15次,每次采样50个点,获得15组有串扰噪声时的受前导位影响下降边响应信号向量。 [0030] (5 j) Effect of preamble bits when receiving the crosstalk noise signal in response to a falling edge, starting from the sampling signal a falling edge of the bit width impose 01010100000 to begin sampling interval, sample 15 times, 50 points per sample, Effects obtained by the leading bit of the crosstalk noise signal 15 in response to a falling edge set vector.

[0031] ⑶获得最坏码型序列向量: [0031] ⑶ obtained worst pattern vector sequence:

[0032] 采用格子法,对有串扰噪声时的受前导位影响上升边和下降边响应信号向量进行计算,得到最坏累计电压和引起最坏眼图的最坏码型序列向量。 [0032] The grid method, the influence to the preamble bits by crosstalk noise during rising and falling edge of the response signal vector has been calculated, the cumulative voltage and cause the worst worst worst eye pattern vector sequence.

[0033] ⑵获得预估的最坏眼图: [0033] ⑵ obtain estimates of the worst eye:

[0034] 将获得的最坏码型序列向量加载到通用模拟电路仿真器SPICE模型中进行仿真, 将仿真结果加载到通用模拟电路仿真器SPICE波形查看器中,查看最坏眼图,记录最坏眼高和眼宽。 [0034] The worst pattern is loaded into the sequence of vectors obtained simulator SPICE model generic analog circuit simulation, the simulation result is loaded into the general-purpose analog circuit simulator SPICE waveform viewer to view the worst eye, recording the worst eye height and width.

[0035] ⑶仿真并行高速链路系统的最坏眼图: [0035] ⑶ simulation speed parallel link system worst eye:

[0036]用通用模拟电路仿真器SPICE生成上升边和下降边不对称的输入信号,将输入信号加载到步骤⑵中的并行高速链路系统的通用模拟电路仿真器SPICE模型中进行仿真,将仿真结果加载到通用模拟电路仿真器SPICE波形查看器中,查看最坏眼图,记录最坏眼高和眼宽。 [0036] SPICE generate rising and falling edges of the input signal with asymmetrical general analog circuit simulator, the input signal is loaded into a general analog simulator SPICE model circuit speed parallel link system in step ⑵ for simulation, emulation results loaded into a general analog circuit simulator SPICE waveform viewer, the worst eye view, high recording worst eye height and width.

[0037] (9)获得预估精度的绝对误差: [0037] (9) obtains an absolute error of prediction accuracy:

[0038] (9a)将步骤⑶中的最坏眼高与步骤(7)中预估的最坏眼高代入下式,计算预估最 In [0038] (9a) in step ⑶ worst eye height of step (7) the estimated worst eye height into the following equation to calculate the estimated most

[0040] 其中:nH表示预估最坏眼高Η的绝对误差,Hbtds表示用最优时域方法BTDS预估的最坏眼高H,H SPICE表示用通用模拟电路仿真器SPICE仿真的最坏眼高H; [0040] wherein: nH denotes the absolute error of the estimated worst eye height Η, Hbtds represented by a time domain method BTDS optimal estimate of the worst eye height H, H SPICE simulation represented by general analog SPICE circuit simulator worst eye height H;

[0041] (9b)将步骤⑶中的最坏眼宽与步骤(7)中预估的最坏眼宽代入下式,计算眼宽的绝对误差; In [0041] (9b) in step ⑶ worst eye width of step (7) the estimated worst eye width into the following equation to calculate the absolute error of the eye width;

Figure CN104143024BD00091

坏眼高的绝对误差; Bad eye high absolute error;

Figure CN104143024BD00092

[0043] 其中:nw表示预估最坏眼宽W的绝对误差,WBTDS表示用最优时域方法BTDS预估的最坏眼宽W,Wspke表示用通用模拟电路仿真器SPICE仿真的最坏眼宽W; [0043] where: nw represents a worst case estimate of the absolute error of the eye width W, WBTDS represented by the best estimate of the time domain method BTDS worst eye width W, Wspke represented by general analog simulator SPICE circuit simulator worst eye W is wide;

[0044] (9c)将输入信号位宽减去最坏眼宽得到峰峰值抖动,将峰峰值抖动代入下式,计算峰峰值抖动绝对误差; [0044] (9c) bit width of the input signal obtained by subtracting the worst eye width jitter peak, the peak to peak jitter into the following equation to calculate the peak to peak jitter absolute error;

Figure CN104143024BD00093

[0046] 其中:ru表示预估峰峰值抖动J的绝对误差,Jbtds表示用最优时域方法BTDS预估的峰峰值抖动J,Jspke表示用通用模拟电路仿真器SPICE仿真的峰峰值抖动J。 [0046] wherein: ru estimated peak jitter J represents absolute error, Jbtds peak represented by an optimal time-domain prediction method BTDS jitter J, Jspke represents a peak to peak jitter general analog circuit simulator SPICE simulation J.

[0047] 本发明与现有技术相比具有以下优点: [0047] The present invention and the prior art has the following advantages:

[0048] 第一,本发明通过对上升边和下降边向量进行多相位采样,克服了现有技术对于脉冲边沿不对称及器件非线性系统驱动器有可能无法得到最坏码型和最坏眼图的缺点,使得本发明具有能够对于脉冲边沿不对称及器件非线性系统驱动器准确的获得最坏码型和最坏眼图的优点。 [0048] First, the present invention is carried out by multi-phase sampling of the rising and falling edge vectors, the prior art overcomes the asymmetry of the pulse edge for nonlinear systems driver device may not be obtained and the worst pattern worst eye shortcomings, the present invention has the advantage that can be obtained accurately and the worst pattern for the worst eye asymmetric pulse edges and nonlinear system drive device.

[0049] 第二,本发明通过将最优时域仿真方法BTDS工程化为最优时域的仿真工具(Best Time-Domain Simulation Tools BTDS_Tools),可以方便的仿真出眼宽、眼高和抖动数据值,克服了现有技术对信号抖动参数的计算描述不够明确,并且眼宽的计算精度不高的缺点,使得本发明具有能够得到精确的眼宽,抖动数据的优点。 [0049] Second, the present invention is optimum by the time domain simulation method BTDS engineered to optimal time domain simulation tool (Best Time-Domain Simulation Tools BTDS_Tools), can easily be simulated eye width, jitter and eye height data value, calculated on the prior art are overcome jitter parameter description is not clear enough, and eye width calculation accuracy is not high shortcomings, the present invention has such a precise eye width can be obtained, the advantages of the dithering data.

[0050] 第三,本发明中通过将并行高速链路系统的时域仿真结果在图形用户界面中显示,用户可以清晰的看到仿真结果进而判断出所设计并行高速链路系统的优劣,克服现有技术没有直观显示仿真结果的缺点,使得本发明具有能够清楚的查看仿真结果的优点。 [0050] Third, the present invention is a high speed by the parallel link system time-domain simulation result is displayed in a graphical user interface, the user can clearly see the simulation results then identify the link system designed for high-speed parallel merits overcome the prior art does not visually display the results of the simulation, so that the present invention is capable of having a clear view of the advantages of the simulation results.

附图说明 BRIEF DESCRIPTION

[0051] 图1是本发明的流程图; [0051] FIG. 1 is a flow chart of the present invention;

[0052]图2是本发明的仿真图。 [0052] FIG. 2 is a simulation diagram of the present invention.

具体实施方式 detailed description

[0053]下面结合附图对本发明作进一步的描述。 [0053] The following figures present invention will be further described in connection with.

[0054] 参照图1对本发明的实施步骤作进一步的描述。 [0054] Referring to FIG. 1 embodiment of the present invention, the step will be further described.

[0055] 步骤1,选用并行高速链路系统。 [0055] Step 1, use a high-speed parallel link system.

[0056] 本发明的实施例中并行高速链路系统选用海力士公司生产的SKhynix的第三代双倍数据率同步动态随机存取存储器(Double-Data-Rate Three Synchronous Dynamic Random Access Memory DDR3)并行高速链路系统进行时域仿真。 Example [0056] In the present invention a high-speed parallel link system selected Hynix produced double-data-rate SKhynix synchronous dynamic random access memory (Double-Data-Rate Three Synchronous Dynamic Random Access Memory DDR3) parallel domain simulation at high speed link system.

[0057] 步骤2,建立SPICE模型。 [0057] Step 2, SPICE model.

[0058] 将并行高速链路系统中的线宽、线间距、介质厚度、介电常数、损耗因子和传输线厚度参数值,赋给通用模拟电路仿真器SPICE模型中对应的参数,完成并行高速链路系统的通用模拟电路仿真器SPICE模型的建立。 [0058] A high-speed parallel link system in line width, line spacing, dielectric thickness, dielectric constant, loss factor, and the transmission line thickness parameter values, the parameter assigned to general analog circuit simulator SPICE models corresponding to complete high-speed parallel chains establish a common analog circuit simulator SPICE model of the road system.

[0059] 步骤3,获得边沿响应信号。 [0059] Step 3 to give the response signal edge.

[0060] 将基准的上升边信号00000001111加载到通用模拟电路仿真器SPICE模型中进行仿真,得到基准上升边响应信号。 [0060] The rising edge of the reference signal is loaded into the simulator 00000001111 SPICE model simulation in general analog circuit to obtain the reference signal in response to rising edge.

[0061] 将基准的下降边信号11111110000加载到通用模拟电路仿真器SPICE模型中进行仿真,得到基准下降边响应信号。 [0061] The falling edge of the reference signal is loaded into the simulator 11111110000 SPICE model simulation in general analog circuit to obtain the reference signal in response to a falling edge.

[0062] 将有前导位0101010的上升边信号01010101111和零信号01010100000加载到通用模拟电路仿真器SPICE模型中进行仿真,将这两个信号的仿真结果相减,得到受前导位影响上升边响应信号。 [0062] The leading bit will have a rising edge of signal 0101010 01010101111 01010100000 zero signal and loaded into a general analog circuit simulator SPICE model simulation, the simulation result of these two signals are subtracted to give a response signal by the side impact rising leading bit .

[0063] 将有前导位0101010的零信号01010100000加载到通用模拟电路仿真器SPICE模型中进行仿真,得到受前导位影响下降边响应信号。 [0063] The leading bit will be a zero signal 01010100000 0101010 is loaded into a general analog circuit simulator SPICE models for simulation to give a response signal by the falling edge leading bit affected.

[0064] 步骤4,计算仿真阶数。 [0064] Step 4, the simulation calculation order.

[0065] 按照下式,计算仿真并行高速链路系统中最坏眼图的阶数: [0065] The number of the following formula, calculated simulation speed parallel link system in accordance with the order of the worst eye:

Figure CN104143024BD00101

[0067] 其中:N表示仿真并行高速链路系统中最坏眼图的阶数,T表示基准上升边响应信号和受前导位影响上升边响应信号相减的差值大于〇. 1 %的持续时间,t表示基准上升边响应信号的上升边的上升时间。 [0067] where: N represents the order of the simulation of parallel high-speed links worst eye system, T represents the reference signal in response to the rising edge and the influence by the leading bit in response to the rising edge of the signal subtracting square difference is greater than 1% of the duration. time, t represents the leading edge of the reference signal in response to the rise time of the rising edge.

[0068] 步骤5,获得上升边和下降边向量。 [0068] Step 5 gave the rising and falling edge vectors.

[0069] 将受前导位影响上升边响应信号值,与逻辑0响应信号值之差超过0.001的第一个点,设定为受前导位影响上升边响应信号的采样起点。 [0069] The influence by the rising edge of the leading bit response signal, a first point difference between the signal value of more than 0.001 and a logic 0 in response, set by the rising edge of the leading bit of the influence signal in response to the sampling start point.

[0070] 将有前导位0101010的上升边信号01010101111,加载到通用模拟电路仿真器SPICE模型中,对模型中任意一根进攻线进行仿真,获得仅有码间串扰的受前导位影响上升边响应信号。 [0070] The leading bit will be the rising edge of signal 01010101111 0101010, is loaded into the general-purpose analog circuit simulator SPICE models, a model of any offensive line simulation, obtained by the rise only between the leading bit of the influence of ISI edge Response signal.

[0071] 对仅有码间串扰的受前导位影响上升边响应信号,从采样起点处以上升边信号01010101111的一个位宽为间隔进行采样,采样15次,每次采样50个点,获得15组仅有码间串扰的受前导位影响上升边响应信号向量。 [0071] a response signal on the side of inter-symbol interference only by the impact of rising leading bit, starting from the sampling bit width impose a rising edge of the signal sampling interval is 01010101111, samples 15, 50 points per sample to obtain a set of 15 only the leading bit is affected by inter-symbol interference in response to the rising edge of the signal vector.

[0072] 将对进攻线进行仿真时受害线上感应出的串扰噪声,与仅有码间串扰的受前导位影响上升边响应信号相加,获得有串扰噪声时的受前导位影响上升边响应信号。 Victim line crosstalk noise induced [0072] will be simulated offensive line, only inter-symbol interference by adding the side signal in response to the impact of rising leading bit, that bit preamble when affected by crosstalk noise rise edge Response signal.

[0073] 对有串扰噪声时的受前导位影响上升边响应信号,从采样起点处以上升边信号01010101111的一个位宽为间隔进行采样,采样15次,每次采样50个点,获得15组有串扰噪声时的受前导位影响上升边响应信号向量。 [0073] Effect of bits crosstalk noise when receiving a preamble signal in response to rising edge, starting from the sampling bit width of a rising edge of the signal imposed 01010101111 sampling interval, sample 15 times, 50 points per sample to obtain 15 group when the preamble bit affected by crosstalk noise in response to the rising edge of the signal vector.

[0074] 将受前导位影响下降边响应信号值,与逻辑1响应信号值之差超过0.001的第一个点,设定为受前导位影响下降边响应信号的采样起点。 [0074] The influence by the falling edge of the leading bit response signal, a first point difference between the signal value of more than 0.001 and logic 1 in response, the leading bit is set by the falling edge of the influence signal in response to the sampling start point.

[0075] 将有前导位0101010的下降边信号01010100000,加载到通用模拟电路仿真器SPICE模型中,对模型中任意一根进攻线进行仿真,获得仅有码间串扰的受前导位影响下降边响应信号。 [0075] The leading bit will have a falling edge of signal 01010100000 0101010, is loaded into the general-purpose analog circuit simulator SPICE models, a model of any offensive line simulation, only inter symbol interference is obtained by the decrease in response to the leading edge position Effect signal.

[0076] 对仅有码间串扰的受前导位影响下降边响应信号,从采样起点处以下降边信号01010100000的一个位宽为间隔开始采样,采样15次,每次采样50个点,获得15组仅有码间串扰的受前导位影响下降边响应信号向量。 [0076] The inter-symbol interference only by a falling edge leading bit influence a response signal from the sampling signal a falling edge of the start point impose 01010100000 bit width of the start interval sampling, the sampling times 15, 50 points per sample to obtain a set of 15 only the leading bit is affected by inter-symbol interference in response to the falling edge of the signal vector.

[0077] 将对进攻线进行仿真时受害线上感应出的串扰噪声,与仅有码间串扰的受前导位影响下降边响应信号相加,获得有串扰噪声时的受前导位影响下降边响应信号。 Victim line crosstalk noise induced [0077] will be simulated offensive line, inter-symbol interference is decreased by only the leading edge of the response signal bit affects together to get affected by the leading bit of the crosstalk noise in response to a falling edge signal.

[0078] 对有串扰噪声时的受前导位影响下降边响应信号,从采样起点处以下降边信号01010100000的一个位宽为间隔开始采样,采样15次,每次采样50个点,获得15组有串扰噪声时的受前导位影响下降边响应信号向量。 [0078] Effect on when the leading bit of the crosstalk noise signal in response to receiving a falling edge, starting from the sampling signal a falling edge of the bit width impose 01010100000 to begin sampling interval, sample 15 times, 50 points per sample to obtain 15 group when the leading bit affected by crosstalk noise falling edge of the response signal vector.

[0079] 步骤6,获得最坏码型序列向量。 [0079] Step 6 gave the worst pattern vector sequence.

[0080] 采用格子法,对有串扰噪声时的受前导位影响上升边和下降边响应信号向量进行计算,得到最坏累计电压和引起最坏眼图的最坏码型序列向量。 [0080] The grid method, the influence to the preamble bits by crosstalk noise during rising and falling edge of the response signal vector has been calculated, the cumulative voltage and cause the worst worst worst eye pattern vector sequence.

[0081] 格子法的具体步骤如下: [0081] DETAILED grid method steps are as follows:

[0082] 第一步,将仅有码间串扰的受前导位影响上升边响应信号向量的第一组值与1相减,得到使用格子法计算所需的上升边向量,标记为R(l,t),t = l,2,......,50,其中,R(l, t)表示使用格子法计算所需的上升边向量中第一组仅有码间串扰的受前导位影响上升边响应信号向量,t表示使用格子法计算所需的上升边向量所包含的值的个数。 [0082] The first step, only the inter-symbol interference influence by the leading bit in response to the rising edge of a first set of values ​​of the signal vector and subtracting 1, to give the desired leading edge vector is calculated using the grid method, labeled R (l , t), t = l, 2, ......, 50, where, R (l, t) represents the calculated desired rise edge vectors between the first set only by the preamble symbol interference method using a lattice Effect of bits in response to the rising edge of the signal vector, t is the number of values ​​required for Trellis rising edge vector calculation method included.

[0083] 第二步,将仅有码间串扰的受前导位影响下降边响应信号向量的第一组值与1相减,得到使用格子法计算所需的下降边向量,标记为F(l,t),t = l,2,......,50,其中,F(l, t)表示使用格子法计算所需的下降边向量中的第一组仅有码间串扰的受前导位影响下降边响应信号向量,t表示使用格子法计算所需的上升边向量所包含的值的个数。 [0083] a second step of receiving the first set of values ​​affect the falling edge of the leading bit of response signal vector only inter-symbol interference and subtracting 1, to give the desired decreased edge vectors calculated using the grid method, labeled F (l , t), t = l, 2, ......, 50, where, F (l, t) is calculated between the required indication of a falling edge in the first group only vector symbol interference lattice law Effect of the leading bit in response to a falling edge signal vector, t is the number of values ​​required for Trellis rising edge vector calculation method included.

[0084] 第三步,用Ai, i,i = 1,2,......,51表示码间串扰对高电平的累积影响电压,其中, i表示码间串扰对高电平的累积影响电压的向量组数;用81;1,1 = 1,2,......,51表示码间串扰对低电平的累积影响电压,其中,i表示码间串扰对低电平的累积影响电压的向量组数;设高电平累积影响电压Ax, i = 0,低电平累积影响电压h, i = 0 ;用Μη (1,i),i = 1, 2,......,51表示引起高电平累积电压的向量,用ML(l,i),i = l,2,......,51表示引起低电平L累积电压的向量。 [0084] the third step, Ai, i, i = 1,2, ......, 51 represents the cumulative effects of intersymbol interference on a high level voltage, wherein, i denotes the high level of intersymbol interference the cumulative vector set applied voltage; 81 a; 1,1 = 1,2, ......, the cumulative effects of voltage on the low level of crosstalk between the symbol 51 represents, where, i denotes a low intersymbol interference the number of cumulative vectors affected by the voltage level; the cumulative effects of high-level voltage provided Ax, i = 0, the cumulative effects of low-level voltage h, i = 0; with Μη (1, i), i = 1, 2, ......, 51 represents a voltage caused by the high level accumulation vector, by ML (l, i), i = l, 2, ......, 51 denotes a low level due to a vector of cumulative voltage L .

[0085] 第四步,用Κ(Α14,Α14+1) =0表示上升边向量中从第i个高电平的累积影响电压A1;i 转变到第1 + 1个高电平的累积影响电压414+1的累加值为0;用? [0085] The fourth step, by Κ (Α14, Α14 + 1) = 0 represents a rising edge of the voltage vector from the cumulative effects of high i-th A1; transition to the cumulative effects of the first i + 1 is a high level accumulating a voltage value of 0 + 414; use? 出14,814+1)=0表示下降边向量中从第i个低电平的累积影响电压Bl>1转变到第i+1个低电平的累积影响电压Bl,1+1的累加值为〇;用? The 14,814 + 1) = 0 represents the falling edge vector> 1 transition from the cumulative effects of voltage Bl i-th low-level voltage to the cumulative impact of the i + 1 th Bl low level, the accumulated value of the square 1 + 1 ;use? 0 1,1,81,1+1)=?(14)表示下降边向量中从第1个高电平的累积影响电压仏转变到第1+1个低电平的累积影响电压& +1的累加值为? 1,1,81,1 1 + 0) =? (14) represent vector Fo falling edge transition from the cumulative effects of a high voltage to a low level 1 + 1 + 1 of cumulative effects of voltage & the cumulative value? (14);用1?出14,414+1)=1?(14)表示上升边向量中从第i个低电平的累积影响电压仏转变到第i+Ι个高电平的累积影响电压A 1+1 的累加值为R(l,i)。 (14);? 14,414 with a + 1) = 1 (14) shows a rising edge transition from the vector Fo cumulative effects of the i-th low-level voltage to the i th + iota A high voltage cumulative effects? 1 + 1 is the accumulated value of R (l, i).

[0086] 第五步,从有串扰噪声时的受前导位影响上升边和下降边响应信号向量第0个到第50个值中依次的查找信号向量的负值,记录负值的位置i;当高电平累积电压向量Mh (l,i +1)的第i+1个值为1时,第i个高电平累积电压A1;1转变到第i+1个高电平累积电压A1>1+1的累加值为R(Ai,Ai+1);当高电平累积电压的向量MH(l,i+l)的第i+Ι个值为0时,第i个高电平累积电压Ax, i转变到第i+1个高电平累积电压Ai, i+1的累加值为F (Ai,Bi+1);当查找出信号向量的所有负值时,得到由第一组有串扰噪声时的受前导位影响上升边响应信号向量引起的总的高电平累积电压Al,51。 [0086] The fifth step, when the crosstalk noise from the influence by the leading bit in response to rising and falling edges of the signal vector of 0 to 50 lookup values ​​sequentially negative signal vector, negative recording position I; when the accumulation of high voltage vector Mh (l, i +1) of the i + 1-th value of 1, the i-th high cumulative voltage A1;. 1 transitions to the high level i + 1-th cumulative voltage A1 > integrated value of R (Ai, Ai + 1) 1 + 1; and when the cumulative high voltage vector MH (l, i + l) th of i + Ι is 0, the i-th high level cumulative voltage Ax, i i + 1 transitions to the first plurality of high levels cumulative voltage Ai, the accumulated value F (Ai, Bi + 1) i + 1; and when to find out all the negative signal vector, obtained from the first group when the preamble bits affected by crosstalk noise rising edge of the high level in response to the total cumulative voltage signal vector caused by Al, 51.

[0087] 第六步,重复第五步,直到得出所有有串扰噪声时的受前导位影响上升边响应信号向量弓丨起的总的高电平累积电压A2,51,A3,51,A4,51,A5,51,......Al4,51, Al4,51 〇 [0087] The sixth step, the fifth step is repeated until all the results when the preamble bits are affected by the crosstalk noise signal in response to the rising edge of the bow Shu vector from total cumulative high voltage A2,51, A3,51, A4 , 51, A5,51, ...... Al4,51, Al4,51 square

[0088] 第七步,比较这十五个总的高电平累积电SAn,51,n=l,2,3,......15,得出最坏的累积电压Aj, 51;引起最坏累积电压Aj, 51的码型向量为Mh (j,i),i = 1,2,......,51,其中, Μη (j,i)表示高电平H的最坏累积电压的码型向量。 [0088] The seventh step of comparing the total of fifteen electric high accumulation SAn, 51, n = l, 2,3, ...... 15, come to the worst cumulative voltage Aj, 51; causing the worst cumulative voltage Aj, the pattern 51 is a vector Mh (j, i), i = 1,2, ......, 51, wherein, Μη (j, i) represents the most high level H bad cumulative voltage vector pattern.

[0089] 第八步,从仅有码间串扰的受前导位影响上升边响应信号向量的第0个到第50个值中依次的查找信号向量的正值,记录正值的位置i;当低电平累积电压向量Ml (l,i + l)的第i+1个值为〇时,第i个低电平累积电压B1;1转变到第i+1个低电平累积电压B1>1+1的累加值为F(Bi,B i+1);当低电平累积电压的向量MU14+1)的第i+Ι个值为1时,第i个低电平累积电压B1;i转变到第i+Ι个低电平累积电压B 1>i+1的累加值为R(Bi,Ai+1);当查找出信号向量的所有正值时,得到由第一组仅有码间串扰的受前导位影响上升边响应信号向量引起的总的低电平累积电压Bl, 51。 [0089] The eighth step, the edge value of 0 in response to a signal vector of 50 values ​​sequentially lookup signal vector by the inter-symbol interference only the impact of rising leading bit, the recording position i from value; when low accumulation voltage vector Ml (l, i + l) when the i + 1 is square, the i-th low-level cumulative voltage B1; 1 transitions to the low level i + 1-th cumulative voltage B1> 1 is incremented by 1 + F (Bi, B i + 1); when the vector MU14 + 1) cumulative voltage low level of the i th value iota + 1, the i-th low accumulation voltage Bl; i i + Ι transition to a low level of voltage B integrated value of the accumulated R (Bi, Ai + 1) 1> i + 1; and when the signal vector to find out all positive values, obtained by the first set only intersymbol interference in response to receiving the leading edge of the bit affects the increase of the total cumulative voltage low level signal vector caused Bl, 51.

[0090] 第九步,重复步骤八直到得出其余十四组仅有码间串扰的受前导位影响上升边响应信号向量引起的总的低电平累积电压B2,51,B3,51,B4,51,B5,51,......Bl4,51, Bl4,51 〇 [0090] The ninth step, the step is repeated until the eight derived code among the fourteen other groups only in response side crosstalk impact by the leading bit of the low level of total cumulative voltage rising signal vectors caused B2,51, B3,51, B4 , 51, B5,51, ...... Bl4,51, Bl4,51 square

[0091] 第十步,比较这十五个总的低电平累积电压仏,51,11=1,2,3,......15,得出最坏的累积电压Bj,51,引起最坏累积电压Bj,51的码型向量为Ml (j,i),i = 1,2,......,51,其中, MUj,i)表示低电平L的最坏累积电压的码型向量。 [0091] The tenth step, comparing the accumulated fifteen total low level voltage Fo, 51,11 = 2,3, ...... 15, come to the worst cumulative voltage Bj, 51, causing the worst cumulative voltage Bj, the pattern 51 is a vector Ml (j, i), i = 1,2, ......, 51, wherein, MUj, i) represents the cumulative worst low level L voltage vector pattern.

[0092] 以上步骤为用格子法对有串扰噪声时的受前导位影响上升边响应信号向量和仅有码间串扰的受前导位影响上升边响应信号向量进行计算,得到最坏累计电压和引起最坏眼图的最坏码型序列向量。 [0092] The above steps for the worst total voltage induced by the leading bit and the impact between the rising edge of the response signal vector and the code only in response to receiving the leading edge of crosstalk impact of rising bit signal vector calculated at the crosstalk noise obtained by lattice method the worst pattern vector sequence worst eye of FIG.

[0093] 步骤7,获得预估的最坏眼图。 [0093] Step 7, to obtain the estimated worst eye.

[0094] 将获得的最坏码型序列向量加载到通用模拟电路仿真器SPICE模型中进行仿真, 将仿真结果加载到通用模拟电路仿真器SPICE波形查看器中,查看最坏眼图,记录最坏眼高和眼宽。 [0094] The worst pattern is loaded into the sequence of vectors obtained simulator SPICE model generic analog circuit simulation, the simulation result is loaded into the general-purpose analog circuit simulator SPICE waveform viewer to view the worst eye, recording the worst eye height and width.

[0095] 步骤8,仿真并行高速链路系统的最坏眼图。 [0095] Step 8, the simulation of parallel high-speed link system worst eye.

[0096] 用通用模拟电路仿真器SPICE生成上升边和下降边不对称的输入信号,将输入信号加载到步骤⑵中的并行高速链路系统的通用模拟电路仿真器SPICE模型中进行仿真,将仿真结果加载到通用模拟电路仿真器SPICE波形查看器中,查看最坏眼图,记录最坏眼高和眼宽。 [0096] SPICE generate rising and falling edges of the input signal with asymmetrical general analog circuit simulator, the input signal is loaded into a general analog simulator SPICE model circuit speed parallel link system in step ⑵ for simulation, emulation results loaded into a general analog circuit simulator SPICE waveform viewer, the worst eye view, high recording worst eye height and width.

[0097] 步骤9,获得预估精度的绝对误差。 [0097] Step 9, to obtain the absolute error of estimate accuracy.

[0098] 将步骤⑶中的最坏眼高与步骤⑵中预估的最坏眼高代入下式,计算预估最坏眼高的绝对误差。 [0098] Step ⑶ high in the worst eye in step ⑵ estimated worst eye height into the following equation to calculate the estimated worst eye high absolute error.

Figure CN104143024BD00121

[0100] 其中:ΠΗ表示预估最坏眼高Η的绝对误差,HBTDS表示用最优时域方法BTDS预估的最坏眼高H,H SPICE表示用通用模拟电路仿真器SPICE仿真的最坏眼高H。 [0100] wherein: ΠΗ represents the absolute error of the estimated worst eye height Η, HBTDS represented by a time domain method BTDS optimal estimate of the worst eye height H, H SPICE simulation represented by general analog SPICE circuit simulator worst eye height H.

[0101] 将步骤⑶中的最坏眼宽与步骤⑵中预估的最坏眼宽代入下式,计算眼宽的绝对误差。 [0101] Step ⑶ the worst eye width in step ⑵ estimated worst eye width into the following equation to calculate the absolute error of the eye width.

Figure CN104143024BD00131

[0103] 其中:nw表示预估最坏眼宽W的绝对误差,WBTDS表示用最优时域方法BTDS预估的最坏眼宽W,Wspke表示用通用模拟电路仿真器SPICE仿真的最坏眼宽W。 [0103] where: nw represents a worst case estimate of the absolute error of the eye width W, WBTDS represented by the best estimate of the time domain method BTDS worst eye width W, Wspke represented by general analog simulator SPICE circuit simulator worst eye width W.

[0104] 将输入信号位宽减去最坏眼宽得到峰峰值抖动,将峰峰值抖动代入下式,计算峰峰值抖动绝对误差。 [0104] The bit width of the input signal obtained by subtracting the worst eye width jitter peak, the peak to peak jitter into the following equation to calculate the peak to peak jitter absolute error.

Figure CN104143024BD00132

[0106] 其中:ru表示预估峰峰值抖动J的绝对误差,Jbtds表示用最优时域方法BTDS预估的峰峰值抖动J,Jspke表示用通用模拟电路仿真器SPICE仿真的峰峰值抖动J。 [0106] wherein: ru estimated peak jitter J represents absolute error, Jbtds peak represented by an optimal time-domain prediction method BTDS jitter J, Jspke represents a peak to peak jitter general analog circuit simulator SPICE simulation J.

[0107] 下面结合仿真实验对本发明效果做进一步的描述。 [0107] Next, the simulation on the effects of the present invention will be further described.

[0108] 1.仿真条件。 [0108] 1. The simulation conditions.

[0109] 本发明的仿真条件采用通用模拟电路仿真器SPICE仿真工具、峰值失真分析仿真工具PDA_Tools、最优时域仿真方法仿真工具BTDS_Tools、海力士Skhynix decks文件; [0109] Simulation conditions of the present invention employs a general-purpose analog circuit simulator SPICE simulation tools, simulation tools peak distortion analysis PDA_Tools, the optimal time-domain simulation simulation tool BTDS_Tools, Hynix Skhynix decks file;

[0110] 2.仿真过程 [0110] 2. The simulation process

[0111] 将海力士Skhynix decks文件的参数设置如下:上升边为20ps,下降边为50ps,位周期UI为750ps,步长10ps,仿真时间为40ns。 [0111] The parameter file Hynix Skhynix decks as follows: the rising edge of 20ps, falling edge of 50ps, UI bit period of 750ps, step 10ps, the simulation time is 40ns.

[0112] 对峰值失真分析Η)Α和最优时域BTDS仿真方法的仿真结果进行验证,将其预测的眼图的预测结果与用其得到的码型放入通用模拟电路仿真器SPICE仿真得到的眼图结果进行对比,误差应小于5%,用以下公式计算并验证误差对比结果。 [0112] Verify peak distortion analysis, [eta]) and simulation results Α optimal time domain simulation method of BTDS, the prediction result of the prediction of the eye pattern and its use was put general analog circuit simulator SPICE simulation to give the results were compared eye, the error should be less than 5%, calculated by the following equation and comparing the results to verify the error.

Figure CN104143024BD00133

[0115] 其中:ΠΗ表示预估最坏眼高Η的绝对误差,Hbtds表示用最优时域方法BTDS预估的最坏眼高H,H SPke表示用通用模拟电路仿真器SPICE仿真的最坏眼高出取表示预估最坏眼宽W 的绝对误差,Wbtds表不用最优时域方法BTDS预估的最坏眼宽W,Wspke表不用通用模拟电路仿真器SPICE仿真的最坏眼宽W。 [0115] wherein: ΠΗ represents the absolute error of the estimated worst eye height Η, Hbtds represented by a time domain method BTDS optimal estimate of the worst eye height H, H SPke represented by general analog simulator SPICE circuit simulator worst comparing the estimated worst case takes eye showing eye width W, Wspke table without general analog circuit simulator SPICE simulation of the worst eye width W of the absolute error, Wbtds table not optimal time-domain prediction method BTDS worst eye width W .

[0116] 对峰值失真分析roA和最优时域BTDS仿真方法的仿真结果进行验证的具体操作步骤如下。 [0116] Specific steps of the simulation results roA peak distortion analysis and optimal time-domain simulation to verify BTDS follows.

[0117] 第一步,首先把通用模拟电路仿真器SPICE仿真得到的trO文件导入峰值失真分析仿真工具roA_T〇〇ls,获得眼图眼高,眼宽及抖动参数值。 [0117] The first step, the general analog circuit simulator SPICE simulation obtained trO file into roA_T〇〇ls peak distortion analysis, simulation tools, to obtain a high eye eye, eye width and jitter parameters. 然后把依据峰值失真分析PDA方法得到的码型导入通用模拟电路仿真器SPICE中仿真,记录得到的眼高,眼宽及抖动值。 Then based on the peak distortion analysis PDA pattern obtained by the method introduced general analog circuit simulator SPICE simulation in, to give high recording eye, eye width and jitter value. 仿真结果表明,峰值失真分析仿真工具PDA_T 〇〇ls预测得到的眼高为666.6mv,眼宽为531.4ps。 Simulation results show that the peak distortion analysis simulation tool PDA_T 〇〇ls predicted eye height 666.6mv, eyes wide 531.4ps. 通用模拟电路仿真器SPICE中测量得到的眼高为809mv,眼宽为608ps。 General analog circuit simulator SPICE obtained measured eye height is 809mv, the eye width of 608ps. 眼高及眼宽误差均超过10%,从以上数据可以得出如下结论:峰值失真分析PDA方法无法处理上升边和下降边不对称的情况。 High eyes and eye width errors are more than 10% from the above data the following conclusions can be drawn: PDA peak distortion analysis method can not handle the situation rising and falling edges asymmetric.

[0118] 第二步,采用最优时域仿真方法BTDS得到的眼高预测结果为793mv,眼宽则为698.4ps。 [0118] The second step, using the optimum eye height prediction results obtained time domain simulation method BTDS is 793mv, the eye width was 698.4ps. 用最优时域仿真方法BTDS得到的码型放入通用模拟电路仿真器SPICE仿真得到的眼高为795mv,眼宽则为697ps,仿真结果如图2所示。 Into generic analog circuit simulator with the optimal pattern obtained time domain simulation method BTDS SPICE simulation obtained eye height is 795mv, was eye width 697ps, the simulation results shown in FIG. 其中图2 (a)和2 (b)是采用本发明最优时域的仿真方法BTDS预测的轮廓及眼图;图2 (c)和2 (d)是采用现有技术最优时域的仿真方法BTDS生成的码型序列放入通用模拟电路仿真器SPICE仿真得到的眼图。 Wherein FIG. 2 (a) and (b) is a simulation method of the present invention is the optimal use of the time domain and the predicted contour eye BTDS FIG. 2; FIG. 2 (c) and 2 (d) is the use of prior art time-domain optimal generated simulation BTDS eye pattern sequences into general analog circuit simulator SPICE simulation obtained.

[0119] 第三步,用最优时域仿真方法BTDS预测的抖动为189.2ps。 [0119] the third step, the optimal time-domain simulation BTDS predicted jitter 189.2ps. 将预测得到的码型放入通用模拟电路仿真器SPICE中验证,得到的抖动为196.13ps,仿真结果如图2 (c)和2 (d)。 The predicted pattern into the general-purpose analog circuit simulator SPICE verifying, obtained jitter 196.13ps, simulation results in FIG. 2 (c) and 2 (d). 对峰值失真分析PDA仿真方法、本发明最优时域BTDS仿真方法以及通用模拟电路仿真器SPICE 的仿真结果如下表。 PDA peak distortion analysis simulation, the present invention is an optimal time-domain simulation method and BTDS general analog circuit simulator SPICE simulation results in the following table.

Figure CN104143024BD00141

[0121] 其中:PDA表示峰值失真分析仿真方法,SPICE表示使用通用模拟电路仿真器的仿真方法,BTDS表示最优时域仿真方法。 [0121] wherein: PDA indicates a peak distortion analysis simulation, SPICE simulation using the general method represents an analog circuit simulator, BTDS represents the optimal time-domain simulation.

[0122] 3.仿真结果及分析。 Results and Analysis [0122] 3. Simulation.

[0123] 通过与通用模拟电路仿真器SPICE仿真结果对比可知,本发明中的最优时域仿真方法BTDS得到的眼宽、眼高以及抖动误差的绝对值均小于5%。 [0123] By comparison with known results of SPICE simulation general analog circuit simulator, the optimal time-domain simulation method of the present invention is obtained BTDS eye width, eye and jitter error of a high absolute value of less than 5%.

[0124] 本发明的最优时域仿真方法BTDS既能够解决并行高速链路系统驱动器边沿不对称问题又可以得到最坏的码型及眼图,通过上表的仿真数据可以证明本发明优于峰值失真分析PDA时域仿真方法和双边沿响应DER时域仿真方法,并且得出了眼宽和抖动的数据,又优于多边沿响应MER时域仿真方法。 [0124] BTDS optimal time-domain simulation method of the present invention can solve both the high-speed parallel link system drive can be edge asymmetry and the worst pattern and eye diagram, simulated by the data in the table demonstrate the present invention can be superior to peak distortion analysis PDA DER domain simulation method and the simulation method in time domain response double edge, and eye width and jitter obtained the data, but also better than the multiple edge time domain simulation method MER response.

Claims (1)

  1. 1. 一种并行高速链路系统的快速时域仿真方法,具体步骤如下: (1)选用并行高速链路系统; ⑵建立SPICE模型: 将并行高速链路系统中的线宽、线间距、介质厚度、介电常数、损耗因子和传输线厚度参数值,赋给通用模拟电路仿真器SPICE模型中对应的参数,完成并行高速链路系统的通用模拟电路仿真器SPICE模型的建立; ⑶获得边沿响应信号: (3a)将基准的上升边信号00000001111加载到通用模拟电路仿真器SPICE模型中进行仿真,得到基准上升边响应信号; (3b)将基准的下降边信号11111110000加载到通用模拟电路仿真器SPICE模型中进行仿真,得到基准下降边响应信号; (3c)将有前导位0101010的上升边信号01010101111和零信号01010100000加载到通用模拟电路仿真器SPICE模型中进行仿真,将这两个信号的仿真结果相减,得到受前导位影响上升边响应信号; (3d)将有前导位0101010 A rapid time-domain simulation system for high speed parallel links, the following steps: (1) selection of a high-speed parallel link system; ⑵ SPICE model established: a high-speed parallel link system in line width, line spacing, medium thickness, dielectric constant, loss factor, and the transmission line thickness parameter values, the parameter assigned to generic analog simulator SPICE circuit models corresponding to complete SPICE simulators model generic analog circuit system in parallel to establish high-speed links; ⑶ edge response signal obtained : (3a) the rising edge signal reference 00000001111 loaded into the simulator SPICE model generic analog circuit simulation, to obtain the reference rising edge response signal; (3B) to a reference falling edge signal 11111110000 loaded into a general analog circuit simulator SPICE model in the simulation, to obtain the reference signal in response to a falling edge; (. 3C) will have a rising edge of the signal for the preamble bit 0101010 01010101111 01010100000 zero signal and loaded into a general analog circuit simulator SPICE model simulation, the simulation result of these two-phase signals Save give rise influence by the leading edge position signal in response; (3D) will have a leading position 0101010 的零信号01010100000加载到通用模拟电路仿真器SPICE模型中进行仿真,得到受前导位影响下降边响应信号; ⑷计算仿真阶数: 按照下式,计算仿真并行高速链路系统中最坏眼图的阶数; TN =- t 其中:N表示仿真并行高速链路系统中最坏眼图的阶数,T表示基准上升边响应信号和受前导位影响上升边响应信号相减的差值大于〇. 1 %的持续时间,t表示基准上升边响应信号的上升边的上升时间; ⑶获得上升边和下降边向量: (5a)将受前导位影响上升边响应信号值与逻辑0响应信号值之差超过0.001的第一个点,设定为受前导位影响上升边响应信号的采样起点; (5b)将有前导位0101010的上升边信号01010101111,加载到通用模拟电路仿真器SPICE模型中,对模型中任意一根进攻线进行仿真,获得仅有码间串扰的受前导位影响上升边响应信号; (5c)对仅有码间串扰的受前导位影 01010100000 zero signal loaded into the simulator SPICE model generic analog circuit simulation, to obtain the dropping impact by the leading edge of a response signal bits; ⑷ simulation calculation order: according to the following formula to calculate a high-speed parallel link system simulation worst eye of order; TN = - t where: N represents the order of the simulation of parallel high-speed links worst eye system, T represents the reference signal in response to the rising edge and the influence by the leading bit of the subtraction signal in response to the rising edge of the difference is greater than square. 1% of the time duration, t represents the reference leading edge in response to the rise time of the rising signal edges; ⑶ obtaining rising and falling edge vectors: (5a) will be subject to the preamble bits affect the rising edge of the response signal value and a logic 0 in response to a difference signal value the first point of more than 0.001, the leading bit is set by the rising edge of the influence signal in response to the sampling start point; (5B) will rise from the leading edge of the signal 01010101111 0101010, is loaded into the general-purpose analog circuit simulator SPICE models, the model any of a simulation offensive line, only inter symbol interference is obtained side by the leading bit of response signal increased impact; (5C) of the inter-symbol interference by only the leading bit Movies 上升边响应信号,从采样起点处以上升边信号01010101111的一个位宽为间隔进行采样,采样15次,每次采样50个点,获得15组仅有码间串扰的受前导位影响上升边响应信号向量; (5d)将对进攻线进行仿真时受害线上感应出的串扰噪声,与仅有码间串扰的受前导位影响上升边响应信号相加,获得有串扰噪声时的受前导位影响上升边响应信号; (5e)对有串扰噪声时的受前导位影响上升边响应信号,从采样起点处以上升边信号01010101111的一个位宽为间隔进行采样,采样15次,每次采样50个点,获得15组有串扰噪声时的受前导位影响上升边响应信号向量; (5f)将受前导位影响下降边响应信号值,与逻辑1响应信号值之差超过0.001的第一个点,设定为受前导位影响下降边响应信号的采样起点; (5g)将有前导位0101010的下降边信号01010100000,加载到通用模拟电路仿真器SPICE模型 A response signal rising edge, starting from the sampling bit width of a rising edge of the signal imposed 01010101111 sampling interval, sample 15 times, 50 points per sample to obtain a set of 15 preamble bits increased by the influence of inter-symbol interference only in response to a signal edge vector; (5D) will attack victim line line induced crosstalk noise simulation, only inter-symbol interference by adding the side signal in response to the impact of rising leading bit, that bit preamble when affected by crosstalk noise rise edge response signal; (5E) Effect of preamble bits when receiving the crosstalk noise signal in response to rising edge, starting from the sampling signal a rising edge of the bit width impose 01010101111 sampling interval, sample 15 times, 50 points per sample, obtained when the preamble bits are affected by the crosstalk noise signal 15 in response to the rising edge vector group; (5F) by the leading one in response to the first falling edge of the impact point of the difference signal value in response to a signal value, the logic more than 0.001 is set Effect of bits by leading a falling edge of the signal in response to the sampling start point; (5g) will have a leading edge of the signal level drops 01010100000 0101010, and loaded onto a general analog circuit simulator SPICE model 中,对模型中任意一根进攻线进行仿真,获得仅有码间串扰的受前导位影响下降边响应信号; (5h)对仅有码间串扰的受前导位影响下降边响应信号,从采样起点处以下降边信号01010100000的一个位宽为间隔开始采样,采样15次,每次采样50个点,获得15组仅有码间串扰的受前导位影响下降边响应信号向量; (5i)将对进攻线进行仿真时受害线上感应出的串扰噪声,与仅有码间串扰的受前导位影响下降边响应信号相加,获得有串扰噪声时的受前导位影响下降边响应信号; (5 j)对有串扰噪声时的受前导位影响下降边响应信号,从采样起点处以下降边信号01010100000的一个位宽为间隔开始采样,采样15次,每次采样50个点,获得15组有串扰噪声时的受前导位影响下降边响应信号向量; (6)获得最坏码型序列向量: 采用格子法,对有串扰噪声时的受前导位影响上升边和下 In any one of the model simulation offensive line, only inter symbol interference is obtained side by the leading bit of response signal drop impact; (5H) to decrease the influence by the leading bit of the inter-symbol interference edge only a response signal from the sample starting impose a falling edge of a signal bit width of the interval 01010100000 begin sampling, the sampling times 15, 50 points per sample to obtain a response to a falling edge between the group 15 only by the preamble symbol interference affecting the signal bit vector; will (5i) victim line induced crosstalk noise simulation offensive line, inter-symbol interference is decreased by only the leading edge of the response signal bit affects together to get affected by the leading bit of the crosstalk noise signal in response to a falling edge; (5 j ) Effect of leading bits when receiving the crosstalk noise signal in response to a falling edge, starting from the sampling signal a falling edge of the bit width impose 01010100000 to begin sampling interval, sample 15 times, 50 points per sample to obtain a crosstalk noise 15 group when the leading bit affected by the falling edge of the response signal vector; (6) obtaining a worst pattern vector sequence: the grid method, when the leading bit of crosstalk noise impact on the rising edge and the receiving 降边响应信号向量进行计算,得到最坏累计电压和引起最坏眼图的最坏码型序列向量; 所述格子法的具体步骤如下: 第一步,将仅有码间串扰的受前导位影响上升边响应信号向量的第一组值与1相减,得到使用格子法计算所需的上升边向量; 第二步,将仅有码间串扰的受前导位影响下降边响应信号向量的第一组值与1相减,得到使用格子法计算所需的下降边向量; 第三步,用A1;i,i = 1,2,......,51表示码间串扰对高电平的累积影响电压,其中,i表示码间串扰对高电平的累积影响电压的向量组数;用81;1,1 = 1,2,......,51表示码间串扰对低电平的累积影响电压,其中,i表示码间串扰对低电平的累积影响电压的向量组数;设高电平累积影响电压A1;1 = 0,低电平累积影响电压B1;1 = 0;用MH(l,i),i = l,2,......,51 表示引起高电平累积电压的向量,用ML(l,i),i = l,2 Falling edge Response signal vector has been calculated, the cumulative voltage and cause the worst worst worst eye pattern vector sequence; specific steps of the grid method is as follows: first, the inter-symbol interference by only the leading bit Effect of the rising edge of a first set of values ​​in response to the signal vector is subtracted from 1, to give the desired rising edge vector calculation method using a lattice; a second step, the leading bit is only affected by inter-symbol interference in response to a falling edge of the signal vector a set of values ​​and a subtracting calculation of the required falling edge of the grid method using the vector obtained; the third step, A1; i, i = 1,2, ......, 51 represents inter-symbol interference of high power cumulative effects of voltage levels, where, i denotes the number of ISI on the cumulative effects of high-level voltage vectors; with 81; 1,1 = 1,2, ......, 51 represents the ISI on cumulative effects of low level voltage, wherein, i denotes the number of vectors on the low-level voltage cumulative effects of ISI; cumulative effects provided high voltage A1; 1 = 0, the cumulative effects of low-level voltage B1; 1 = 0; with the MH (l, i), i = l, 2, ......, 51 represents the cumulative voltage vector due to the high level, with the ML (l, i), i = l, 2 ,......,51表示引起低电平L累积电压的向量; 第四步,用1?014,心4+1)=〇表示上升边向量中从第1个高电平的累积影响电压4 14转变到第1 + 1个高电平的累积影响电压414+1的累加值为0;用? , ......, L 51 represents cumulative voltage vector due to the low level;? A fourth step, by 1014, the heart 4 + 1) = square cumulative vector indicates rising edge from a high level Effect voltage 414 transitions to the cumulative effects of voltage of high level 1 + 1 + 1 the accumulated value is 0414; use? 出14,8 14+1)=0表示下降边向量中从第i个低电平的累积影响电压B1;1转变到第i+1个低电平的累积影响电压B 1>1+1的累加值为0;用? A 14,8 14 + 1) = 0 represents the voltage drop from the i-th low B1 cumulative effects of edge vectors; transition to an i + 1-th cumulative effects of low level voltage B 1> 1 + 1 of cumulative value of 0; use? 01,1,81, 1+1)=?(1,1)表示下降边向量中从第1个高电平的累积影响电压六1转变到第i+1个低电平的累积影响电压B i+1的累加值为F (1,i);用R (B1;i,A1>i+1) =R (1,i)表示上升边向量中从第i个低电平的累积影响电压仏转变到第i+1个高电平的累积影响电压A1+1的累加值为R (1,i); 第五步,从有串扰噪声时的受前导位影响上升边和下降边响应信号向量第0个到第50 个值中依次的查找信号向量的负值,记录负值的位置i;当高电平累积电压向量MH(l,i+l) 的第i+1个值为1时,第i个高电平累积电压A 1;1转变到第i+1个高电平累积电压A1>1+1的累加值为R (Ai,Ai+1);当高电平累积电压的向量Mh (1,i+1)的第i+1个值为0时,第i个高电平累积电压A1;i转变到第i+1个高电平累积电压A 1>i+1的累加值为F(Ai,Bi+1);当查找出信号向量的所有负值时,得到由第一组有串扰噪声时的受前导位影响上升边响应信号 01,1,81, 1 + 1) =? (1,1) indicates a falling edge transition from the vector cumulative effects of a high voltage six 1 to i + 1-one low-level voltage B cumulative effects the accumulated value F (1, i) i + 1 of the; (; i, A1> i + 1 B1) = R (1, i) represents the cumulative affect the voltage rising edge of the i-th vector from a low level by R Fo i + 1 transitions to the first plurality of high levels of the cumulative effects of the accumulated value of the voltage A1 + R (1, i) 1; a fifth step, when the leading bit of impact from crosstalk noise by rising and falling edge of the response signal vector of 0 to find values ​​of 50 successive negative signal vector, the negative recording position I; when the cumulative high voltage vector MH (l, i + l) first with value 1 i + 1 when the i-th high cumulative voltage a 1; 1 transitions to the high level i + 1-th cumulative voltage A1> 1 + 1 is the accumulated value of R (Ai, Ai + 1); high level when the accumulated voltage vector Mh (1, i + 1) when the i + 1 is 0, the i-th high cumulative voltage A1; transition i to i + 1-th high cumulative voltage a 1> i + 1 the accumulated value F (Ai, Bi + 1); find out when all the negative signal vector, obtained from the rise time of the preamble bits are affected by the crosstalk noise signal in response to a first set of edges 量引起的总的高电平累积电压Ai,51; 第六步,重复第五步,直到得出所有有串扰噪声时的受前导位影响上升边响应信号向量引起的总的高电平累积电压; 第七步,比较得出的所有总的高电平累积电压,得出最坏的累积电压; 第八步,从仅有码间串扰的受前导位影响上升边响应信号向量的第0个到第50个值中依次的查找信号向量的正值,记录正值的位置i;当低电平累积电压向量Ml (l,i+l)的第i+1 个值为〇时,第i个低电平累积电压B1;1转变到第i + 1个低电平累积电压B1>1+1的累加值为F (BuBm);当低电平累积电压的向量ML(l,i + l)的第i + 1个值为1时,第i个低电平累积电压B1;i转变到第i+1个低电平累积电压B1>i+1的累加值为R(Bi,Ai+1);当查找出信号向量的所有正值时,得到由第一组仅有码间串扰的受前导位影响上升边响应信号向量引起的总的低电平累积电压Bl,51; 第九步 The total amount of high level due to the cumulative voltage Ai, 51; a sixth step, the fifth step is repeated until all the results when the preamble bits are affected by the crosstalk noise caused by the rising edge of the response signal vector cumulative total high voltage ; seventh step, the cumulative total of all the high-level voltage comparison results, obtained worst cumulative voltage; eighth step, only inter symbol interference from the edges by the leading bit in response to the impact of rising signal vector 0th 50 to the second lookup values ​​sequentially signal vector values, recording the position value of i; low level when the cumulative voltage vector Ml (l, i + l) i + 1 of the first square with value, the i a low accumulation voltage B1; 1 transitions to the low level i + 1-th cumulative voltage B1> integrated value of F (BuBm) 1 + 1; and when a low accumulation voltage vector ML (l, i + l ) the i + 1-th value of 1, the i-th low-level cumulative voltage Bl; transition i to i + 1-th low cumulative voltage B1> i + accumulated value of R 1 (Bi, Ai + 1); Find all the positive values ​​when the signal vector obtained by the rise of the leading bit of the influence of crosstalk between the first set of side code only in response to the cumulative total of the low level voltage caused by the signal vector Bl, 51; ninth step 重复第八步直到得出所有仅有码间串扰的受前导位影响上升边响应信号向量引起的总的低电平累积电压; 第十步,比较得出的所有总的低电平累积电压,得出最坏的累积电压; ⑵获得预估的最坏眼图: 将获得的最坏码型序列向量加载到通用模拟电路仿真器SPICE模型中进行仿真,将仿真结果加载到通用模拟电路仿真器SPICE波形查看器中,查看最坏眼图,记录最坏眼高和眼宽; ⑶仿真并行高速链路系统的最坏眼图: 用通用模拟电路仿真器SPICE生成上升边和下降边不对称的输入信号,将输入信号加载到步骤⑵中的并行高速链路系统的通用模拟电路仿真器SPICE模型中进行仿真,将仿真结果加载到通用模拟电路仿真器SPICE波形查看器中,查看最坏眼图,记录最坏眼高和眼宽; (9)获得预估精度的绝对误差: (9a)将步骤⑶中的最坏眼高与步骤(7)中预估的最坏眼高 The eighth step is repeated until all the stars inter-symbol interference only by the leading edge position in response to increase in the influence of the total low level due to cumulative voltage signal vector; tenth step, the cumulative total of all the low-level voltage comparison derived, the worst results of cumulative voltage; ⑵ obtained estimated worst eye: the worst pattern sequences obtained vector is loaded into the general-purpose analog circuit simulator SPICE model simulation, the simulation result is loaded into the general-purpose analog circuit simulator SPICE waveform viewer, the worst eye view, high recording worst eye height and width; simulated parallel ⑶ worst eye speed link system: generating generic analog SPICE circuit simulator rising and falling edges of the asymmetric input signal, the input signal is loaded into a general analog circuit simulator SPICE models speed parallel link system in step ⑵ for simulation, the simulation result is loaded into the general-purpose analog circuit simulator SPICE waveform viewer, the worst eye view , high recording worst eye height and width; (9) the accuracy of the estimated absolute errors obtained: (9a) in step ⑶ worst eye height of step (7) of the estimated worst eye height 代入下式,计算预估最坏眼高的绝对误差; Into the following equation to calculate estimated absolute error high worst eye;
    Figure CN104143024BC00041
    其中:nH表示预估最坏眼高H的绝对误差,Hbtds表示用最优时域方法BTDS预估的最坏眼高H,HSPICE表示用通用模拟电路仿真器SPICE仿真的最坏眼高H; (9b)将步骤⑶中的最坏眼宽与步骤(7)中预估的最坏眼宽代入下式,计算眼宽的绝对误差; Wherein: nH denotes the absolute error estimate of the worst eye height H, Hbtds represented by a time domain method BTDS optimal estimate of the worst eye height H, HSPICE worst eye height H represents a general-purpose analog circuit simulator SPICE simulation; (9b) the worst eye width of step (7) in the step ⑶ estimated worst eye width into the following equation to calculate the absolute error of the eye width;
    Figure CN104143024BC00042
    其中:_表示预估最坏眼宽W的绝对误差,WBTDS表示用最优时域方法BTDS预估的最坏眼宽W,WSPke表示用通用模拟电路仿真器SPICE仿真的最坏眼宽W; (9c)将输入信号位宽减去最坏眼宽得到峰峰值抖动,将峰峰值抖动代入下式,计算峰峰值抖动绝对误差; Wherein: _ represents a worst case estimate of the absolute error of the eye width W, WBTDS represented by the best estimate of the time domain method BTDS worst eye width W, WSPke represented by general analog circuit simulator SPICE simulation of the worst eye width W; (9c) bit width of the input signal obtained by subtracting the worst eye width jitter peak, the peak to peak jitter into the following equation to calculate the peak to peak jitter absolute error;
    Figure CN104143024BC00051
    其中:nj表不预估峰峰值抖动J的绝对误差,Jbtds表不用最优时域方法BTDS预估的峰峰值抖动J,Jspke表示用通用模拟电路仿真器SPICE仿真的峰峰值抖动J。 Wherein: nj table does not peak jitter J estimated absolute error, Jbtds table not optimal time-domain method BTDS estimated peak jitter J, Jspke represents a peak to peak jitter general analog circuit simulator SPICE simulation J.
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