CN107942794B - Method for simulating McBSP interface by using GPIO interface - Google Patents

Abstract

The invention discloses a method for simulating an McBSP interface by using a GPIO interface, which comprises the following steps: step a: selecting 5 GPIO interfaces in the DSP to simulate an McBSP interface, 1 simulation clock signal CLK, 1 simulation sending frame synchronizing signal FSX, 1 simulation receiving frame synchronizing signal FSR, 1 simulation receiving serial data signal DR and 1 simulation sending serial data signal DX; step b: setting a clock signal, a fixed period value, the number of bits of the length of a transmitted and received data word, a mark of a transmitted and received frame synchronization signal and a clock mark bit according to the design requirement of the transmitter; step c: in the timer interrupt handler of the DSP, two branches for transmitting and receiving data are set. The invention reduces time complexity and increases the number of McBSP interfaces of the DSP chip.

Description

Method for simulating McBSP interface by using GPIO interface

Technical Field

The invention relates to an interface of an embedded system, in particular to a method for simulating an McBSP interface by using a GPIO interface.

Background

A General Purpose Input/Output (GPIO) port is applied to an embedded system more often, and a user can transmit signals by controlling the GPIO port to Output high and low levels through programming, such as a user-defined synchronization timestamp, to ensure time synchronization of each board.

The high-speed Multi-channel Buffered Serial Ports (McBSP) are multifunctional Serial communication interfaces developed by TI special for DSP chips, have powerful functions, are compatible with various common Serial communication modes, can be interfaced with an industrial standard coder/decoder, an analog interface chip, other Serial analog-to-digital converters and other digital-to-analog converters to realize full-duplex Serial communication, and have a double-buffer data register structure which allows continuous data stream transmission.

The DSP chip usually has only two McBSP interfaces, and when complex programs are processed, the two interfaces are not enough to be used. And because the related pins and registers of the McBSP interface are numerous, the software configuration is more complex, and great troubles are brought to engineers who utilize the McBSP to research and develop.

Disclosure of Invention

In order to solve the technical problems, the invention provides a method for simulating an McBSP interface by using a GPIO interface.

The technical scheme adopted by the invention is as follows:

a method for simulating an McBSP interface by using a GPIO interface comprises the following steps:

step a, selecting 5 GPIO interfaces to simulate an McBSP interface, 1 GPIO interface to simulate a clock signal CLK, 1 GPIO interface to simulate a sending frame synchronization signal FSX, 1 GPIO interface to simulate a receiving frame synchronization signal FSR, 1 GPIO interface to simulate a receiving serial data signal DR, and 1 GPIO interface to simulate a sending serial data signal DX in a DSP chip;

b, setting a fixed period value PRD according to the required clock signal CLK, wherein the PRD is equal to the reciprocal of the CLK; setting the value of a transmission variable FSXCNT as the number of bits of the transmitted data word length according to the number of bits of the data word length required to be transmitted; setting the value of the receive variable FSRCNT to the number of bits of the received data word length in accordance with the number of bits of the data word length to be received; setting a receiving frame synchronization signal mark FSRFLAG according to an effective frame period needing to be received; utilizing a DSP software timer to generate a timer interrupt with the duration of PRD/2, and setting a clock FLAG bit CLK _ FLAG;

and c, setting two branches of sending and receiving data in the interrupt processing program of the timer of the DSP chip.

The step c comprises the following steps:

step c1, the data transmission branches as follows, the DSP chip judges that the clock FLAG bit CLK _ FLAG is 0, the clock FLAG bit CLK _ FLAG is changed into 1, and the GPIO interface for outputting the analog clock signal CLK is set to be low level; then after the DSP chip judges that the transmission variable FSXFLAG is 1, setting the transmission variable FSXFLAG to be 0, setting the GPIO interface for outputting the analog frame synchronizing signal FSX to be a high level, and after two timing periods, setting the GPIO interface for outputting the analog frame synchronizing signal FSX to be a low level; then the DSP chip circularly judges whether the sending variable FSXCNT is more than 0, if so, each timing period sends a data bit through the GPIO interface of the analog serial data signal DX, and the counting of the sending variable FSXCNT is decreased; if the data bit is equal to 0, the data bit is sent completely; then step c1 is repeatedly executed;

step c2, the data receiving branch is as follows, the DSP chip judges the clock FLAG bit CLK _ FLAG is 1, then the clock FLAG bit CLK _ FLAG is changed into 0, and the GPIO interface for outputting the analog clock signal CLK is set to be high level; then after the DSP chip judges that the frame synchronization signal mark FSRFLAG is 1, setting the frame synchronization signal mark FSRFLAG to be 0, setting the GPIO interface for outputting the analog frame synchronization signal FSR to be high level, and after two timing periods, setting the GPIO interface for outputting the analog frame synchronization signal FSR to be low level; then the DSP chip circularly judges whether the receiving variable FSRCNT is larger than 0, if so, a data bit is collected through a GPIO interface of the analog serial data signal DR in every two timing periods, and the counting of the receiving variable FSRCNT is decreased; if equal to 0, it indicates that all data bits have been received; step c2 is then repeatedly performed.

Compared with the prior art, the invention has the following beneficial effects:

increasing the number of McBSP interfaces for the DSP chip;

and (II) a plurality of registers of the McBSP do not need to be configured, so that the complexity is reduced, and the time is saved.

Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

Fig. 1 is a flowchart illustrating an emulation of an McBSP interface using a GPIO interface according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an interface connection between an FPGA and a DSP according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the interface connection between the DSP and the FPGA according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a data transmission according to an embodiment of the present invention;

FIG. 5 is a timing diagram of receiving according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

A method for simulating an McBSP interface by using a GPIO interface comprises the following steps:

step a, selecting 5 GPIO interfaces to simulate an McBSP interface, 1 GPIO interface to simulate a clock signal CLK, 1 GPIO interface to simulate a sending frame synchronization signal FSX, 1 GPIO interface to simulate a receiving frame synchronization signal FSR, 1 GPIO interface to simulate a receiving serial data signal DR, and 1 GPIO interface to simulate a sending serial data signal DX in a DSP chip;

step b, setting a fixed period value PRD according to the size of a required clock signal CLK (the value range does not exceed the maximum clock which can be provided by the DSP chip), wherein the PRD is equal to the reciprocal of the CLK; setting the value of a transmission variable FSXCNT (having a value range of 8, 12, 16, 20, 24 or 32 bits) as the number of bits of the transmitted data word length according to the number of bits of the data word length to be transmitted; setting the value of a receive variable FSRCNT (having a value range of 8, 12, 16, 20, 24 or 32 bits) to the number of bits of the received data word length in accordance with the number of bits of the data word length to be received; setting a receiving frame synchronization signal mark FSRFLAG (value range is 0 or 1) according to an effective frame period needing to be received; utilizing a DSP software timer to generate a timer interrupt with the duration of PRD/2, and setting a clock FLAG bit CLK _ FLAG (the value range is 0 or 1);

and c, setting two branches of sending and receiving data in the interrupt processing program of the timer of the DSP chip.

The step c comprises the following steps:

step c1, the data transmission branches as follows, the DSP chip judges that the clock FLAG bit CLK _ FLAG is 0, the clock FLAG bit CLK _ FLAG is changed into 1, and the GPIO interface for outputting the analog clock signal CLK is set to be low level; then after the DSP chip judges that the transmission variable FSXFLAG is 1, setting the transmission variable FSXFLAG to be 0, setting the GPIO interface for outputting the analog frame synchronizing signal FSX to be a high level, and after two timing periods, setting the GPIO interface for outputting the analog frame synchronizing signal FSX to be a low level; then the DSP chip circularly judges whether the sending variable FSXCNT is more than 0, if so, each timing period sends a data bit through the GPIO interface of the analog serial data signal DX, and the counting of the sending variable FSXCNT is decreased; if the data bit is equal to 0, the data bit is sent completely; then step c1 is repeatedly executed;

step c2, the data receiving branch is as follows, the DSP chip judges the clock FLAG bit CLK _ FLAG is 1, then the clock FLAG bit CLK _ FLAG is changed into 0, and the GPIO interface for outputting the analog clock signal CLK is set to be high level; then after the DSP chip judges that the frame synchronization signal mark FSRFLAG is 1, setting the frame synchronization signal mark FSRFLAG to be 0, setting the GPIO interface for outputting the analog frame synchronization signal FSR to be high level, and after two timing periods, setting the GPIO interface for outputting the analog frame synchronization signal FSR to be low level; then the DSP chip circularly judges whether the receiving variable FSRCNT is larger than 0, if so, a data bit is collected through a GPIO interface of the analog serial data signal DR in every two timing periods, and the counting of the receiving variable FSRCNT is decreased; if equal to 0, it indicates that all data bits have been received; step c2 is then repeatedly performed.

As shown in fig. 1, a flowchart for simulating an McBSP interface by using a GPIO interface shows three steps of the present invention, which are GPIO selection, parameter setting, and data transmission.

In one embodiment of the invention, the DSP chip adopts TMS320DM642, the FPGA chip which communicates with the DSP adopts XQVR600-4C228V, and the communication between the two is an McBSP interface which is simulated through a GPIO interface. An interface connection schematic diagram of the FPGA and the DSP is shown in fig. 2, an interface connection schematic diagram of the DSP and the FPGA is shown in fig. 3, the FPGA is respectively connected with five pins GPIO10, GPIO11, GPIO12, GPIO13 and GPIO14 of the DSP through five IO pins of TTL, wherein the GPIO10 simulates a clock signal CLK, the GPIO14 simulates sending of a frame synchronization signal FSX, the GPIO12 simulates receiving of a frame synchronization signal FSR, the GPIO11 simulates receiving of a serial data signal DR, the GPIO13 simulates sending of a serial data signal DX, and the five GPIO interfaces of the DSP simulate an McBSP interface.

The following parameters are set in the DSP software: CLK is 100Hz, PRD is 10ms, FSXCNT is 16, FSRCNT is 24, FSXFLAG is 1, FSRFLAG is 1, CLK _ FLAG is 0.

According to the step c, two branches of sending and receiving data are programmed in the interrupt processing function of the DSP software timer, and the data transmission function of the McBSP interface can be realized. The data transmission sequence is shown in fig. 4, and in each frame period, the DSP can transmit 16 bits of data; the receiving sequence is shown in fig. 5, and in each frame period, the DSP can receive 24 bits of data; therefore, the data receiving and transmitting function of the simulation McBSP interface is completed.

The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims (2)

1. A method for simulating an McBSP interface by using a GPIO interface is characterized by comprising the following steps:

step a, selecting 5 GPIO interfaces to simulate an McBSP interface in a DSP chip, wherein 1 GPIO interface simulates a clock signal CLK, 1 GPIO interface simulates a sending frame synchronization signal FSX, 1 GPIO interface simulates a receiving frame synchronization signal FSR, 1 GPIO interface simulates a receiving serial data signal DR, and 1 GPIO interface simulates a sending serial data signal DX;

b, setting a fixed period value PRD according to the required clock signal CLK, wherein the PRD is equal to the reciprocal of the CLK; setting the value of a transmission variable FSXCNT as the number of bits of the transmitted data word length according to the number of bits of the data word length required to be transmitted; setting the value of the receive variable FSRCNT to the number of bits of the received data word length in accordance with the number of bits of the data word length to be received; setting a receiving frame synchronization signal mark FSRFLAG according to an effective frame period needing to be received; utilizing a DSP software timer to generate a timer interrupt with the duration of PRD/2, and setting a clock FLAG bit CLK _ FLAG;

and c, setting two branches of sending and receiving data in the interrupt processing program of the timer of the DSP chip.

2. The method for simulating the McBSP interface by using the GPIO interface as claimed in claim 1, wherein the step c comprises the steps of:

step c1, the data transmission branches as follows, the DSP chip judges that the clock FLAG bit CLK _ FLAG is 0, the clock FLAG bit CLK _ FLAG is changed into 1, and the GPIO interface for outputting the analog clock signal CLK is set to be low level; then after the DSP chip judges that the transmission variable FSXFLAG is 1, setting the transmission variable FSXFLAG to be 0, setting the GPIO interface for outputting the analog frame synchronizing signal FSX to be a high level, and after two timing periods, setting the GPIO interface for outputting the analog frame synchronizing signal FSX to be a low level; then the DSP chip circularly judges whether the sending variable FSXCNT is more than 0, if so, each timing period sends a data bit through the GPIO interface of the analog serial data signal DX, and the counting of the sending variable FSXCNT is decreased; if the data bit is equal to 0, the data bit is sent completely; then step c1 is repeatedly executed;

step c2, the data receiving branch is as follows, the DSP chip judges the clock FLAG bit CLK _ FLAG is 1, then the clock FLAG bit CLK _ FLAG is changed into 0, and the GPIO interface for outputting the analog clock signal CLK is set to be high level; then after the DSP chip judges that the frame synchronization signal mark FSRFLAG is 1, setting the frame synchronization signal mark FSRFLAG to be 0, setting the GPIO interface for outputting the analog frame synchronization signal FSR to be high level, and after two timing periods, setting the GPIO interface for outputting the analog frame synchronization signal FSR to be low level; then the DSP chip circularly judges whether the receiving variable FSRCNT is larger than 0, if so, a data bit is collected through a GPIO interface of the analog serial data signal DR in every two timing periods, and the counting of the receiving variable FSRCNT is decreased; if equal to 0, it indicates that all data bits have been received; step c2 is then repeatedly performed.

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