CN107942120B - Current detection circuit and current detection method - Google Patents
Current detection circuit and current detection method Download PDFInfo
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- CN107942120B CN107942120B CN201710966742.3A CN201710966742A CN107942120B CN 107942120 B CN107942120 B CN 107942120B CN 201710966742 A CN201710966742 A CN 201710966742A CN 107942120 B CN107942120 B CN 107942120B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides a current detection circuit and a current detection method, which are used for solving the problem that nondestructive detection, smaller PCB area and adjustable peak current cannot be achieved in the prior art. Wherein the current detection circuit includes: the input circuit comprises two MOS tubes, namely a first MOS tube and a second MOS tube, wherein the first MOS tube multiplexes a power switch tube in a switch power supply, the two MOS tubes are composed of a plurality of unit MOS tubes with the same type and the same size, and the unit MOS tubes form different internal resistance values according to set current attenuation multiples in a parallel connection and series connection mode, and are respectively a first MOS tube with a smaller internal resistance value and a second MOS tube with a larger internal resistance value; the two MOS tubes are respectively connected to the two input ends of the differential current detection amplifier, and the internal resistances of the two MOS tubes are used as sampling resistors.
Description
Technical Field
The invention relates to a current detection circuit in a switching power supply, in particular to a current detection circuit and a current detection method based on an implementation scheme in a control chip of the switching power supply.
Background
The existing current detection of the switching power supply is divided into off-chip implementation and on-chip implementation. The off-chip implementation means that the control chip is externally connected with a discrete power switch tube, firstly, a discrete resistor is connected in series with the source electrode of the power switch tube, the switch current is converted into voltage on the resistor and transmitted back to the chip, the mode is limited by the loss of the sampling resistor, the improvement of the power efficiency is not facilitated, the peak voltage cannot be selected to be too high, the signal-to-noise ratio of the detection voltage is low, the reliability is easily reduced due to external interference, and the detection resistor is easily burnt out and loses efficacy due to the fact that the detection resistor is subjected to larger power consumption; secondly, the current transformer is connected in series with the drain end of the power tube, so that the current obtained by attenuating the inductance current in a fixed proportion is dropped on a fixed resistor, and a detection voltage is generated and transmitted back to the control chip.
The on-chip implementation means that a power switch tube M20 is integrated in a control chip U1, a detection resistor is designed between a source electrode of the power switch tube M20 and the ground to detect a switching current, and two general methods exist at present, one is that a metal resistor Rm (as shown in fig. 1A) is used as a detection resistor, as shown in fig. 1A, the control chip U1 comprises a detection circuit 10 and a control circuit 20 of the switch tube, the detection circuit 10 samples the current of the metal resistor Rm connected in series with the source electrode of the power switch tube M20, and the switching current is converted into a voltage VCS on the resistor Rm and transmitted back to the control chip U1. Secondly, the internal resistance of the power switch tube M20 (as shown in fig. 1B) is used for detecting resistance when the power switch tube M is turned on, as shown in fig. 1B, the control chip U2 comprises a detection circuit 10 and a control circuit 20 of the switch tube, the detection circuit 10 samples the current of the internal resistance of the power switch tube M20, and the switching current is converted into a voltage VCS on the resistance and is transmitted back to the control chip U2. Therefore, the metal resistor and the internal resistance of the power switch tube working in the linear region can be small, so that the power switch tube has almost no power consumption loss, is high in efficiency, is designed in a chip, isolates the interference of the outside on detection waveforms, saves the areas of package pins and a PCB panel, and still has the defect of large error. In the control chip of the current mainstream switching power supplies such as BUCK, ACDC and the like, a general non-destructive current detection circuit principle is shown in fig. 2, and the current detection transimpedance gain of the mode is as follows:
Design time R 1 、R 2 And R is 4 The resistance is larger, and the high square resistance resistor with the same process type can be adopted for drift cancellation; therefore, the detection voltage Vcs is affected by the process drift of the small detection resistor Rs, i.e. the layout matching degree of the power switch tube or the metal resistorThe maximum value of the peak current is easy to deviate from the design value, the error of the detected current is caused, and the maximum peak current is not controllable outside the control chip.
Disclosure of Invention
In view of this, the present invention provides a current detection circuit and a current detection method, so as to solve the problem that the nondestructive detection, the smaller PCB area and the peak current are not compatible in the prior art, and the internal resistance of the power tube is utilized to receive the input current, and meanwhile, the current detection precision is not limited by the process drift of the detection resistor.
In one aspect of the present invention, there is provided a current detection circuit for detecting a switching current flowing through a switching power supply, the current detection circuit comprising: the input circuit comprises two MOS tubes, namely a first MOS tube and a second MOS tube, wherein the first MOS tube multiplexes a power switch tube in a switch power supply, the two MOS tubes are composed of a plurality of unit MOS tubes with the same type and the same size, and the unit MOS tubes form different internal resistance values according to set current attenuation multiples in a parallel connection and series connection mode, and are respectively a first MOS tube with a smaller internal resistance value and a second MOS tube with a larger internal resistance value; the two MOS tubes are respectively connected to two input ends of the differential current detection amplifier, and the internal resistances of the two MOS tubes are used as sampling resistors; when the two MOS tubes work in a linear conduction state, the detected current signal is received based on the conduction resistance of the first MOS tube, and a first current signal reflecting actual current is generated; the voltage on the two MOS tubes is equal through the differential current detection amplifier, so that an attenuation current signal is generated through the second MOS tube according to the current attenuation multiple, and then the attenuation current signal is mirrored through the differential current detection amplifier and output to the output signal end to serve as a detection current signal to be provided to the detection resistor (Rcs), and a current detection voltage drop signal is generated at the current detection end (CS).
Preferably, the internal resistance value of the first MOS tube is the parallel value of N unit MOS tubes, and the internal resistance value of the second MOS tube is the serial value of M unit MOS tubes; the current attenuation multiple of the input circuit is M times N times.
Preferably, the substrates of the M serial unit MOS tubes of the second MOS tube are connected with respective source end potentials.
Preferably, the gates of the first MOS tube and the second MOS tube of the input circuit are connected to the same driving signal, the sources of the first MOS tube and the second MOS tube are grounded, the drain electrode of the first MOS tube is connected to the input signal end, and the drain electrode of the first MOS tube is led out to serve as a first output end of the input circuit; the drain electrode of the second MOS tube is led out to serve as a second output end of the input circuit.
Preferably, the differential current detection amplifier comprises a differential operational amplifier unit, an error cancellation branch, a regulation branch and an output branch which are sequentially connected, and a first input end connected with a first output end of the input circuit and a second input end connected with a second output end of the input circuit.
The differential operational amplifier unit comprises a first branch, a second branch, a third branch and a fourth branch, and a first transistor and a third transistor pair, a second transistor and a fourth transistor pair which form a differential input transistor pair; the first branch is a constant current circuit comprising a first constant current source generated by an internal reference and is connected with a first output end of the input circuit through a first transistor; the second branch is a current branch in mirror image relation with the fourth branch and is connected with a second output end of the input circuit through a second transistor; the third branch is a current branch obtained by mirroring the first constant current source and is connected with a first output end of the input circuit through a third transistor; the fourth branch is a current branch in mirror image relation with the second branch, and the mirror image is equal to the current of the third branch after being added with the error counteracting branch, and is connected with the second output end of the input circuit through a fourth transistor; the error cancellation branch is a constant current circuit comprising a second constant current source which is slightly smaller than the first constant current source and is generated by an internal reference, and is used for canceling attenuation multiple calculation deviation introduced by bias current; the adjusting branch is connected between the second input end of the differential current detection amplifier and the output of the differential operational amplifier unit and is used for realizing the dynamic equality of the voltages of the first input end and the second input end of the differential current detection amplifier; the output branch is an image current branch and is used for outputting an attenuated current signal after proportional attenuation.
The first branch comprises a first constant current source and a first field effect transistor, the first constant current source is generated by a reference in the chip and is obtained by mirroring, the first end of the first constant current source is connected to a power supply voltage, the second end of the first constant current source is connected with the drain electrode of the first field effect transistor, the grid electrode of the first field effect transistor is connected with the drain electrode of the first field effect transistor, and the source electrode of the first field effect transistor is connected to the base electrode of the first transistor; the collector and the base of the first transistor are connected together, and the emitter of the first transistor is connected with the emitter of the third transistor and is used as a first input end of the differential current detection amplifier together;
the second branch consists of a second field effect transistor and a fifth field effect transistor, the source electrode of the fifth field effect transistor is connected to a power supply voltage, the grid electrode and the drain electrode of the fifth field effect transistor are connected together and connected to the drain electrode of the second field effect transistor in parallel, the grid electrode of the second field effect transistor is connected with the grid electrode of the first field effect transistor, and the source electrode of the second field effect transistor is connected to the collector electrode of the second field effect transistor; the base electrode of the second transistor is connected to the base electrode of the first transistor, and the emitter electrode of the second transistor is connected with the emitter electrode of the fourth transistor and is used as a second input end of the differential current detection amplifier together;
The third branch consists of a third field effect transistor and a sixth field effect transistor, the source electrode of the sixth field effect transistor is connected to a power supply voltage, the grid electrode and the drain electrode of the sixth field effect transistor are connected together and connected to the drain electrode of the third field effect transistor in parallel, the grid electrode of the third field effect transistor is connected with the grid electrode of the first field effect transistor, and the source electrode of the third field effect transistor is connected to the collector electrode of the third field effect transistor; the base electrode of the third transistor is connected to the base electrode of the first transistor, and the emitter electrode of the third transistor is connected with the emitter electrode of the first transistor and is used as a first input end of the differential current detection amplifier together;
the fourth branch consists of a fourth field effect transistor and a seventh field effect transistor, the source electrode of the seventh field effect transistor is connected to a power supply voltage, the grid electrode of the seventh field effect transistor is connected with the grid electrode of the sixth field effect transistor, the drain electrode of the seventh field effect transistor is connected to the drain electrode of the fourth field effect transistor, the grid electrode of the fourth field effect transistor is connected with the grid electrode of the first field effect transistor, and the source electrode of the fourth field effect transistor is connected to the collector electrode of the fourth field effect transistor; the base electrode of the fourth transistor is connected to the base electrode of the first transistor, and the emitter electrode of the fourth transistor is connected with the emitter electrode of the second transistor and is used as a second input end of the differential current detection amplifier together.
The error cancellation branch is composed of a constant current branch generated by a reference in the control chip and comprises a current branch of a second constant current source which is slightly smaller than the first constant current source and is generated by the internal reference, the first end of the second constant current source is connected to the drain electrode of the fourth field effect transistor, and the second end of the second constant current source is grounded.
Preferably, the current level of the second constant current source in the error cancellation branch should be slightly smaller than that of the first constant current source to cancel the attenuation multiple calculation deviation introduced by the bias current.
The regulating branch circuit is composed of an eighth field effect transistor and a ninth field effect transistor, the source electrode of the eighth field effect transistor is connected to a power supply voltage, the grid electrode of the eighth field effect transistor is connected with the drain electrode of the seventh field effect transistor, and the drain electrode of the eighth field effect transistor is connected with the drain electrode of the ninth field effect transistor; the ninth field effect transistor gate is connected to the fourth field effect transistor gate, and the ninth field effect transistor source is connected to the fourth transistor emitter, and collectively serves as a second input terminal of the differential current sense amplifier.
The output branch is a mirror current branch and is composed of a tenth field effect transistor and an eleventh field effect transistor, wherein the grid electrode and the source electrode of the tenth field effect transistor are respectively connected with the grid electrode and the source electrode of the eighth field effect transistor, the drain electrode of the tenth field effect transistor is connected with the drain electrode of the eleventh field effect transistor, the grid electrode of the eleventh field effect transistor is connected with the grid electrode of the fourth field effect transistor, and the source electrode of the eleventh field effect transistor is connected with an external resistor and is used as an output end of the whole current detection circuit.
As described above, the current detection circuit provided by the invention is a current detection circuit based on-resistance sampling of a MOS transistor in an on-chip implementation scheme, and is used for detecting a switching current flowing through a switching power supply. The input circuit comprises a power switch tube (namely a first detection MOS tube, also simply called a first MOS tube) and a second detection MOS tube (also simply called a second MOS tube), wherein an input signal end is connected with an input voltage in a switching power supply and is connected to a drain end of the power switch tube to serve as a first input end of the differential current detection amplifier; the grid electrode of the power switch tube is connected with a switch tube control signal generated by the control chip, the source electrode of the power switch tube is connected with the control ground, and the voltage on the drain electrode of the power switch tube is the first current detection signal; and the grid electrode of the second detection MOS tube is connected with a switching tube control signal generated by the control chip, the source electrode of the second detection MOS tube is connected with the control ground, the drain electrode of the second detection MOS tube is connected to the second input end of the differential current amplifier, and the drain electrode voltage of the second detection MOS tube is the second current detection signal. The power switch tube and the second detection MOS tube are designed based on unit MOS tubes with consistent width-to-length ratio, wherein the power switch tube is connected with a plurality of unit MOS tubes in parallel, the second detection MOS tube is connected with a plurality of unit MOS tubes in series and is used for receiving a current signal to drop on the internal resistance of the detection MOS tube so as to obtain a voltage signal representing the condition of the switching current, and the switching current is attenuated in an accurate proportion by utilizing the comparison of the on-resistance of the MOS tubes of the same type and the offset of the process deviation. The differential current detection amplifier comprises a differential operational amplifier unit, an error counteracting branch, an adjusting branch and an output branch, wherein the structure of the differential operational amplifier unit is not limited to be a symmetrical structure, and the differential operational amplifier unit is respectively coupled to the drain end of the power switch tube and the drain end of the second detection MOS tube so as to receive current signals flowing through the power switch tube and the second current detection MOS tube. The regulating branch of the differential current detecting amplifier makes the voltages on the internal resistances of the two detecting MOS transistors of the differential operational amplifier unit equal, namely, the voltages of the two input ends of the differential operational amplifier unit are equal. Thus, the circuit can generate the attenuation current signal in proportion to the attenuation of the actual switching current, and mirror the attenuation current signal after attenuation and output the attenuation current signal, namely, the attenuation current signal which can represent the magnitude of the input switching current is provided to be output as a detection current signal.
In still another aspect of the present invention, there is provided a current detection method for detecting a switching current flowing through a switching power supply, the current detection method comprising: the sampling step, the input signal end receives the detected current signal and drops on the first MOS tube to generate a first current signal reflecting the actual current; the voltage on the two MOS tubes is equal through the differential current detection amplifier, so that an attenuation current signal is generated through the second MOS tube according to the current attenuation multiple; an image output step of outputting an attenuated current signal image to an output signal terminal through a differential current sense amplifier for being supplied to a sense resistor (Rcs) to generate a current sense voltage drop signal at a current sense terminal (CS); the two MOS tubes are composed of a plurality of unit MOS tubes with the same type and the same size, the internal resistance value of the first MOS tube is the parallel connection value of the N unit MOS tubes, and the internal resistance value of the second MOS tube is the serial connection value of the M unit MOS tubes; the current attenuation multiple is M times and N times.
The invention provides a current detection method based on MOS tube on-resistance sampling, when the control signal of a control chip to a switching tube is high level, a power switching tube and a second detection MOS tube work in a linear region on state, the current signal of a switching power supply is received based on the on-resistance of the power switching tube, and the internal resistances of the linear region of the second detection MOS tube and the power switching tube form a ratio, so that the input current is attenuated according to the ratio. The power switch tube and the second detection MOS tube are designed based on unit MOS tubes with consistent width-to-length ratio, wherein the power switch tube is formed by connecting a plurality of unit MOS tubes in parallel, and the second detection MOS tube is formed by connecting a plurality of unit MOS tubes in series; the differential current detection amplifier is used for equalizing the voltages of the drain ends of the two detection MOS tubes through regulating the branch circuits to generate detection current which is in decay proportion with the switching current; and mirroring and outputting the attenuated detection current, namely providing a detection current signal capable of representing the magnitude of the input switch current.
Drawings
For a better understanding of the present invention, the present invention will be described in detail with reference to the following drawings:
FIG. 1A is a schematic block diagram of a current detection circuit of the first prior art applied to a switching power supply;
FIG. 1B is a schematic block diagram of a current detection circuit of the second prior art applied to a switching power supply;
FIG. 2 is a schematic circuit diagram of a conventional current detection circuit;
FIG. 3 is a schematic block diagram of a current detection circuit applied to a switching power supply according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a current detection circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of connection details of a plurality of unit MOS transistors of each detection MOS transistor in the current detection circuit according to the embodiment of the present invention;
fig. 6 is a waveform diagram illustrating the operation of the current detection circuit in the switching power supply system according to the embodiment of the invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to these examples. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one having ordinary skill in the art that the present invention may be practiced without some of these specific details, and that certain methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
Fig. 3 is a schematic diagram of a switching power supply application of a current detection circuit according to an embodiment of the present invention, and only a portion relevant to the innovation of the present invention is shown for convenience of explanation. As one of the embodiments of the present invention, the switching power supply includes a power switch control chip U20, and a transformer A1, a diode D1, a capacitor C1, a resistor R1, and a resistor Rcs1.
The power switch control chip U20 of the switch power supply is an integrated chip and comprises a Drain electrode pin Drain of the switch tube, a current detection pin CS and a grounding pin GND.
The input end VIN of the switching power supply is connected with the homonymous end of the primary winding NP of the transformer A1, the heteronymous end of the primary winding NP of the transformer A1 is connected with a Drain pin of the power switch control chip U20, the homonymous end of the secondary winding NS of the transformer A1 is connected with the anode of the follow current diode D1, the cathode of the diode D1 is connected with one end of the output capacitor C1 and one end of the output resistor R1 together, and the other ends of the capacitor C1 and the resistor R1 are grounded with the heteronymous end of the secondary winding NS.
The power switch control chip U20 is composed of a current detection circuit 100 and a control circuit 200, where the control circuit 200 can control a current loop by using the sampled output voltage and the inductor current signal, and generate a GATE signal GATE of the power switch tube MNp to control the switching frequency and the on duty ratio of the power switch tube MNp in the current detection circuit 100.
The current detection circuit 100 includes an input signal end IIN, an output signal end IOUT, a driving signal input end GATE and a ground end GND, the input end IIN of the current detection circuit 100 is connected to a Drain pin of the power switch control chip U20, receives an input inductor current to be sampled, outputs a sampling current signal IOUT attenuated in equal proportion after operation processing of an internal differential current detection amplifying circuit, and the ground pin GND of the current detection circuit 100 is grounded.
The output signal end IOUT of the current detection circuit 100 is connected with one end of a current detection resistor Rcs1 with adjustable size at the periphery of the chip, and the other end of the current detection resistor Rcs1 is grounded; the inside of the chip can also be designed with a current detection resistor Rcs2 with higher precision, the output signal end IOUT of the current detection circuit 100 is connected with one end of the current detection resistor Rcs2 with fixed resistance value inside the chip, and the other end of the current detection resistor Rcs2 is grounded.
Fig. 4 is a circuit diagram of a current detection circuit 100 according to an embodiment of the present invention, and as shown in fig. 4, the current detection circuit 100 according to an embodiment of the present invention includes an input signal terminal IIN, an output signal terminal IOUT, a driving signal input terminal GATE, and a ground terminal GND, and further includes an input circuit 11 and a differential current detection amplifier 12, wherein:
The input circuit 11 includes a power switch tube (i.e. a first detection MOS tube) MNp and a second detection MOS tube MNs, where the input signal end IIN is used to connect to an input voltage in the switching power supply and to connect to a drain end of the power switch tube MNp, and the drain end of the power switch tube MNp is further led out as a first output end of the input circuit 11 and is used to connect to a first input end Va of the differential current amplifier; the GATE end of the power switch tube MNp receives a switch tube control signal GATE generated by a control chip, and the source end of the power switch tube MNp is grounded to GND; the drain terminal of the second detection MOS tube is led out to serve as a second output terminal of the input circuit 11 and is used for being connected to a second input terminal Vb of the differential current amplifier, the GATE terminal of the second detection MOS tube receives a switching tube control signal GATE generated by the control chip, and the source terminal of the second detection MOS tube is grounded GND.
The input circuit 11 is configured to receive a current signal Iin to be detected in the switching power supply and drop the current signal Iin on the internal resistance of the power switching tube MNp, so as to generate a first current signal reflecting an actual current, obtain a voltage signal VA representing an actual switching current condition, and offset a process deviation by using the on-resistance of the same type of MOS tube, so as to realize accurate proportional attenuation of the switching current. The power switch tube and the second detection MOS tube are designed based on unit MOS tubes with consistent width-to-length ratio, wherein the power switch tube is connected with N unit MOS tubes in parallel, and the resistance value of the internal resistance of a linear region can be as low as 10-100 milliohm level; the second detection MOS tube is formed by connecting M unit MOS tubes in series; the resistance value of the internal resistance of the linear region is about 10 ohms; the ratio of the detected current signal Iout obtained after passing through the differential current detection amplifier 12 to the switching current Iin is:
Namely, the current attenuation multiple A of the current detection circuit is M times N times.
The differential current sense amplifier 12 includes a differential operational amplifier unit 120, an error cancellation branch 126, a regulation branch 127, and an output branch 129. Wherein:
the differential operational amplifier unit 121 includes a first input terminal Va and a second input terminal Vb, a first branch 121, a second branch 122, a third branch 123 and a fourth branch 124, and first and third transistors Q1 and Q3, and second and fourth transistors Q2 and Q4 constituting a differential input transistor pair. The first input terminal Va and the second input terminal Vb are coupled to the drain terminal of the power switch tube MNp and the drain terminal of the second detecting MOS tube, respectively, to receive the first current detection signal (i.e., a signal reflecting the actual current) and the second current detection signal (i.e., an attenuation current signal).
The first branch 121 is a constant current circuit including a first constant current source I1 generated from an internal reference, and is connected to a first output terminal of the input circuit 11 through a first transistor Q1. The first branch 121 comprises a first constant current source I1 and a first field effect transistor M1, the first constant current source I1 is generated by a reference inside a chip and is mirrored, a first end of the first constant current source I1 is connected to a power supply voltage end VCC, a second end of the first constant current source I1 is connected with a drain electrode of the first field effect transistor M1, a grid electrode of the first field effect transistor M1 is connected with the drain electrode of the first field effect transistor M1, and a source electrode of the first field effect transistor M1 is connected to a base electrode of the first transistor Q1; the collector and base of the first transistor Q1 are connected together, and the emitter of the first transistor Q1 is connected to the emitter of the third transistor Q3 and led out as a first input Va of the differential current sense amplifier 12 for connection to a first output of the input circuit 11.
The second branch 122 is a constant current branch in mirror image relationship with the fourth branch 124 and is connected to the second output terminal of the input circuit 11 through a second transistor Q2. The second branch 122 is composed of a second field effect transistor M2 and a fifth field effect transistor M5, wherein the source electrode of the fifth field effect transistor M5 is connected to the power supply voltage VCC, the gate electrode and the drain electrode of the fifth field effect transistor M5 are connected together and connected to the drain electrode of the second field effect transistor M2 in parallel, the gate electrode of the second field effect transistor M2 is connected to the gate electrode of the first field effect transistor M1, and the source electrode of the second field effect transistor M2 is connected to the collector electrode of the second transistor Q2; the base of the second transistor Q2 is connected to the base of the first transistor Q1, and the emitter of the second transistor Q2 is connected to the emitter of the fourth transistor Q4 and led out as a second input terminal Vb of the differential current sense amplifier 12 for connection to a second output terminal of the input circuit 11.
The third branch 123 is a constant current circuit mirrored by the first constant current source I1, and is connected to the first output terminal of the input circuit through the third transistor Q3. The third branch 123 is composed of a third field effect transistor M3 and a sixth field effect transistor M6, wherein the source electrode of the sixth field effect transistor M6 is connected to the power supply voltage VCC, the gate electrode and the drain electrode thereof are connected together and connected to the drain electrode of the third field effect transistor M3, the gate electrode of the third field effect transistor M3 is connected to the gate electrode of the first field effect transistor M1, and the source electrode of the third field effect transistor M3 is connected to the collector electrode of the third transistor Q3; the base of the third transistor Q3 is connected to the base of the first transistor Q1, and the emitter of the third transistor Q3 is connected to the emitter of the first transistor Q1, so as to be used as the first input terminal Va of the differential current detection amplifier 12 together, so as to be connected to the first output terminal of the input circuit 11.
The first transistor Q1 and the third transistor Q3 form a current mirror, so that the third branch current I3 and the first branch current I1 have the following relationship:
I3＝I1......(2)
the fourth branch 124 is a constant current branch in mirror image relationship with the second branch 122, and is added to the error cancellation branch 126 to form a mirror image equal to the third branch current I3, and is connected to the second output terminal of the input circuit through a fourth transistor Q4. The fourth branch 124 is composed of a fourth field effect transistor M4 and a seventh field effect transistor M7, the source of the seventh field effect transistor M7 is connected to the power voltage VCC, the gate thereof is connected to the gate of the sixth field effect transistor M6, the drain of the seventh field effect transistor M7 is connected to the drain of the fourth field effect transistor M4, and the drain of the seventh field effect transistor M7 is also used as the output of the differential operational amplifier unit 120; the gate of the fourth field effect transistor M4 is connected to the gate of the first field effect transistor M1, and the source of the fourth field effect transistor M4 is connected to the collector of the fourth transistor Q4; the base of the fourth transistor Q4 is connected to the base of the first transistor Q1, and the emitter of the fourth transistor Q4 is connected to the emitter of the second transistor Q2, so as to be used together as the second input terminal Vb of the differential current detection amplifier 12, so as to be connected to the second output terminal of the input circuit 11.
The second transistor Q2 and the fourth transistor Q4 form a current mirror, so that the relationship between the fourth branch current I4 and the second branch current I2 is:
I4＝I2......(3)
the error cancellation branch 126 is a constant current branch including a second constant current source I5 slightly smaller than the first constant current source, which is generated by a reference inside the chip and mirrored, and is connected to the output of the differential operational amplifier unit 120. The first end of the second constant current source I5 is connected to the drain of the fourth field effect transistor M4, and the second end thereof is connected to the ground GND. From the mirror relationship of the sixth field effect transistor M6 and the seventh field effect transistor M7 and the node current equation of the drain of the fourth field effect transistor M4, it is possible to obtain:
I4+I5＝I3......(4)
the current of the second constant current source I5 in the error cancellation branch 123 should be close to the current value of the first constant current source I1 to cancel the error of the attenuation multiple a introduced by the bias current of the first constant current source I1; namely:
I5≈I1......(5)
note that the second constant current source I5 has to be slightly smaller than the first constant current source I1 to ensure that the second branch current I2 allows the transistors of both the second and fourth branches to operate in the saturation region.
The regulation branch 127 is connected between the second input terminal Vb of the differential current detection amplifier and the output of the differential operational amplifier unit 120, so as to be connected between the input and the output of the differential operational amplifier unit 120 in a feedback form, and is used for realizing dynamic equality of the voltages of the first input terminal Va and the second input terminal Vb of the differential operational amplifier unit 120. The regulation branch 127 is formed by eighth and ninth field effect transistors M8 and M9, and generates a regulation branch current I6, where a source of the eighth field effect transistor M8 is connected to a power supply voltage VCC, a gate of the eighth field effect transistor M8 is connected to a drain of the seventh field effect transistor M7, and a drain of the eighth field effect transistor M9 is connected to a drain of the ninth field effect transistor M9; the gate of the ninth field effect transistor M9 is connected to the gate of the fourth field effect transistor M4, and the source of the ninth field effect transistor M9 is connected to the emitter of the fourth transistor Q4, together as the second input terminal Vb of the differential current sense amplifier 12.
The voltage Va and Vb at the two input terminals Va and Vb of the differential operational amplifier unit 120 are equal by the action of the adjusting branch 127, and the circuit principle can be known as follows:
VA＝(Iin+I1+I3)*R MNP_on ……(6)
VB＝(I2+I4+I6)*R MNs_on ……(7)
VA＝VB……(8)
the output branch 129 is an image current branch, and is connected to the output of the differential operational amplifier unit 120, and is used as a final stage circuit of the differential current detection amplifier 12, and is configured to output a detection current signal Iout that can represent the switching current after being attenuated proportionally. The output branch 129 is formed by tenth and eleventh field effect transistors M10 and M11, wherein the gate and source of the tenth field effect transistor M10 are respectively connected with the gate and source of the eighth field effect transistor M8, the drain of the tenth field effect transistor M10 is connected with the drain of the eleventh field effect transistor M11, the gate of the eleventh field effect transistor M11 is connected with the gate of the fourth field effect transistor M4, and the source of the eleventh field effect transistor M11 is led out as an output signal terminal IOUT of the current detection circuit, and outputs a detection current signal IOUT as an output terminal of the whole current detection circuit for connection with an external detection resistor. The gate voltages and the source voltages of the field effect transistors M10 and M8 are respectively connected to the same node, and the design dimensions are equal, so that the branch currents where the field effect transistors M10 and M8 are located are equal, namely:
Iout＝16......(9)
The method is characterized in that the method is obtained by finishing (2) to (9):
the input current Iin is generally an ampere-level current, and the constant current source is a microampere level current, so that 2 x I1 in the denominator of the formula can be ignored, iout obtained by attenuation in a molecule is generally a microampere level, the bias current sources I1 and I5 are both microampere levels, and the I5 is designed to be a current value slightly smaller than the I1, so that the influence of constant current bias on attenuation multiple is reduced to the greatest extent. (10) The derivation of the equation verifies the correctness of the design principle equation (1). The two sampling resistors Rp and Rs which are composed of a plurality of unit metal resistors with the same type and the same size can offset the influence of the process deviation and the temperature drift coefficient of the sampling resistor on the detection attenuation multiple, eliminate the influence factor of the sampling current on the process temperature characteristic of the resistor, and ensure the accuracy, the high precision and the reliability of the current detection attenuation multiple. The invention solves the problem that nondestructive detection, smaller PCB area and adjustable peak current can not be achieved in the prior art, the detection precision of the current detection method is irrelevant to the process temperature characteristic of the sampling resistor, and the detection purpose of providing the detection current signal capable of representing the magnitude of the input switch current with high accuracy and reliability is realized.
Fig. 5 is a schematic diagram of connection details of a plurality of unit MOS transistors of a power MOS transistor in a current detection circuit according to an embodiment of the present invention. In the input circuit 11, the power switch tube MNp and the second detection MOS tube MNs are designed based on unit MOS tubes with consistent width-to-length ratio, and the power switch tube (i.e., the first detection MOS tube) MNp is formed by connecting N unit MOS tubes in parallel. The input signal end IIN is connected with the input voltage in the switching power supply, is connected to the drain end of the unit MOS tube MNp1, MNp2 … … MNPn, is also led out to serve as a first output end of the input circuit 11, and is used for being connected to a first input end Va of the differential current amplifier; the GATE ends of the unit MOS tubes MNp, MNp2, … … MNPn are connected together and receive a switching tube control signal GATE generated by a control chip; the source ends of the unit MOS transistors MNp1, MNp2 … … MNPn are grounded to GND. The second detection MOS transistor MNs is formed by connecting M unit MOS transistors in series, wherein the source end of the unit MOS transistor MNs1 is grounded to GND, the drain end of the unit MOS transistor MNs2 is connected to the source end of the unit MOS transistor MNs2, the drain end of the unit MOS transistor MNs2 is connected to … … the source end of the unit MOS transistor MNs3 (M-1), the drain end of the unit MOS transistor MNsm is connected to the source end of the unit MOS transistor MNsm, and finally the drain end of the unit MOS transistor MNsm leads out the second output end of the input circuit 11 and is used for being connected to the second input end Vb of the differential current amplifier; the GATE ends of the unit MOS tubes MNs1, MNs2 and … … MNSM are connected together and receive a switching tube control signal GATE generated by a control chip.
In order to prevent errors caused by bias effects, preferably, substrates of M serial unit MOS transistors of the second detection MOS transistor MNs are all connected to respective source-end potentials.
The following describes and illustrates the implementation of the preferred embodiment of the invention based on the above-described circuit.
Fig. 6 is a waveform diagram illustrating the operation of the current detection circuit in the switching power supply system according to the embodiment of the invention. The DCM (discontinuous) operation mode is exemplified here, but it should be noted that the present invention has the same effect on current detection in CCM (continuous) mode.
In the t1 period, the GATE signal Is low level to control the power switch tube to turn off, during which the Drain terminal Drain of the switch tube (i.e. the input signal terminal IIN of the current detection circuit) Is connected to the input voltage VIN through the primary side inductor of the transformer, so that the Drain terminal Drain of the switch tube presents a high voltage waveform equal to the input voltage, the secondary side inductor of the transformer starts to demagnetize, and the secondary side current Is gradually decreases from the peak current Ispk to 0. And entering a t2 period, wherein the secondary side current is reduced to 0 at the stage, but the power switch tube is not opened yet, and the Drain terminal Drain terminal voltage of the switch tube presents a high-voltage ringing waveform under the charge and discharge action of leakage inductance, so that the power switch tube is also called as a ringing stage of an intermittent mode. the current Iin flowing into the current detection circuit from the primary side in the time period of t1 and t2 is 0 due to the turn-off of the power switch tube, and the voltage drop VCS on the current detection pin CS is also 0; until the power switch tube is started, a stage t3 is entered, the primary winding is excited, and the primary current Iin gradually rises to Ipk; the attenuation of the current detection circuit 100 generates the waveform of the output signal terminal IOUT in fig. 6, i.e. the current attenuated by m×n by Iin, assuming that the internal resistance R of the power switch tube MNp is taken MNP_on Taking the internal resistance value R of the second detection tube MNs as the parallel value of 30 unit MOS tubes MNS_on Is the serial value of 30 unit MOS tubes, passes throughThe attenuated detection current Iout obtained by the current detection circuit is 1/900 of the input inductance current; finally, the output current Iout drops on a detection resistor outside the chip to generate VCS voltage for the internal current loop circuit to adopt to control a loop. The magnitude of VCS voltage is equal to rcs_ipk/(m_n), and corresponds to two external application schemes of the output signal terminal IOUT of the current detection circuit 100 and the detection resistor with adjustable magnitude of the chip periphery shown in fig. 5, two calculation modes are also corresponding to the magnitude of VCS voltage, that is, rcs 1_ipk/(m_n) and Rcs 2_ipk/(m_n).
The invention has the beneficial effects that:
in order to solve the problem that nondestructive testing, smaller PCB cost and adjustable peak current cannot be achieved in the prior art, the circuit provided by the preferred embodiment of the invention is adopted. Compared with the prior art, 1) the on-resistance of the linear region of the unit power switching tubes is parallel when the main power loop receives switching current, the resistance is as low as 10 milliohms to 1 ohm (10 mΩ -1 Ω), even if the input current has ampere (A) level, the loss on the parallel metal resistor is very small, which is equivalent to realizing nondestructive detection; 2) The two detection MOS tubes in the circuit are obtained by respectively connecting unit MOS tubes with the same type and the same width-to-length ratio in parallel and in series, and when the layout is drawn, attention is paid to matching of the two detection MOS tubes, so that the influence of process deviation and temperature drift coefficient of the resistance of the linear region of the MOS tubes on the detection attenuation multiple can be counteracted, the detection current is not influenced by the process temperature characteristic of the detection MOS tubes, and the accuracy, high precision and reliability of the current detection attenuation multiple are ensured; 3) The peak voltage can be adjusted only by connecting the detection resistor outside the chip with the current detection signal attenuated by the current detection circuit, and the detection resistor can be properly increased (generally k omega level) on the premise of ensuring that the MOS tube inside the chip works in a saturation region because the output current is determined, so that a larger peak voltage value can be obtained, the signal-to-noise ratio of the detection signal under light load is improved, and the anti-interference capability of the detection is enhanced; 4) The circuit provided by the preferred embodiment of the invention can be integrated in a chip of a CMOS process, can be integrated in a control chip, can also be independently made into a chip for replacing a transformer for system application, saves the PCB layout area and the packaging pins, ensures that the whole switching power supply has low cost and small volume, and is beneficial to the improvement of the power density of the switching power supply.
Claims (11)
1. A current detection circuit for detecting a current in a switching power supply, comprising:
the input signal end and the output signal end, and also comprises an input circuit and a differential current detection amplifier,
the input circuit comprises two MOS tubes, namely a first MOS tube and a second MOS tube, wherein the first MOS tube multiplexes a power switch tube in the switch power supply, the two MOS tubes are composed of a plurality of unit MOS tubes with the same type and the same size, and the unit MOS tubes form different internal resistance values according to the set current attenuation times in a parallel connection and serial connection mode, and are respectively a first MOS tube with a smaller internal resistance value and a second MOS tube with a larger internal resistance value; the two MOS tubes are respectively connected to two input ends of the differential current detection amplifier, and the internal resistances of the two MOS tubes are used as sampling resistors; wherein, the liquid crystal display device comprises a liquid crystal display device,
when the two MOS tubes work in a linear conduction state, receiving a detected current signal based on the conduction resistance of the first MOS tube, and generating a first current signal reflecting actual current; the voltage on the two MOS tubes is equal through the differential current detection amplifier, so that an attenuation current signal is generated through the second MOS tube according to the current attenuation multiple, and then the attenuation current signal is mirrored through the differential current detection amplifier and is output to the output signal end.
2. The current detection circuit of claim 1, wherein: the first MOS tube and the second MOS tube of the input circuit, the internal resistance value of the first MOS tube is the parallel connection value of the internal resistances of the N unit MOS tubes, and the internal resistance value of the second MOS tube is the serial connection value of the internal resistances of the M unit MOS tubes; the current attenuation multiple of the input circuit is M times N times.
3. The current detection circuit according to claim 2, wherein: the substrates of the M serial unit MOS tubes of the second MOS tube are connected with respective source end potentials.
4. A current detection circuit according to any one of claims 1 to 3, wherein: the first MOS tube and the second MOS tube of the input circuit are connected with the same driving signal by the grid electrodes, the source electrodes of the first MOS tube and the second MOS tube are grounded, the drain electrode of the first MOS tube is connected with the input signal end, and the drain electrode of the first MOS tube is led out to serve as a first output end of the input circuit; the drain electrode of the second MOS tube is led out to serve as a second output end of the input circuit.
5. The current detection circuit of claim 4, wherein: the differential current detection amplifier comprises a differential operational amplifier unit, an error cancellation branch, an adjusting branch and an output branch which are sequentially connected, a first input end connected with a first output end of an input circuit and a second input end connected with a second output end of the input circuit,
The differential operational amplifier unit comprises a first branch, a second branch, a third branch and a fourth branch, a first transistor and a third transistor pair, a second transistor and a fourth transistor pair which form a differential input transistor pair;
the first branch is a constant current circuit comprising a first constant current source generated by an internal reference and is connected with a first output end of the input circuit through a first transistor;
the second branch is a current branch in mirror image relation with the fourth branch and is connected with a second output end of the input circuit through a second transistor;
the third branch is a current branch obtained by mirroring the first constant current source and is connected with a first output end of the input circuit through a third transistor;
the fourth branch is a current branch in mirror image relation with the second branch, and the mirror image is equal to the current of the third branch after being added with the error counteracting branch, and is connected with the second output end of the input circuit through a fourth transistor;
the error cancellation branch is a current branch comprising a second constant current source slightly smaller than the first constant current source and generated by an internal reference;
the adjusting branch is connected between the second input end of the differential current detection amplifier and the output of the differential operational amplifier unit;
The output branch is an image current branch and is used for outputting an attenuated current signal after proportional attenuation.
6. The current detection circuit of claim 5, wherein: the first branch comprises a first constant current source and a first field effect transistor, the first end of the first constant current source is connected to a power supply voltage, the second end of the first constant current source is connected with the drain electrode of the first field effect transistor, the grid electrode of the first field effect transistor is connected with the drain electrode of the first field effect transistor, and the source electrode of the first field effect transistor is connected to the base electrode of the first transistor; the collector and the base of the first transistor are connected together, the emitter of the first transistor is connected with the emitter of the third transistor, and the first input end serving as a differential current detection amplifier is led out;
the second branch consists of a second field effect transistor and a fifth field effect transistor, the source electrode of the fifth field effect transistor is connected to the power supply voltage, the grid electrode and the drain electrode of the fifth field effect transistor are connected together and connected to the drain electrode of the second field effect transistor in parallel, the grid electrode of the second field effect transistor is connected with the grid electrode of the first field effect transistor, and the source electrode of the second field effect transistor is connected to the collector electrode of the second transistor; the base electrode of the second transistor is connected to the base electrode of the first transistor, the emitter electrode of the second transistor is connected with the emitter electrode of the fourth transistor, and the second input end serving as a differential current detection amplifier is led out;
The third branch consists of a third field effect transistor and a sixth field effect transistor, the source electrode of the sixth field effect transistor is connected to the power supply voltage, the grid electrode and the drain electrode of the sixth field effect transistor are connected together and connected to the drain electrode of the third field effect transistor in parallel, the grid electrode of the third field effect transistor is connected with the grid electrode of the first field effect transistor, and the source electrode of the third field effect transistor is connected to the collector electrode of the third transistor; the base electrode of the third transistor is connected to the base electrode of the first transistor, and the emitter electrode of the third transistor is connected with the emitter electrode of the first transistor;
the fourth branch consists of a fourth field effect transistor and a seventh field effect transistor, the source electrode of the seventh field effect transistor is connected to the power supply voltage, the grid electrode of the seventh field effect transistor is connected with the grid electrode of the sixth field effect transistor, the drain electrode of the seventh field effect transistor is connected to the drain electrode of the fourth field effect transistor, the grid electrode of the fourth field effect transistor is connected with the grid electrode of the first field effect transistor, and the source electrode of the fourth field effect transistor is connected to the collector electrode of the fourth field effect transistor; the base electrode of the fourth transistor is connected to the base electrode of the first transistor, and the emitter electrode of the fourth transistor is connected with the emitter electrode of the second transistor and is used as a second input end of the differential current detection amplifier.
7. The current detection circuit of claim 5, wherein: the error cancellation branch comprises a second constant current source, a first end of the second constant current source is connected to the drain electrode of the fourth field effect transistor, and a second end of the second constant current source is grounded.
8. The current detection circuit of claim 5, wherein: the regulating branch circuit is composed of an eighth field effect transistor and a ninth field effect transistor, the source electrode of the eighth field effect transistor is connected to the power supply voltage, the grid electrode of the eighth field effect transistor is connected with the drain electrode of the seventh field effect transistor, and the drain electrode of the eighth field effect transistor is connected with the drain electrode of the ninth field effect transistor; the ninth field effect transistor gate is connected to the fourth field effect transistor gate and the ninth field effect transistor source is connected to the emitter of the fourth transistor.
9. The current detection circuit of claim 5, wherein: the output branch circuit is composed of a tenth field effect transistor and an eleventh field effect transistor, wherein the grid electrode and the source electrode of the tenth field effect transistor are respectively connected with the grid electrode and the source electrode of the eighth field effect transistor, the drain electrode of the tenth field effect transistor is connected with the drain electrode of the eleventh field effect transistor, the grid electrode of the eleventh field effect transistor is connected with the grid electrode of the fourth field effect transistor, and the source electrode of the eleventh field effect transistor is led out to serve as an output end of the current detection circuit.
10. The current detection circuit according to any one of claims 5 to 9, wherein: the circuit also comprises a first detection resistor, wherein one end of the first detection resistor is connected with the output signal end of the current detection circuit and is led out to serve as a current detection end; the other end of the first detection resistor is grounded.
11. A current detection method for detecting a current in a switching power supply, comprising the steps of:
the sampling step, the input signal end receives the detected current signal and drops on the first MOS tube to generate a first current signal reflecting the actual current; the voltage on the two MOS tubes is equal through the differential current detection amplifier, so that an attenuation current signal is generated through the second MOS tube according to the current attenuation multiple;
an image output step of outputting an attenuated current signal image to an output signal end through a differential current detection amplifier;
the two MOS tubes are composed of a plurality of unit MOS tubes with the same type and the same size, the internal resistance value of the first MOS tube is the parallel connection value of the N unit MOS tubes, and the internal resistance value of the second MOS tube is the serial connection value of the M unit MOS tubes; the current attenuation multiple is M times and N times.
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| CN107765067B (en) * | 2017-10-17 | 2023-07-07 | 深圳南云微电子有限公司 | Current detection circuit and current detection method |
| CN109802583A (en) * | 2019-01-11 | 2019-05-24 | 深圳南云微电子有限公司 | A kind of full-bridge synchronous rectifier integrated with current detecting |
| CN115236481B (en) * | 2022-05-24 | 2023-10-27 | 上海沛塬电子有限公司 | High-precision current detection method and chip module thereof |
| CN116973618B (en) * | 2023-09-25 | 2023-12-08 | 上海紫鹰微电子有限公司 | Current sampling circuit |
| CN117118766B (en) * | 2023-10-13 | 2024-02-06 | 无锡众享科技有限公司 | Current equalization circuit and two-way Ethernet power supply system |
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