CN107926112B - Circuit structure - Google Patents
Circuit structure Download PDFInfo
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- CN107926112B CN107926112B CN201680048905.3A CN201680048905A CN107926112B CN 107926112 B CN107926112 B CN 107926112B CN 201680048905 A CN201680048905 A CN 201680048905A CN 107926112 B CN107926112 B CN 107926112B
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- conductor
- interlayer connection
- ground conductor
- multilayer substrate
- circuit structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/08—Microstrips; Strip lines
- H01P3/085—Triplate lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
- H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
- H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0433—Sockets for IC's or transistors
- G01R1/0441—Details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/08—Microstrips; Strip lines
- H01P3/088—Stacked transmission lines
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
Abstract
There is provided a circuit structural body formed in a shape including a multilayer substrate including a plurality of layers of first to N-th three-plate structural bodies each including first to N-th (N is an integer of 2 or more) planar conductors, an interlayer connection conductor, and a side ground conductor; the interlayer connection conductor is configured to connect the first to Nth planar conductors to each other; the side ground conductor is formed on a side of the multilayer substrate substantially parallel to and adjacent to the inter-operative layer connection conductor.
Description
Technical Field
The present invention relates to a circuit structure of a multilayer substrate forming a high-frequency circuit, and more particularly to a circuit structure body having a multilayer three-plate structure.
Background
In a high frequency circuit, a three-plate structure is used in many cases. Further, a three-plate line structure in which a three-plate structure is formed by using each layer of a multilayer substrate has been studied.
The three-plate structure is described in, for example, patent document 1 and patent document 2.
In patent document 1, an inter-board connecting element of a three-board strip line type in which three-board structures are engaged with each other is described. In the inter-board connecting element of the three-board strip line type, strip conductors respectively formed between the first layer and the second layer and between the third layer and the fourth layer of a multilayer substrate formed of four layers are joined to each other by through-hole plating (via hole).
Further, patent document 2 discloses a three-board line interlayer connector (structure) between a first three-board line and a second three-board line.
Documents of the prior art
Patent document
Patent document 1: JP S63-158004U
Patent document 2: JP 2013-05296A
Disclosure of Invention
Problems to be solved by the invention
A three-plate structure using a multilayer substrate is used in various high-frequency circuits.
In addition, the high frequency circuit requires various demands. Among these requirements, for example, in order to realize a wider range and higher functions of the microstrip antenna, a demand for narrowing the distance between elements has been increased. Recently, in addition to series feeding to the related art microstrip antenna, a need for supporting parallel feeding has been increased for a high frequency circuit. This growing demand also leads to a demand for narrowing the distance between the elements. In addition, for example, when the number of layers in the multilayer substrate is further increased, many connection spaces are required in order to connect lines in different layers to each other. As a result, as the number of layers of the panel increases, various restrictions on design and manufacturing also greatly affect the three-panel structure surroundings.
For example, in the three-plate stripline type inter-board connection element described in patent document 1, it is difficult to uniformly join two or more layers of three-plate structures.
Further, in the description of the three-plate structure of patent document 2, a structure and a method in which a three-plate structure including two or more layers and three-plate lines are connected to each other by a conductor are not disclosed.
Further, as the components of the three-plate structure, there are cases where it is necessary to appropriately provide components for suppressing energy loss. The inventors of the present invention have conceived that this component will be required in the future for a circuit structure in which three-plate lines in different layers are connected to each other through conductors in a multilayer substrate structure having a plurality of three-plate structures.
In patent document 1, it is not assumed that the component is provided in a through hole portion of a three-plate line for connecting a plurality of layers. Further, in patent document 2, a member for connecting three-plate wires to each other by a conductor is not disclosed, and a member thereof is not assumed.
The present invention has been made on the assumption as described above, and provides a circuit structure body having a circuit structure including a plurality of planar conductors which have a three-plate structure in different layers of a multilayer substrate and are connected to each other by conductors, the circuit structure body having a small footprint and maintaining good circuit characteristics.
Means for solving the problems
According to an embodiment of the present invention, there is provided a circuit structure body including:
a multilayer substrate including a plurality of layers of first to N-th three-plate structural bodies each including first to N-th (N is an integer of 2 or more) planar conductors;
an interlayer connection conductor configured to connect the first to nth plane conductors to each other; and
a side ground conductor formed on a side of the multilayer substrate close to the interlayer connection conductor and substantially parallel to the interlayer connection conductor.
Effects of the invention
According to the present invention, it is possible to provide a circuit structure body having a circuit structure including a plurality of planar conductors which have a three-plate structure in different layers of a multilayer substrate and are connected to each other by conductors, the circuit structure body having a small footprint and maintaining good circuit characteristics.
Drawings
Fig. 1 includes an explanatory view for explaining a circuit structure body according to an embodiment of the present invention.
Fig. 2 includes an explanatory view for explaining a circuit structure body according to another embodiment of the present invention.
Fig. 3 includes an explanatory view for explaining a circuit structure body for comparison with the present invention.
Fig. 4 includes an explanatory diagram for illustrating characteristics of one circuit structure body according to the embodiment of the present invention.
Fig. 5 includes an explanatory view for explaining a circuit structure body according to still another embodiment of the present invention.
Fig. 6 is an explanatory view for explaining a circuit structure body according to still another embodiment of the present invention.
Fig. 7 is an explanatory view for explaining a circuit structure body according to still another embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described with reference to the accompanying drawings.
Fig. 1 includes an explanatory view for explaining a circuit structure body according to an embodiment of the present invention. Fig. 1(a) is a perspective view for explaining a four-layer substrate including a two-layer three-plate structure. Fig. 1(b) to 1(d) are sectional views in three directions.
In this embodiment, the broadband lines of the parallel plate transmission lines are formed on a two-layer three-plate four-layer substrate. The wire may be used as a power supply circuit for a high-frequency circuit or an antenna.
In the multilayer substrate 1 serving as a two-layer three-plate structure body, the ground conductor surface and the planar conductor forming the three-plate line are formed in the respective layers. Further, in the multilayer substrate 1, the side surface ground conductor 2 is formed on the side surface (the depth side surface of fig. 1 (a)).
The side surface ground conductor 2 formed on the multilayer substrate 1 maintains a substantially parallel relationship with an interlayer connection conductor 3 described later. The side ground conductor 2 may be formed to cover the entire side, or may be limitedly formed around the interlayer connection conductor 3. It is desirable that the side ground conductor 2 has at least a size large enough to cover a projected portion formed when the interlayer connection conductor 3 is projected onto the side.
In the inner layer of the multilayer substrate 1, a plurality of planar conductors 4 serving as three-plate lines are formed. The planar conductors 4 in the respective layers are connected to each other via the interlayer connection conductor 3.
In the following description, the planar conductor 4 on the upper side in the drawing is referred to as an upper three-plate line conductor, the planar conductor 4 on the lower side in the drawing is referred to as a lower three-plate line conductor, and the interlayer connection conductor 3 is referred to as an interlayer connection line.
The interlayer connection conductor 3 functions to connect the planar conductors 4 (the upper three-plate line conductor and the lower three-plate line conductor) formed in different layers of the multilayer substrate 1 to each other while maintaining high-frequency characteristics.
In the present embodiment, one ground conductor layer is formed in a layer between the second layer and the third layer (a layer between the plurality of planar conductors 4 serving as three-plate line conductors) of the multilayer substrate 1, in which a portion corresponding to the interlayer connection conductor 3 is excluded. The ground conductor layer is commonly used as a ground conductor surface in the upper and lower three-plate structures. In the following description, the commonly used ground conductor surface is referred to as an intermediate ground conductor surface. The circuit structure portion may be formed such that each of the three-plate structures has an upper ground conductor surface and a lower ground conductor surface, respectively, without using an intermediate ground conductor surface.
In this embodiment, the interlayer connection conductor 3 is formed as a planar conductor. The interlayer connection conductor 3 is formed in a shape that achieves impedance matching with the planar conductor 4 serving as a three-plate line. The interlayer connection conductor 3 may be formed by mounting a conductive material, or may be formed by filling a conductive material with a via, for example.
It is desirable that the distance between the ground conductor 2 and the interlayer connection conductor 3 formed on the side face of the multilayer substrate 1 is a distance smaller than half the distance between the intermediate ground conductor surface and the surface ground conductor surfaces (upper surface ground conductor and lower surface ground conductor) to be formed on the multilayer substrate 1 (1/2). Preferably, the distance is expected to be about three-quarters of a single layer (3/4). In other words, it is desirable that this distance is equal to or smaller than the distance between the three-plate line forming the three-plate structure and the respective two ground conductor surfaces.
In this way, a circuit structure including a plurality of planar conductors having a three-plate structure in different layers of the multilayer substrate and connected to each other by conductors is formed.
In the relationship between the components of the circuit structure in this case, the side surface ground conductor is formed on the side surface of the substrate at a position where the side surface ground conductor and the interlayer connection conductor have an optimum positional relationship with respect to the high-frequency circuit. With this structure, it is possible to secure waveguides of different three-plate structures while saving space and maintaining circuit functions. Furthermore, the size of the cut-outs formed in the surface of the intermediate ground conductor can be optimally designed, thereby achieving further space savings.
That is, according to the present embodiment, it is possible to provide a circuit structure body that has a small footprint and maintains good circuit characteristics, with a circuit structure including a plurality of planar conductors that have a three-plate structure in different layers of a multilayer substrate and are connected to each other by conductors.
Next, another embodiment of the present invention is described. In the description of this embodiment, the same portions as those of the above-described embodiment are simplified or omitted.
Fig. 2 includes an explanatory view for explaining a circuit structure body of another embodiment. Fig. 2(a) is a perspective view for explaining a four-layer substrate having a two-layer three-plate structure. Fig. 2(b) to 2(d) are sectional views in three directions. The circuit structure shown in fig. 2 is different from the circuit structure shown in fig. 1 in that the interlayer connection conductor 3 is formed of a through hole.
As shown in fig. 2, the interlayer connection conductor 3 is a cylindrical (columnar) through-hole. Further, the interlayer connection conductor 3 may be formed as a cylindrical (columnar) via hole in an inner layer of the multilayer substrate.
In the multilayer substrate 1', similarly to the above-described embodiment, the three-plate line and the ground conductor surface of the parallel plate transmission mode are formed in the respective layers, and the ground conductor 2 is formed on the side face (the depth side face of fig. 2 (a)). The ground conductor 2 has a relationship substantially parallel to the interlayer connection conductor 3.
In this way, a circuit structure including a plurality of planar conductors having a three-plate structure in different layers of the multilayer substrate and connected to each other by conductors is formed. Here, for the high-frequency circuit, the ground conductor is formed at a position on the side face where the ground conductor and the conductor connecting the three-plate lines to each other have an optimum positional relationship. With this structure, it is possible to secure waveguides of different three-plate structures while saving space and maintaining circuit functions. Furthermore, the cut-outs formed in the surface of the intermediate ground conductor can be optimally dimensioned, thereby further saving space.
That is, according to the present embodiment, it is possible to provide a circuit structure body that has a small footprint and maintains good circuit characteristics, with a circuit structure including a plurality of planar conductors that have a three-plate structure in different layers of a multilayer substrate and are connected to each other by conductors.
Now, the advantages of the present invention will be described by taking a two-layer three-plate four-layer substrate in which three-plate lines are bonded to each other through a through-hole as an example.
Fig. 3 includes an explanatory view for explaining a circuit structure body for comparison with the present invention. In the interlayer connection circuit, interlayer connection is performed between the three board lines at a position near the center of the substrate by using a plurality of through holes.
As shown in fig. 3, when a multi-layered three-plate structure is provided, three-plate lines are connected to each other and an area around the connected portion of the three-plate lines is surrounded by other through holes. With this structure, the connection between the layers and the component configured to suppress energy loss can be incorporated into the circuit structure.
In this circuit configuration, the following problems can be pointed out: an appropriate distance between the area surrounded by the via hole and other circuit elements is required, and the formation of the via hole becomes more difficult as the number of layers increases. Further, when the number of layers is further increased, such a constraint that the wiring is inhibited from spreading with respect to the upper and lower layers may greatly affect the design. In other words, even in the case where the number of layers is increased, a problem of providing the efficiency of each circuit element in a small area while maintaining high-frequency characteristics can be pointed out.
Meanwhile, in the circuit structure according to the invention of the present application, the ground conductor provided to the wall surface of the multilayer substrate is formed so as to maintain the positional relationship of the surface substantially parallel to the interlayer connection conductor. As a result, space saving can be achieved while maintaining high frequency characteristics. In other words, when the circuit structures shown in fig. 1 and 2 and the circuit structure shown in fig. 3 are formed in a multilayer substrate while keeping the high-frequency characteristics the same, the circuit structures shown in fig. 1 and 2 can be designed in a more space-saving manner. In addition, the circuit structures shown in fig. 1 and 2 can contribute to reducing the number of through holes.
Hereinafter, examples of the size and number of through holes required for the circuit structures shown in fig. 1 and 2 and the circuit structure shown in fig. 3, which may have equivalent characteristics, are described in a comparative manner.
Size:
the circuit configuration of fig. 3: the center of the through hole is
(outermost diameter:
)
the circuit configuration of fig. 1: 3mm (in the vertical direction in FIG. 1(b) × 1.5mm (in the horizontal direction in FIG. 1 (b))
The circuit configuration of fig. 2: 3mm x 3mm
The number of through holes:
the circuit configuration of fig. 3: 7 (through hole diameter:
)
the circuit configuration of fig. 1: 0
The circuit configuration of fig. 2: 1
Fig. 4(a) is a graph of return loss characteristics, and fig. 4(b) is a graph of insertion loss characteristics obtained by simulating the characteristics of the circuit structure shown in fig. 1. The simulation condition was set to a circuit size of 15mm × 20mm and Δ S was 0.02.
In the characteristic diagram, the simulation result under the condition that the thickness of each layer is set to 0.762mm and the distance between the interlayer connection conductor 3 formed in the multilayer substrate and the ground conductor 2 on the side face is set to 0.765mm is shown. As shown in the characteristic diagram, good characteristics can be maintained.
Next, some possible modes of the present invention are exemplified.
In fig. 5, a modified example 1 of the circuit configuration of the present invention is shown.
The circuit structure shown in fig. 5(a) is a mode in which a three-layer three-plate structure is formed by further adding layers. The circuit structure shown in fig. 5(b) is a mode in which a four-layer three-plate structure is formed.
A plurality of planar conductors each in the shape of a strip are provided to different 3 layers or 4 layers of the multilayer substrate. Further, an interlayer connection conductor serving as an interlayer connection line connects planar conductors in 3 layers or 4 layers to each other. Each of the members is formed in a shape that realizes impedance matching according to a branching direction or a bonding direction of a desired high-frequency signal.
The present invention is effective for reducing the size even when the number of layers of the three-plate structure is further increased in this way. This structure can be used, for example, for branching and joining of high-frequency transmission paths available in phased array antennas.
Fig. 6 is a modified example 2 of the circuit configuration of the present invention.
In this circuit structure, two ground vias are formed on each side face side of the interlayer connection conductor 3. In this way, a circuit structure in which a desired number of through holes grounded to the side ground conductor 2 are provided around the interlayer connection conductor 3 can be adopted.
In addition, a shape may be adopted in which a via hole for grounding is provided around the interlayer connection conductor 3 together with the side ground conductor 2 instead of a through hole.
Fig. 7 is a modified example 3 of the circuit configuration of the present invention.
In this circuit configuration, the planar conductors serving as three-plate lines extend in different directions by layer. Circuit structures may be formed in this manner.
As described above, according to the present invention, it is possible to provide a circuit structure body having a circuit structure including a plurality of planar conductors which have a three-plate structure in different layers of a multilayer substrate and are connected to each other by conductors, which has a small footprint and maintains good circuit characteristics.
The specific configuration of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, each of the modification examples described above may be appropriately combined to be incorporated in a circuit configuration.
Further, part or all of the above embodiments may also be described as follows. The following supplementary description is not intended to limit the present invention.
[ supplementary notes 1]
A circuit structure body, comprising:
a multilayer substrate that serves as a multilayer three-plate structural body and has a ground conductor surface and a strip conductor in each layer;
an interlayer connection conductor serving as an interlayer connection line for connecting the strip conductors in different layers to each other; and
and a ground conductor formed on a side surface of the multilayer substrate close to the interlayer connection conductor, the ground conductor having a positional relationship substantially parallel to the interlayer connection conductor.
[ supplementary notes 2]
In the circuit structure according to the above supplementary note, the ground conductor surface excluding the portion corresponding to the interlayer connection conductor is formed on one layer sandwiched by the plurality of strip conductors of the multilayer substrate.
[ supplementary notes 3]
In the circuit structure according to the above supplementary note, the ground conductor surface excluding the portion corresponding to the interlayer connection conductor is formed on one layer sandwiched by the plurality of strip conductors of the multilayer substrate.
[ supplementary notes 4]
The circuit structure body as described in the above supplementary note, wherein a portion between the interlayer connection conductor and the ground conductor formed on the side of the multilayer substrate close to the interlayer connection conductor is formed of a dielectric different from the base material of the multilayer substrate.
[ supplementary notes 5]
The circuit structure body as described in the above supplementary note, wherein a portion between the interlayer connection conductor and the ground conductor formed on the side surface of the multilayer substrate close to the interlayer connection conductor is formed of a dielectric having a higher dielectric constant than that of the base material of the multilayer substrate.
[ supplementary notes 6]
The circuit structure body as described in the above supplementary note, wherein a portion between the interlayer connection conductor and the ground conductor formed on the side surface of the multilayer substrate close to the interlayer connection conductor is formed of a dielectric having a dielectric constant lower than that of the base material of the multilayer substrate.
[ supplementary notes 7]
As the circuit structure body described in the above supplementary explanation,
wherein a portion formed between the interlayer connection conductor and a ground conductor formed on a side of the multilayer substrate close to the interlayer connection conductor is formed of a dielectric different from a base material of the multilayer substrate,
wherein a distance between the ground conductor and the interlayer connection conductor formed on the side surface of the multilayer substrate is set to a distance that achieves approximately equal distance and permittivity between the ground conductor and the strip conductor having a three-plate structure formed in the multilayer substrate, with the permittivity of a dielectric different from the base material of the multilayer substrate as a coefficient.
The present invention can be applied to a multilayer substrate or a multilayer substrate having a large number of layers, which requires space saving when forming a high-frequency circuit structure.
This application claims priority from Japanese patent application No.2015-166912, filed on 26.8.2015, the entire disclosure of which is incorporated herein by reference.
Description of the reference numerals
1, 1' multilayer substrate
2 side ground conductor
3 interlayer connection conductor
4 multiple plane conductors
Claims (7)
1. A circuit structure body, comprising:
a multilayer substrate including a plurality of layers of first to N-th three-plate structural bodies each including first to N-th planar conductors, wherein N is an integer of 2 or more;
an interlayer connection conductor configured to connect the first to Nth plane conductors to each other; and
a side ground conductor formed on a side surface of the multilayer substrate arranged near the interlayer connection conductor of the multilayer substrate and substantially parallel to the interlayer connection conductor,
wherein the nth three-plate structural body is formed by nth three-plate lines, wherein N is more than or equal to 1 and less than or equal to N, and the nth three-plate lines comprise:
an nth planar conductor; and an nth planar ground conductor and an n +1 th planar ground conductor sandwiching the nth planar conductor therebetween,
wherein an m-th planar ground conductor disposed between the first to N-th planar conductors has a cutout allowing the interlayer connection conductor to pass therethrough, wherein m is 2. ltoreq. N, one side surface of the cutout is in contact with the side surface ground conductor,
wherein the circuit structure body operates the interlayer connection conductor and the side ground conductor as a high-frequency circuit.
2. The circuit structure body according to claim 1, wherein the interlayer connection conductor is formed of a planar conductor.
3. The circuit structure body according to claim 1, wherein the interlayer connection conductor is formed of a through hole.
4. The circuit structure body according to claim 1, wherein a distance between the side ground conductor and the interlayer connection conductor formed on the side of the multilayer substrate is: a distance less than half of a distance between an intermediate ground conductor surface and a surface ground conductor surface formed in the multilayer substrate.
5. The circuit structure body according to any one of claims 1, 2, 3 and 4,
wherein the first to Nth planar conductors each serving as a strip line are provided to different three layers of the multilayer substrate,
wherein the interlayer connection conductors serving as interlayer connection lines are configured to connect the first to Nth plane conductors in the different three layers to each other, and
wherein a portion between the interlayer connection conductor and the side ground conductor operates as a transmission line for high-frequency signals.
6. The circuit structure body according to any one of claims 1, 2, 3 and 4,
wherein the interlayer connection conductor connects the first to Nth planar conductors extending from the same side as the side ground conductor,
wherein the interlayer connection conductor and the side ground conductor operate as a transmission line for high-frequency signals, the transmission line being continuous from a parallel plate transmission line formed in the three-plate structural body.
7. The circuit structure body according to any one of claims 1, 2, 3 and 4,
wherein a portion between the interlayer connection conductor and the side ground conductor of the multilayer substrate is formed of a dielectric,
wherein the side surface ground conductor is formed to have at least a size large enough to cover a projected portion formed when the interlayer connection conductor is projected onto the side surface.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015-166912 | 2015-08-26 | ||
| JP2015166912A JP6222747B2 (en) | 2015-08-26 | 2015-08-26 | Circuit structure |
| PCT/JP2016/003753 WO2017033434A1 (en) | 2015-08-26 | 2016-08-17 | Circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107926112A CN107926112A (en) | 2018-04-17 |
| CN107926112B true CN107926112B (en) | 2021-03-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680048905.3A Active CN107926112B (en) | 2015-08-26 | 2016-08-17 | Circuit structure |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11018404B2 (en) |
| EP (1) | EP3344019B1 (en) |
| JP (1) | JP6222747B2 (en) |
| CN (1) | CN107926112B (en) |
| WO (1) | WO2017033434A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022128024A (en) | 2021-02-22 | 2022-09-01 | 株式会社東芝 | Substrate, high-frequency circuit, antenna device, wireless communication device, and method for manufacturing substrate |
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| JP2001189609A (en) | 1999-12-28 | 2001-07-10 | Mitsubishi Electric Corp | Microstrip line connector |
| JP2001313505A (en) * | 2000-05-01 | 2001-11-09 | Mitsubishi Electric Corp | Power distributor |
| JP2004259959A (en) * | 2003-02-26 | 2004-09-16 | Kyocera Corp | Wiring board |
| JP2006246189A (en) * | 2005-03-04 | 2006-09-14 | Mitsubishi Electric Corp | Strip line connecting structure |
| JP5126625B2 (en) | 2007-03-02 | 2013-01-23 | 日本電気株式会社 | Compact filtering structure |
| JP2013005296A (en) | 2011-06-17 | 2013-01-07 | Hitachi Chem Co Ltd | Line interlayer connector, planar array antenna having line interlayer connector and planar array antenna module |
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| KR20150095092A (en) * | 2014-02-12 | 2015-08-20 | 한국전자통신연구원 | Board assembly for transmitting high speed signal and method of manufacturing the same |
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2015
- 2015-08-26 JP JP2015166912A patent/JP6222747B2/en active Active
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2016
- 2016-08-17 CN CN201680048905.3A patent/CN107926112B/en active Active
- 2016-08-17 US US15/746,876 patent/US11018404B2/en active Active
- 2016-08-17 WO PCT/JP2016/003753 patent/WO2017033434A1/en active Search and Examination
- 2016-08-17 EP EP16838785.0A patent/EP3344019B1/en active Active
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| JPH04802A (en) * | 1990-04-17 | 1992-01-06 | Mitsubishi Electric Corp | Triplate line type inter-substrate connecting element |
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| JP2002100901A (en) * | 2000-09-25 | 2002-04-05 | Mitsubishi Electric Corp | Multilayer planar waveguide |
| JP2003168903A (en) * | 2001-12-03 | 2003-06-13 | Mitsubishi Electric Corp | Structure for connecting strip lines |
| JP2004087563A (en) * | 2002-08-23 | 2004-03-18 | Nec Engineering Ltd | Multilayer board and semiconductor device |
| JP2009111658A (en) * | 2007-10-30 | 2009-05-21 | Kyocera Corp | Multilayer wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017045847A (en) | 2017-03-02 |
| EP3344019A4 (en) | 2019-04-17 |
| WO2017033434A1 (en) | 2017-03-02 |
| CN107926112A (en) | 2018-04-17 |
| US11018404B2 (en) | 2021-05-25 |
| JP6222747B2 (en) | 2017-11-01 |
| US20200112076A1 (en) | 2020-04-09 |
| EP3344019B1 (en) | 2021-06-16 |
| EP3344019A1 (en) | 2018-07-04 |
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