CN107919155A - A kind of non-volatile three-state content addressing memory and its addressing method - Google Patents

Abstract

The invention relates to the field of embedded control, and discloses a non-volatile tri-state content addressable memory and its addressing method. The memory includes: a search line, a matching line, a complementary search line and a plurality of storage units. The unit includes a first storage resistor and a second storage resistor, the first end of the first storage resistor is connected to the search line, the second end of the first storage resistor is connected to the matching line, and the second The first end of the storage resistor is connected to the complementary search line, and the second end of the second storage resistor is connected to the matching line. The non-volatile three-state content addressable memory and its addressing method provided by the invention have the characteristics of high storage density and high reliability.

Description

A non-volatile tri-state content addressable memory and its addressing method

technical field

The invention relates to the field of embedded control, in particular to a non-volatile three-state content addressable memory and its realization method.

Background technique

In the era of big data and cloud computing, with the popularization of various smart devices, a large amount of data is generated, and it also needs to be transmitted by the network. In order to improve the efficiency and security of data transmission, it becomes very necessary to screen data in routers. The traditional software-based screening method mainly relies on multiple access and comparison operations between the CPU (Central Processing Unit) and the main memory, and the time cost and power consumption cost are relatively large. TCAM (ternary content addressable memory, ternary content addressable memory), as a hardware-level solution, can realize fast and efficient search and matching through parallel comparison, and better solve the problems existing in traditional software implementation methods.

The fast lookup and matching of TCAM is often at the cost of increasing chip area and power consumption. The traditional TCAM design is based on SRAM (Static Random Access Memory). A single TCAM unit often requires 12-16 transistors. The large unit area makes it difficult to increase the storage density of TCAM. At the same time, the large area also leads to large parasitic capacitance. Cause dynamic (active) power consumption is bigger. In addition, the traditional TCAM inherits the volatile characteristic of SRAM, and the power supply cannot be cut off in the static (standby) mode, otherwise the stored information will be lost. This characteristic also leads to a large static power consumption.

Aiming at the problems existing in traditional TCAM, a current research hotspot is how to realize high-density non-volatile TCAM based on a new type of non-volatile memory. Internationally, well-known research institutions including IBM, NEC and Tohoku University, TSMC and Tsinghua University in Taiwan, etc. are the flagship conferences in the field of integrated circuits ISSCC (International Solid State Integrated Circuits Conference) and Symposium onVLSI Circuits (VLSIC, Large-Scale Integrated Circuits Symposium ) from 2011 to 2016 reported the relevant achievements of non-volatile TCAM for six consecutive years. Compared with traditional TCAM, the existing non-volatile TCAM has the advantages of smaller unit area and low static power consumption. First of all, the number of transistors in the TCAM unit is reduced to 2-6, which greatly reduces the area of the TCAM unit. Secondly, the non-volatile characteristics of the new memory allow the TCAM to be completely powered off in the dormant state without worrying about information loss, which is beneficial to Reduced static power consumption. However, there are still some problems in the existing non-volatile TCAM scheme, mainly in:

The storage window between "0" and "1" signals is small. For non-volatile TCAM based on MRAM, because MRAM itself has a small Roff/Ron (Ron is low resistance, Roff is high resistance) and is susceptible to fluctuations , resulting in a small storage window between the “0” and “1” signals in the corresponding nonvolatile TCAM. For RRAM-based non-volatile TCAM, because it mainly relies on the voltage division between the RRAM storage resistor and the transistor to obtain "0" or "1", and the transistor and the RRAM storage resistor fluctuate greatly when the size is small, and the fluctuation rules are inconsistent , causing the resulting storage window between "0" and "1" signals to be susceptible to fluctuations and deteriorate.

The area of the TCAM unit is still relatively large, and the area of the smallest non-volatile TCAM unit is still 50F2 (F is the characteristic size of each process generation). Since the existing non-volatile TCAM unit still needs the assistance of a transistor to realize the TCAM function, and the transistor needs to be fabricated on the CMOS front-end process, this will expand the area of the TCAM unit on the one hand, and limit the three-dimensional (3D) of the TCAM unit on the other hand. ) is not conducive to the possibility of 3D integration of RRAM.

Contents of the invention

The object of the present invention is to provide a non-volatile three-state content addressable memory with high storage density and strong reliability and its addressing method.

To achieve the above object, the present invention provides the following technical solutions:

A non-volatile three-state content addressable memory, the memory includes: a search line, a match line, a complementary search line and a plurality of storage units, the storage unit includes a first storage resistor and a second storage resistor, the first The first end of a storage resistor is connected to the search line, the second end of the first storage resistor is connected to the matching line, and the first end of the second storage resistor is connected to the complementary search line, so The second end of the second storage resistor is connected to the matching line.

Optionally, the storage unit further includes a first current limiting device and a second current limiting device, the first end of the first storage resistor is connected in series with the first current limiting device and then connected to the search line, The first end of the second storage resistor is connected in series with the second current limiting device and then connected to the complementary search line.

Optionally, the plurality of storage units are arranged in an array, the storage units located in the same row share a matching line, the storage units not located in the same row do not share a matching line, and the storage units located in the same column do not share a matching line. The storage units share a search line and a complementary search line, the storage units not located in the same column do not share the same search line, and the storage units not located in the same column do not share the same complementary search line.

Optionally, the memory also includes:

A matching line driving circuit, the matching line driving circuit is connected to the matching line, and the matching line driving circuit is used to generate a set voltage;

A search line drive circuit, the search line drive circuit is respectively connected to the search line and the complementary search line, and the search line drive circuit is used to generate a reset voltage;

A match line sense amplifier, the match line sense amplifier is connected to the match line, and the match line sense amplifier is used to amplify and output the match signal.

The present invention also provides an addressing method applied to the above-mentioned non-volatile tri-state content addressable memory, wherein the output end of the matching line is connected to the input end of the sense amplifier, and the method includes:

obtaining a search signal, the search signal including "1", "0" and "X";

judging whether the search signal is "1";

If yes, charge the match line and search line to the precharge voltage, and keep the complementary search line low;

If not, then judging whether the search signal is "0";

If the search signal is "0", precharge the matching line and the complementary search line to a high level, and keep the search line at a low level;

If the search signal is not "0", then judge whether the search signal is "X";

if the search signal is "X", precharging the search line, the match line and the complementary search line to a high level;

obtaining the voltage at the output terminal of the matching line;

Judging whether the output voltage is greater than a reference voltage, the value of the reference voltage is a set value, the set value is a level value between the high level VH2 and the low level VL2, and the high level VH2 is When the signal matches the storage information of the storage unit, the level value of the matching line after discharge in the discharge phase, the low level VL2 is the difference between the signal and the storage information of the storage unit When matching, the level value of the matching line after discharge in the discharge phase;

If yes, output "1";

If not, output "0".

According to the specific embodiment provided by the present invention, the present invention discloses the following technical effects: the non-volatile three-state content addressable memory provided by the present invention adopts devices that can be integrated in the complementary metal oxide semiconductor CMOS back-end process to construct the storage unit , does not contain transistors that need to be integrated in the CMOS front-end process. On the one hand, it reduces the volume of the memory unit and increases the storage density of the memory. On the other hand, it makes the 3D integration of the memory possible. Moreover, when the present invention is searching for information, the matching line driving circuit is used to charge the matching line to the precharge voltage, and the searching line driving circuit is used to reset the voltages of the searching line and the complementary searching line, that is, "0" and "1" "The signal is not obtained through the voltage division of the transistor, which avoids the problem of a small storage window between the "0" and "1" signals caused by the voltage division of the transistor, and improves the reliability of the memory.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some of the present invention. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without paying creative labor.

FIG. 1 is a schematic structural diagram of a storage unit of a non-volatile tri-state content addressable memory according to a first embodiment of the present invention;

2 is a schematic structural diagram of a storage unit of a non-volatile tri-state content addressable memory according to a second embodiment of the present invention;

3 is a schematic structural diagram of a non-volatile tri-state content addressable memory according to the first embodiment of the present invention;

4 is a schematic structural diagram of a non-volatile tri-state content addressable memory according to a second embodiment of the present invention;

Fig. 5 is a schematic flow chart of the addressing method of the non-volatile three-state content addressable memory of the present invention;

FIG. 6 is a schematic diagram of charging and discharging of the non-volatile tri-state content addressable memory in addressing according to the first embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The object of the present invention is to provide a non-volatile three-state content addressable memory with high storage density and strong reliability and its addressing method.

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 is a schematic structural diagram of a nonvolatile three-state content addressable memory according to the first embodiment of the present invention. As shown in FIG. 1, the nonvolatile three-state content addressable memory includes: search lines 107, 109, match lines 102, 103, complementary search lines 106, 108, match line drive circuit 110, search line drive circuit 101, multiple match line sense amplifiers 104, 105 and multiple storage units 111, the multiple storage units are arranged in an array, located at The memory cells in the same row share a matching line, the memory cells not in the same row do not share a matching line, the memory cells in the same column share a search line and a complementary search line, and are not in the same column The memory cells above do not share the same search line, and the memory cells not located in the same column do not share the same complementary search line; the match line sense amplifier is connected to the match line one by one, and the output end of the match line is connected to the match line The input terminals of the match line sense amplifier are connected, and the match line sense amplifier is used to compare the output voltage of the match line with the reference voltage Vref1, and amplify and output the comparison result; the match line drive circuit 110 is connected to the The matching lines are connected, and the matching line driving circuit 110 is used to generate a set voltage; the search line driving circuit 101 is respectively connected to the search line and the complementary search line, and the search line driving circuit 101 is used to generate a reset Voltage. FIG. 2 is a schematic structural diagram of a storage unit of a nonvolatile three-state content addressable memory according to the first embodiment of the present invention. As shown in FIG. 2 , the storage unit includes a first storage resistor 204 and a second storage resistor 207, so The first terminal 206 of the first storage resistor 204 is connected to the search line 202, the second terminal 205 of the first storage resistor 204 is connected to the matching line 201, and the first terminal of the second storage resistor 207 209 is connected to the complementary search line 203 , and the second end 208 of the second storage resistor 207 is connected to the matching line 201 .

Fig. 3 is a schematic structural diagram of the storage unit of the non-volatile tri-state content addressable memory according to the second embodiment of the present invention. As shown in Fig. 3, the second embodiment of the non-volatile tri-state content-addressable memory provided by the present invention In the storage unit, the first terminal 303 of the first storage resistor 302 in the storage unit is connected in series with the first current limiting device 304 and then connected to the search line 305, and the first terminal 308 of the second storage resistor 306 is connected to the second The current limiting device 309 is connected in series with the complementary search line 310 , the second terminal 303 of the first storage resistor 302 is connected to the matching line 301 , and the second terminal 307 of the second storage resistor 306 is connected to the matching line 301 . FIG. 4 is a schematic structural diagram of a nonvolatile three-state content addressable memory according to a second embodiment of the present invention. As shown in FIG. 4 , the storage unit 411 of the nonvolatile three-state content addressable memory in this embodiment has The storage unit of the device, other elements and connection relationship are the same as the non-volatile tri-state content addressable memory in the first embodiment, and the non-volatile tri-state content-addressable memory includes search lines 407, 409, matching lines 402, 403 , complementary search lines 406, 408, match line drive circuit 410, search line drive circuit 401, multiple match line sense amplifiers 404, 405 and multiple memory cells 411.

The non-volatile tri-state content addressable memory provided by the present invention is constructed by devices such as resistive variable memory RRAM that can be integrated in the back-end process, and does not use transistors and other devices manufactured in the front-end of the complementary metal oxide semiconductor CMOS process , the volume of the storage unit is reduced, and the storage density of the memory is increased. At the same time, the non-volatile tri-state content addressable memory provided by the present invention no longer uses the traditional transistor voltage division method to obtain "1" and "0". The storage window avoids the problem of large fluctuations and instability in the "1" and "0" windows, and enhances the reliability of information storage.

Fig. 5 is a schematic flow chart of the addressing method of the non-volatile three-state content addressable memory of the present invention, as shown in Fig. 5, the steps of the addressing method are as follows:

Step 501: Obtain a search signal, the search signal includes "1", "0" and "X", and "1", "0" and "X" are logic values;

Step 502: judging whether the search signal is "1";

Step 503: If the search signal is "1", the match line drive circuit charges the match line to the pre-charge voltage, the search line drive circuit charges the search line to the pre-charge voltage, and the complementary search line remains low. For this For the storage unit without a current limiting device in the first embodiment of the invention, the precharge voltage is generally the power supply voltage; for the storage unit containing the current limiting device in the second embodiment of the present invention, the precharge voltage is generally the power supply voltage voltage and the sum of the conduction voltage of the current limiting device. Afterwards, the memory enters the discharge phase. FIG. 6 is a schematic diagram of charging and discharging of the non-volatile three-state content addressable memory in the first embodiment of the present invention when addressing. As shown in FIG. 6, when searching for "1", if the stored If the logic value stored in the cell is "1", then the memory cell has only a high-impedance discharge path to the matching line. When other memory cells in the same row also match, the matching line ML will only discharge to a higher level VH1. Since the storage resistor between the matching line ML and the search line SL is in a low-resistance state, the search line SL will also discharge to a higher level along with the matching line ML, as shown by the solid line 607 in FIG. 6; if the storage The logic value stored in the cell is "0", and the memory cell will have a low-impedance discharge path to the matching line ML, and the matching line ML will be discharged to a lower level VL1, as shown by the dotted line 608 in FIG. 6 , the search line SL The storage resistor between the matching line ML and the matching line ML is in a high-impedance state, and the search line SL will be discharged to a higher level;

Step 504: If the search signal is not "1", then judge whether the search signal is "0";

Step 505: If the search signal is "0", precharge the matching line and the complementary search line to a high level, and keep the search line at a low level, and then enter the discharge comparison stage, as shown in FIG. 6 , in When searching for "0", if the logic value stored in the storage unit is "0", then the storage unit has only a high-impedance discharge path to the matching line ML. It will only be discharged to a higher level VH1, as shown by the solid line 604 in Figure 6, since the storage resistor between the matching line ML and the complementary search line SLB is in a low resistance state, the complementary search line SLB will also follow the matching line ML is discharged to a higher level; if the logic value stored in the memory cell is "1", the memory cell will have a low-impedance discharge path to the matching line ML, and the matching line ML will be discharged to a lower level VL1, as shown in Figure 6 As shown by the dotted line 605 in , the storage resistor between the complementary search line SLB and the matching line ML is in a high-impedance state, and the complementary search line SLB will be discharged to a higher level;

Step 506: If the search signal is not "0", then judge whether the search signal is "X";

Step 507: If the search signal is "X", precharge the search line, match line and complementary search line to a high level, and then enter the discharge comparison stage, as shown in FIG. 6 , regardless of the storage unit Whether the stored logic value is "1" or "0", the storage unit will not discharge the matching line;

Step 508: Obtain the voltage at the output terminal of the matching line;

Step 509: judging whether the output voltage is greater than a reference voltage, the value of the reference voltage is a set value, and the set value is a level value between the high level VH2 and the low level VL2, As shown by the dotted line 611 in FIG. 6;

Step 510: If the output voltage is greater than the reference voltage, the sense amplifier connected to the matching line outputs "1", which means that the stored information of the memory unit matches the search information, and the sense amplifier is a comparison amplifier;

Step 511: If the output voltage is less than or equal to the reference voltage, the sense amplifier connected to the matching line outputs "0", which means that the stored information of the memory unit does not match the search information.

The pre-charging voltage in the present invention is generally the power supply voltage in the first embodiment provided by the present invention, and is the sum of the power supply voltage and the conduction voltage of the current limiting device in the second embodiment.

Wherein, the truth table stored in the storage unit in the first embodiment is shown in Table 1, and the truth table stored in the storage unit in the first embodiment is shown in Table 2.

Table I

Storing data The first memory resistance (RRAM resistance) Second storage resistor (RRAM resistor) 0 HRS (high resistance state) LRS (low resistance state) 1 LRS (low resistance state) HRS (high resistance state) x HRS (high resistance state) HRS (high resistance state)

Table II

Storing data The first memory resistance (RRAM resistance) Second storage resistor (RRAM resistor) 0 HRS (high resistance state) LRS (low resistance state) 1 LRS (low resistance state) HRS (high resistance state) x HRS (high resistance state) HRS (high resistance state)

The writing operation of the non-volatile tri-state content addressable memory provided by the present invention adopts the method of applying excitation, which is divided into two steps, first writing the left resistance, and then writing the right resistance. The excitation application method is similar to the writing operation of the crossbar architecture, which can be Use VPP/2 or VPP/3 algorithm. VSET is the set (set) voltage; VRESET is the reset (reset) voltage, and VT is the conduction voltage of the current-limiting device. The VSET and VRESET voltages are generated by the ML drive circuit 201 and the SL drive circuit 204. The VPP/2 algorithm applied excitation method for the write operation of the non-volatile tri-state content addressable memory provided by the first embodiment is shown in Table 3, VPP/ 3. The incentive method for applying the algorithm is shown in Table 4. The incentive method for applying the VPP/2 algorithm for the write operation of the non-volatile three-state content addressable memory provided by the second embodiment is shown in Table 5. The incentive method for applying the VPP/3 algorithm As shown in Table 6.

The non-volatile tri-state content addressable memory provided by the present invention adopts the drive circuit to set, reset and charge when performing write operations and searching information, and no longer uses the traditional transistor voltage division method to obtain "1" and "0" The storage window avoids the problem of large fluctuations and instability in the "1" and "0" windows, and enhances the reliability of information storage.

Table three

Table four

Table five

Table six

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

In this paper, specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; meanwhile, for those of ordinary skill in the art, according to the present invention Thoughts, there will be changes in specific implementation methods and application ranges. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (5)

1. A non-volatile tri-state content addressable memory, characterized in that the memory comprises: a search line, a match line, a complementary search line and a plurality of storage units, and the storage unit comprises a first storage resistor and a second storage resistor A storage resistor, the first end of the first storage resistor is connected to the search line, the second end of the first storage resistor is connected to the matching line, the first end of the second storage resistor is connected to the The complementary search line is connected, and the second end of the second storage resistor is connected to the matching line. 2. The non-volatile tri-state content addressable memory according to claim 1, wherein the storage unit further comprises a first current limiting device and a second current limiting device, and the first storage resistance of the first The terminal is connected in series with the first current limiting device and then connected to the search line, and the first terminal of the second storage resistor is connected in series with the second current limiting device and then connected to the complementary search line. 3. The non-volatile tri-state content addressable memory according to claim 1 or 2, wherein the plurality of storage units are arranged in an array, and the storage units located in the same row share a matching line , the storage units located in different rows occupy different matching lines, the storage units located in the same column share a search line and a complementary search line, and the storage units located in different columns occupy different search lines, and The memory cells located on different columns occupy different complementary search lines. 4. The non-volatile tri-state content addressable memory according to claim 1 or 2, wherein the memory further comprises: A matching line driving circuit, the matching line driving circuit is connected to the matching line, and the matching line driving circuit is used to generate a set voltage; A search line drive circuit, the search line drive circuit is respectively connected to the search line and the complementary search line, and the search line drive circuit is used to generate a reset voltage; A match line sense amplifier, the match line sense amplifier is connected to the match line, and the match line sense amplifier is used to amplify and output the match signal. 5. An addressing method for a non-volatile three-state content-addressable memory, characterized in that, the method is applied to the matching of the non-volatile three-state content-addressable memory as described in claim 1 or 2. The output end of line is connected with the input end of sense amplifier, and described method comprises: obtaining a search signal, the search signal including "1", "0" and "X"; judging whether the search signal is "1"; If yes, charge the match line and search line to the precharge voltage, and keep the complementary search line low; If not, then judging whether the search signal is "0"; If the search signal is "0", precharge the matching line and the complementary search line to a high level, and keep the search line at a low level; If the search signal is not "0", then judge whether the search signal is "X"; if the search signal is "X", precharging the search line, the match line and the complementary search line to a high level; obtaining the voltage at the output end of the matching line; Judging whether the output voltage is greater than a reference voltage, the value of the reference voltage is a set value, the set value is less than the high level VH2 and greater than the low level VL2, and the high level VH2 is the signal When matching with the storage information of the storage unit, the level value of the match line after discharge in the discharge phase, the low level VL2 is when the signal does not match the storage information of the storage unit, the match line The level value after discharge in the discharge phase; If yes, output "1"; If not, output "0".