CN107896098A - A kind of pulse per second (PPS) gate controller and control method - Google Patents
A kind of pulse per second (PPS) gate controller and control method Download PDFInfo
- Publication number
- CN107896098A CN107896098A CN201610868881.8A CN201610868881A CN107896098A CN 107896098 A CN107896098 A CN 107896098A CN 201610868881 A CN201610868881 A CN 201610868881A CN 107896098 A CN107896098 A CN 107896098A
- Authority
- CN
- China
- Prior art keywords
- signal
- voltage
- frequency
- vcxo
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention relates to a kind of pulse per second (PPS) gate controller and control method, including VXCO modules, in addition to gps signal receiver, accumulation of phase module, DDS frequency division modules, voltage-controlled correcting module and servo module；The present invention is used as synchronous reference signal by introducing gps signal, and reference signal is synchronized in the pulse signal width of T=1 second and carries out accumulation of phase calculating with fractional frequency signal, and direct current correction voltage is finally counted to obtain by phase difference, pass through byVoltage-controlled amendment is carried out to VCXO modules after being combined with the initial correction voltage V0 measured by servo module, improves the rate-adaptive pacemaker precision of VCXO modules.
Description
Technical field
The present invention relates to Technology of Atomic Frequency Standards field, and in particular to a kind of pulse per second (PPS) gate controller and control method.
Background technology
In inactive type rubidium atom frequency scale, quantized system is the core component of whole atomic frequency standard, and it is steady that it provides a frequency
Atomic resonance Absorption Line fixed, line width is narrower.After comprehensive modulate, voltage-controlled quartz oscillator is come from caused by electronic circuit
（VCXO）Band modulation microwave interrogation signals act on quantized system, after quantum frequency discrimination, by servo circuit to quantum reflect
The processing of frequency information, most the output frequency of local oscillator is locked in the hyperfine 0-0 transition centers frequency of ground state of rubidium atom at last.
Existing most of servo circuits synchronize phase demodulation to quantum frequency discrimination signal according to the comprehensive synchronous phase discrimination signal provided, and according to
Identified result information realizes that the closed loop of complete machine locks by the way of the independent voltage-controlled local oscillators of D/A, is exported eventually through local oscillator
The higher frequency signal of stability.The popularization of GPS synchronous calibrations, it is that there is provided a new stage to existing atomic clock,
We completely can be synchronous with GPS by the longtime running index of atomic clock, and short run target retains prior art, thus can be with
Avoid the output signal frequency change brought due to complete machine drift caused by internal system reason.
The content of the invention
The technical problem to be solved in the present invention is：It is proposed a kind of second that can improve VCXO output frequency precisions and stability
Pulse gate control device and control method.
The technical scheme that the present invention proposes for solution above-mentioned technical problem（One）It is：A kind of pulse per second (PPS) gate controller,
Including VXCO modules, in addition to gps signal receiver, accumulation of phase module, DDS frequency division modules, voltage-controlled correcting module and servo
Module；
The gps signal receiver is suitable to receive gps signal and its signal output part is connected to the letter of the accumulation of phase module
Number input；
The signal input part of the DDS frequency division modules is connected to the signal output part of the VXCO modules, the DDS frequency division modules
Signal output part be connected to the signal input part of the accumulation of phase module；
The signal output part of the accumulation of phase module is connected to the signal input part of the servo module, the accumulation of phase mould
Block is suitable to calculate the synchronous reference signal from gps signal receiver and the phase between VCXO fractional frequency signal by accumulating
Potential difference, and phase difference is converted into difference on the frequency, then difference on the frequency is converted into direct current correction voltage by voltage-controlled Slope relationship, finally
By direct current correction voltage output to servo module；
The quantized system that is acted on the VCXO modules of the servo module being suitable to is detected in terms of to obtain initial correction voltage,
Voltage-controlled amendment is carried out to VCXO modules by voltage-controlled correcting module after initial correction voltage combination direct current rectifies a deviation voltage again.
The technical scheme that the present invention proposes for solution above-mentioned technical problem（Two）It is：A kind of pulse per second (PPS) gate control method,
Including following characteristics step：
A, GPS second pulse signal f0, the GPS second arteries and veins are obtained after obtaining gps satellite signal and converted processing by receiver
The frequency for rushing signal strobe f0 is that 1Hz i.e. width is T=1 second, and the same of 1KHZ is produced based on the GPS second pulse gate signal f0
Reference signal f1 is walked, the signal f0 and signal f1 are delivered in accumulation of phase module；
B, VCXO output signal is obtained into fractional frequency signal f2 after DDS is divided and delivered in accumulation of phase module；
C, when GPS second pulse gate signal f0 is in high level, the phase difference for starting the signal f1 and fractional frequency signal f2 is accumulated
Calculate, and record the concrete numerical value of the signal f1 and signal f2 phase difference；
D, in the sampling by M T=1 second andWhen=0, the phase data obtained in the M*T times is converted into described in correspondence
Signal f1 and signal f2 frequency difference value；
E, according to default VCXO voltage-controlled slope value by frequency difference valueTransform into direct current correction magnitude of voltage；
F, by voltage-controlled correcting module according to formulaVoltage-controlled amendment, V are carried out to the VCXO0It is defeated for servo module
The magnitude of voltage of voltage-controlled correcting module is delivered to, V is the correction voltage for actually directly acting on VCXO.
Further, in addition to step g, the peak of the setting VCXO output frequencies and minimum are respectively
And corresponding magnitude of voltage upper and lower limit V1, V2 are recorded, judge that the correction voltage V and described magnitude of voltage V1, V2's is big
Small relation, as the V>V1 or V<During V2, the V=V0；As the V2<V<It is described during V1。
Further, in addition to step h, set VCXO voltage-controlled slope value a, pass through a*=b, b are daily VCXO's
Aging drift data, by b compensation to VCXO because in frequency change caused by aging drift.
Further, the fractional frequency signal f2 has similar coarse frequency value with the synchronous reference signal f1 frequencies.
Further, when carrying out DDS scaling down processings to fractional frequency signal f2 in the step b, the DDS that uses for
AD9852, the frequency dividing numerical value of DDS communications is determined by its technical manual, with reference to formula：
Wherein, F is by walking the coarse frequency value of measured signal that hour counter counts, single-chip microcomputer computing obtains, f 1KHz；
The frequency dividing numerical value is write into DDS buffer areas, 1KHz frequency signal is obtained after DDS, by the frequency signal of gained again
Final 1KHz frequency signals output is obtained after delivering to low-pass filtering module.
Further, in the step c, when GPS second pulse gate signal f0 is in high level, after the t1 times,
The rising edge of VCXO first pulse of fractional frequency signal f2, makes accumulation of phase effective, after the T seconds, GPS second pulse gate high level
When arriving again, after the t2 times, when then and the fractional frequency signal f2 rising edge that arrives arrive when, i.e. moment reference signal
The phase difference accumulation calculating process of f1 and VCXO fractional frequency signals is continued for.
The beneficial effects of the invention are as follows：
The present invention is used as synchronous reference signal by introducing gps signal, and reference is synchronized in the pulse signal width of T=1 second
Signal carries out accumulation of phase calculating with fractional frequency signal, and direct current correction voltage is finally counted to obtain by phase difference, pass through by
Voltage-controlled amendment is carried out to VCXO modules after being combined with the initial correction voltage V0 measured by servo module, improves VCXO modules
Rate-adaptive pacemaker precision.
It is noted that when phase accumulation calculates, by being set in phase after the t1 times in pulse per second (PPS) time gate
Position accumulation is effective and accumulation of phase calculating is still provided within the t2 times outside pulse per second (PPS) time gate so that accumulation of phase calculates
As a result with actually more conforming to, amendment precision is further improved.
Brief description of the drawings
The pulse per second (PPS) gate controller and control method of the present invention are described further below in conjunction with the accompanying drawings.
Fig. 1 is the structured flowchart of pulse per second (PPS) gate controller in the present invention；
Fig. 2 is the schematic diagram handled fractional frequency signal f2；
Fig. 3 is to calculate schematic diagram in accumulation of phase；
Fig. 4 is the scope adjustment schematic diagram of VCXO output frequencies.
Embodiment
Embodiment
According to Fig. 1, the pulse per second (PPS) gate controller in the present invention, including VXCO modules, in addition to gps signal connects
Receipts machine, accumulation of phase module, DDS frequency division modules, voltage-controlled correcting module and servo module.
Gps signal receiver be suitable to receive gps signal and its signal output part be connected to accumulation of phase module signal it is defeated
Enter end.
The signal input part of DDS frequency division modules is connected to the signal output part of VXCO modules, and the signal of DDS frequency division modules is defeated
Go out the signal input part that end is connected to accumulation of phase module.
The signal output part of accumulation of phase module is connected to the signal input part of servo module, and accumulation of phase module is suitable to logical
The phase difference crossed between accumulation synchronous reference signal of the calculating from gps signal receiver and the fractional frequency signal from VCXO, and
Phase difference is converted into difference on the frequency, then difference on the frequency is converted into direct current by voltage-controlled Slope relationship and rectified a deviation voltage, most direct current at last
Voltage output of rectifying a deviation is to servo module.
The quantized system that is acted on VCXO modules of servo module being suitable to is detected in terms of to obtain initial correction voltage, then
Voltage-controlled amendment is carried out to VCXO modules by voltage-controlled correcting module after initial correction voltage combination direct current correction voltage.
The pulse per second (PPS) gate control method carried out in above-mentioned control device, comprises the following steps：
A, GPS second pulse signal f0, GPS second pulse lock are obtained after obtaining gps satellite signal and converted processing by receiver
Gate signal f0 frequency is that 1Hz i.e. width is T=1 second, and 1KHZ reference synchronization letter is produced based on GPS second pulse gate signal f0
Number f1, signal f0 and signal f1 are delivered in accumulation of phase module；
B, VCXO output signal is obtained into fractional frequency signal f2 after DDS is divided and delivered in accumulation of phase module；
C, as shown in figure 3, when GPS second pulse gate signal f0 is in high level, commencing signal f1 and fractional frequency signal f2 phase
Difference accumulation calculates, and the concrete numerical value of tracer signal f1 and signal f2 phase difference；
D, in the sampling by M T=1 second andWhen=0, the phase data obtained in the M*T times is converted into induction signal
F1 and signal f2 frequency difference value；
E, according to default VCXO voltage-controlled slope value by frequency difference valueTransform into direct current correction magnitude of voltage；
F, by voltage-controlled correcting module according to formulaVoltage-controlled amendment, V are carried out to VCXO0It is delivered to for servo module
The magnitude of voltage of voltage-controlled correcting module, V are the correction voltage for actually directly acting on VCXO.
It can be used as preferably：As shown in figure 4, also include step g, the peak of VCXO output frequencies and minimum is set
Value is respectivelyAnd corresponding magnitude of voltage upper and lower limit V1, V2 are recorded, judge rectify a deviation voltage V and magnitude of voltage V1, V2
Magnitude relationship, work as V>V1 or V<During V2, V=V0；Work as V2<V<During V1,。
It can be used as preferably：Also include step h, set VCXO voltage-controlled slope value a, pass through a*=b, b are every
Its VCXO aging drift data, by b compensation to VCXO because in frequency change caused by aging drift.
It can be used as preferably：Fractional frequency signal f2 has similar coarse frequency value with synchronous reference signal f1 frequencies.
It can be used as preferably：As shown in Fig. 2 when carrying out DDS scaling down processings to fractional frequency signal f2 in stepb, adopt
DDS is AD9852, the frequency dividing numerical value of DDS communications is determined by its technical manual, with reference to formula：
Wherein, F is by walking the coarse frequency value of measured signal that hour counter counts, single-chip microcomputer computing obtains, f 1KHz；
Frequency dividing numerical value is write into DDS buffer areas, 1KHz frequency signal is obtained after DDS, the frequency signal of gained is delivered to again
Final 1KHz frequency signals output is obtained after low-pass filtering module.
As shown in figure 3, in step c, when GPS second pulse gate signal f0 is in high level, after the t1 times, VCXO's
The rising edge of first pulse of fractional frequency signal f2, makes accumulation of phase effective, and after the T seconds, GPS second pulse gate high level arrives again
When coming, after the t2 times, when then and the fractional frequency signal f2 rising edge that arrives arrive when, i.e. moment reference signal f1 with
The phase difference accumulation calculating process of VCXO fractional frequency signals is continued for.
The present invention's is not limited to above-described embodiment, and the technical scheme of above-mentioned each embodiment of the invention can be handed over each other
Fork combination forms new technical scheme, in addition all technical schemes formed using equivalent substitution, all falls within the guarantor of application claims
In the range of shield.
Claims (7)
1. a kind of pulse per second (PPS) gate controller, including VXCO modules, it is characterised in that：Also include gps signal receiver, phase
Accumulate module, DDS frequency division modules, voltage-controlled correcting module and servo module；
The gps signal receiver is suitable to receive gps signal and its signal output part is connected to the letter of the accumulation of phase module
Number input；
The signal input part of the DDS frequency division modules is connected to the signal output part of the VXCO modules, the DDS frequency division modules
Signal output part be connected to the signal input part of the accumulation of phase module；
The signal output part of the accumulation of phase module is connected to the signal input part of the servo module, the accumulation of phase mould
Block is suitable to calculate the synchronous reference signal from gps signal receiver and the phase between VCXO fractional frequency signal by accumulating
Potential difference, and phase difference is converted into difference on the frequency, then difference on the frequency is converted into direct current correction voltage by voltage-controlled Slope relationship, finally
By direct current correction voltage output to servo module；
The quantized system that is acted on the VCXO modules of the servo module being suitable to is detected in terms of to obtain initial correction voltage,
Voltage-controlled amendment is carried out to VCXO modules by voltage-controlled correcting module after initial correction voltage combination direct current rectifies a deviation voltage again.
2. a kind of pulse per second (PPS) gate control method, including following characteristics step：
A, GPS second pulse signal f0, the GPS second arteries and veins are obtained after obtaining gps satellite signal and converted processing by receiver
The frequency for rushing signal strobe f0 is that 1Hz i.e. width is T=1 second, and the same of 1KHZ is produced based on the GPS second pulse gate signal f0
Reference signal f1 is walked, the signal f0 and signal f1 are delivered in accumulation of phase module；
B, VCXO output signal is obtained into fractional frequency signal f2 after DDS is divided and delivered in accumulation of phase module；
C, when GPS second pulse gate signal f0 is in high level, the phase difference for starting the signal f1 and fractional frequency signal f2 is accumulated
Calculate, and record the concrete numerical value of the signal f1 and signal f2 phase difference；
D, in the sampling by M T=1 second andWhen=0, the phase data obtained in the M*T times is converted into described in correspondence
Signal f1 and signal f2 frequency difference value；
E, according to default VCXO voltage-controlled slope value by frequency difference valueTransform into direct current correction magnitude of voltage；
F, by voltage-controlled correcting module according to formulaVoltage-controlled amendment, V are carried out to the VCXO0It is defeated for servo module
The magnitude of voltage of voltage-controlled correcting module is delivered to, V is the correction voltage for actually directly acting on VCXO.
3. pulse per second (PPS) gate control method according to claim 1, it is characterised in that：Also include step g, the VCXO is set
The peak and minimum of output frequency be respectivelyAnd corresponding magnitude of voltage upper and lower limit V1, V2 are recorded, judge
The correction voltage V and described magnitude of voltage V1, V2 magnitude relationship, as the V>V1 or V<During V2, the V=V0；When described
V2<V<It is described during V1。
4. pulse per second (PPS) gate control method according to claim 3, it is characterised in that：Also include step h, set VCXO pressure
Slope value a is controlled, passes through a*=b, b are daily VCXO aging drift data, and b compensation is arrived into VCXO caused by aging drift
In frequency change.
5. pulse per second (PPS) gate control method according to claim 1, it is characterised in that：The fractional frequency signal f2 with it is described synchronous
Reference signal f1 frequencies have similar coarse frequency value.
6. pulse per second (PPS) gate control method according to claim 1, it is characterised in that：To fractional frequency signal in the step b
When f2 carries out DDS scaling down processings, the DDS used determines the divider ratio of DDS communications by its technical manual for AD9852
Value, with reference to formula：
Wherein, F is by walking the coarse frequency value of measured signal that hour counter counts, single-chip microcomputer computing obtains, f 1KHz；
The frequency dividing numerical value is write into DDS buffer areas, 1KHz frequency signal is obtained after DDS, by the frequency signal of gained again
Final 1KHz frequency signals output is obtained after delivering to low-pass filtering module.
7. pulse per second (PPS) gate control method according to claim 1, it is characterised in that：In the step c, in GPS second arteries and veins
Signal strobe f0 is rushed in high level, after the t1 times, the rising edge of VCXO first pulse of fractional frequency signal f2, tires out phase
Product is effective, after the T seconds, when GPS second pulse gate high level arrives again, after the t2 times, when frequency dividing that is subsequent and arriving
When signal f2 rising edge arrives, i.e. the phase difference accumulation calculating process of moment reference signal f1 and VCXO fractional frequency signals is held always
It is continuous.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610868881.8A CN107896098A (en) | 2016-09-30 | 2016-09-30 | A kind of pulse per second (PPS) gate controller and control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610868881.8A CN107896098A (en) | 2016-09-30 | 2016-09-30 | A kind of pulse per second (PPS) gate controller and control method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107896098A true CN107896098A (en) | 2018-04-10 |
Family
ID=61802457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610868881.8A Pending CN107896098A (en) | 2016-09-30 | 2016-09-30 | A kind of pulse per second (PPS) gate controller and control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107896098A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201252534Y (en) * | 2008-05-23 | 2009-06-03 | 北京工业大学 | Digital phase-locked loop system realized by GPS time signals |
| CN104410413A (en) * | 2014-11-20 | 2015-03-11 | 江汉大学 | Atomic frequency standard frequency correction method and device and atomic frequency standard |
| CN104485948A (en) * | 2014-10-31 | 2015-04-01 | 江汉大学 | Control method for time standard equipment and time standard equipment |
| CN104485954A (en) * | 2014-10-31 | 2015-04-01 | 江汉大学 | Control method for time equipment and time equipment |
-
2016
- 2016-09-30 CN CN201610868881.8A patent/CN107896098A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201252534Y (en) * | 2008-05-23 | 2009-06-03 | 北京工业大学 | Digital phase-locked loop system realized by GPS time signals |
| CN104485948A (en) * | 2014-10-31 | 2015-04-01 | 江汉大学 | Control method for time standard equipment and time standard equipment |
| CN104485954A (en) * | 2014-10-31 | 2015-04-01 | 江汉大学 | Control method for time equipment and time equipment |
| CN104410413A (en) * | 2014-11-20 | 2015-03-11 | 江汉大学 | Atomic frequency standard frequency correction method and device and atomic frequency standard |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1183676C (en) | Multi-input phase locked loop with interference-free reference switch | |
| CN100477527C (en) | Phase-locked loop and method for improving clock accuracy | |
| US20090296869A1 (en) | Communication systems, clock generation circuits thereof, and method for generating clock signal | |
| CN104410413B (en) | Atomic frequency standard frequency Correction Method, device and atomic frequency standard | |
| US9240795B2 (en) | Apparatus and methods for phase-locked loop oscillator calibration and lock detection | |
| CN104485954B (en) | The control method and time device of a kind of time device | |
| CN103219946A (en) | Polar transmitter having frequency modulating path with interpolation in compensating feed input and related method thereof | |
| CN105049040B (en) | A kind of method that Atomic Clocks Based on Coherent Population Trapping output frequency is corrected using GNSS | |
| CN107315338A (en) | A kind of chronometer time correcting device | |
| TW200509537A (en) | System and method for coarse tuning a phase locked loop (PLL) synthesizer using 2-pi slip detection | |
| CN108923782A (en) | A kind of all-digital phase-locked loop and its quick phase-lock technique | |
| JP2000278124A (en) | Pll circuit | |
| CN107896106A (en) | Adjust the phase of digital phase locked loop | |
| CN203872160U (en) | Synchronous processing apparatus | |
| CN204993302U (en) | Digital low frequency phase -locked loop | |
| CN105281752A (en) | Clock data recovery system based on digital phase-locked loop | |
| CN103338036B (en) | Based on the frequency signal link control method of atomic clock of phase group process | |
| CN102281062B (en) | Method and equipment for outputting clock signals | |
| CN207218667U (en) | A kind of satellite navigation time complexity curve device | |
| CN103152038B (en) | A kind of passive Rb atom frequency marking servo-drive system and quantum frequency discrimination method | |
| CN101207436B (en) | Apparatus and method of feedback time-delay phase locking as well as phase error detection unit | |
| CN107896098A (en) | A kind of pulse per second (PPS) gate controller and control method | |
| CN104639158B (en) | Synchronous two phase-locked loop adjusting method | |
| CN102082658B (en) | Method and device for enhancing frequency stability of target clock | |
| CN207133596U (en) | A kind of time-domain signal source device based on constant temperature |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180410 |