CN107895942B - Esd protection circuit and method, array substrate, display device - Google Patents
Esd protection circuit and method, array substrate, display device Download PDFInfo
- Publication number
- CN107895942B CN107895942B CN201711271063.0A CN201711271063A CN107895942B CN 107895942 B CN107895942 B CN 107895942B CN 201711271063 A CN201711271063 A CN 201711271063A CN 107895942 B CN107895942 B CN 107895942B
- Authority
- CN
- China
- Prior art keywords
- film transistor
- grid
- double gate
- gate thin
- esd protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
Abstract
The invention discloses a kind of esd protection circuit and method, array substrate, display device, the circuit includes: electrostatic starting point and Electro-static Driven Comb end；The ESD protection component being connected between the electrostatic starting point and Electro-static Driven Comb end; the electrostatic that the electrostatic starting point generates is transmitted to the Electro-static Driven Comb end by the ESD protection component; the ESD protection component includes at least one double gate thin-film transistor; wherein, the double gate thin-film transistor has first grid and second grid；Negative pressure provides end; the negative pressure provides end and is connected with the second grid of at least one double gate thin-film transistor, and the negative pressure provides end and is used to provide negative pressure to the second grid of at least one double gate thin-film transistor to expand the flat region of the ESD protection component.As a result, by adjusting the second grid voltage of double gate thin-film transistor, changes the threshold voltage of thin film transistor (TFT), and then effectively expand the flat region of ESD protection component, reduce leakage current, the signal voltage of display device is inhibited to lose.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of esd protection circuit, a kind of array substrate, a kind of display
Device and a kind of ESD guard method.
Background technique
ESD (Electro-Static discharge, Electro-static Driven Comb) protects the flat region of structure relatively narrow in the related technology,
It causes the operating voltage range leakage current in display device larger, the voltage of data-signal and grid signal is caused to be leaked.
Summary of the invention
The present invention is directed to solve at least some of the technical problems in related technologies.For this purpose, of the invention
First purpose is to propose a kind of esd protection circuit, can effectively expand flat region, reduce leakage current.
Second object of the present invention is to propose a kind of array substrate.Third object of the present invention is to propose one kind
Display device and fourth object of the present invention are to propose a kind of ESD guard method.
In order to achieve the above objectives, a kind of esd protection circuit that first aspect present invention embodiment proposes, comprising: electrostatic rises
Beginning and Electro-static Driven Comb end；The ESD protection component being connected between the electrostatic starting point and Electro-static Driven Comb end, the ESD are protected
The electrostatic that the electrostatic starting point generates is transmitted to the Electro-static Driven Comb end by protecting assembly, and the ESD protection component includes at least
One double gate thin-film transistor, wherein the double gate thin-film transistor has first grid and second grid；Negative pressure provides end,
The negative pressure provides end and is connected with the second grid of at least one double gate thin-film transistor, the negative pressure offer end for
The second grid of at least one double gate thin-film transistor provides negative pressure to expand the flat region of the ESD protection component.
The esd protection circuit proposed according to embodiments of the present invention, it includes at least one double grid film crystal that ESD, which protects component,
Pipe, negative pressure provide end and provide negative pressure to the second grid of at least one double gate thin-film transistor to expand the flat of ESD protection component
Smooth area.As a result, by the voltage of the second grid of adjusting double gate thin-film transistor, change the threshold voltage of thin film transistor (TFT), into
And the flat region of ESD protection component is effectively expanded, leakage current is reduced, the signal voltage of display device is inhibited to lose.
According to one embodiment of present invention, ESD protection component includes the first double gate thin-film transistor, and described first
The first end of double gate thin-film transistor is connected with the electrostatic starting point, the second end of first double gate thin-film transistor and institute
It states Electro-static Driven Comb end to be connected, the first grid of first double gate thin-film transistor is thin by first capacitor and first double grid
The first end of film transistor is connected, and the first grid of first double gate thin-film transistor also passes through the second capacitor and described first
The second end of double gate thin-film transistor is connected.
According to one embodiment of present invention, the ESD protection component includes that the second double gate thin-film transistor and third are double
Gate thin-film transistors, wherein the first end of second double gate thin-film transistor is connected with the electrostatic starting point, and described second
The second end of double gate thin-film transistor is connected with the Electro-static Driven Comb end, the first grid of second double gate thin-film transistor with
The first end of second double gate thin-film transistor is connected；The first end of the third double gate thin-film transistor and the electrostatic rise
Beginning is connected, and the second end of the third double gate thin-film transistor is connected with the Electro-static Driven Comb end, the third double grid film
The first grid of transistor is connected with the second end of the third double gate thin-film transistor.
According to one embodiment of present invention, the electrostatic starting point is connected with grid line or data line.
According to one embodiment of present invention, the Electro-static Driven Comb end and the metal layer phase where public electrode lead-out wire
Even.
According to one embodiment of present invention, the first grid is top-gated, and the second grid is bottom gate.
In order to achieve the above objectives, a kind of array substrate that second aspect of the present invention embodiment proposes, including a plurality of grid line,
Multiple data lines and the esd protection circuit described at least one.
The array substrate proposed according to embodiments of the present invention passes through the esd protection circuit of aforementioned first aspect embodiment, energy
Enough flat regions for effectively expanding esd protection circuit, reduce leakage current, the signal voltage of display device are inhibited to lose.
According to one embodiment of present invention, when the esd protection circuit is at least two, ESD described in a portion
The electrostatic starting point of protection circuit is connected with a plurality of grid line respectively, and the electrostatic of esd protection circuit described in another part rises
Beginning is respectively to be connected with the multiple data lines.
In order to achieve the above objectives, a kind of display device that third aspect present invention embodiment proposes, including the array
Substrate.
The display device proposed according to embodiments of the present invention can by the array substrate of aforementioned second aspect embodiment
The flat region for effectively expanding esd protection circuit in array substrate, reduces leakage current, the signal voltage of display device is inhibited to lose.
In order to achieve the above objectives, a kind of Electro-static Driven Comb ESD guard method that fourth aspect present invention embodiment proposes, including
Following steps: component is protected to produce the electrostatic starting point by the ESD being connected between electrostatic starting point and Electro-static Driven Comb end
Raw electrostatic is transmitted to the Electro-static Driven Comb end, wherein and the ESD protection component includes at least one double gate thin-film transistor,
The double gate thin-film transistor has first grid and second grid；End is provided at least one described double grid film by negative pressure
The second grid of transistor provides negative pressure, to expand the flat region of the ESD protection component.
The ESD guard method proposed according to embodiments of the present invention, it includes at least one double grid film crystal that ESD, which protects component,
Pipe, negative pressure provide end and provide negative pressure to the second grid of at least one double gate thin-film transistor to expand the flat of ESD protection component
Smooth area.As a result, by the voltage of the second grid of adjusting double gate thin-film transistor, change the threshold voltage of thin film transistor (TFT), into
And the flat region of ESD protection component is effectively expanded, leakage current is reduced, the signal voltage of display device is inhibited to lose.
Detailed description of the invention
Fig. 1 is the block diagram of esd protection circuit according to an embodiment of the present invention；
Fig. 2 is the voltage and current relationship of electrostatic starting point in esd protection circuit according to an embodiment of the invention
Curve synoptic diagram；
Fig. 3 is the circuit diagram of esd protection circuit according to an embodiment of the invention；
Fig. 4 be in esd protection circuit according to an embodiment of the invention the threshold voltage of double gate thin-film transistor and its
Bottom gate voltage VAG_SRelationship curve synoptic diagram；
Fig. 5 be esd protection circuit according to an embodiment of the invention different threshold voltages under electrostatic starting point electricity
The curve synoptic diagram of pressure and current relationship；
Fig. 6 is the circuit diagram of esd protection circuit according to an embodiment of the invention: and
Fig. 7 is the flow chart of ESD guard method according to an embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
Below with reference to the accompanying drawings the esd protection circuit and method, array substrate, display device of the embodiment of the present invention described.
Fig. 1 is the block diagram of esd protection circuit according to an embodiment of the present invention.As shown in Figure 1, ESD protection electricity
Road includes: that electrostatic starting point P1, Electro-static Driven Comb end P2, ESD protection component 10 and negative pressure provide end P3.
Wherein, ESD protects component 10 to be connected between electrostatic starting point P1 and Electro-static Driven Comb end P2, and ESD protects component 10
The P1 electrostatic generated in electrostatic starting point is transmitted to Electro-static Driven Comb end P2, it includes at least one double grid film that ESD, which protects component 10,
Transistor TFT, wherein double gate thin-film transistor TFT has first grid G1 and second grid G2；Negative pressure provide end P3 at least
The second grid G2 of one double gate thin-film transistor TFT is connected, and negative pressure provides end VSH and is used for at least one double grid film crystal
The second grid G2 of pipe TFT provides negative pressure to expand the flat region of ESD protection component 10.
It should be noted that the voltage V of electrostatic starting point P1 and electric current I relation curve are there are a flat region, i.e. ESD is protected
The flat region of protecting assembly 10, as shown in Fig. 2, respectively with VTNAnd VTPRepresent the boundary of negative sense and positive flat region.In the flat region
In electric current it is smaller, outside flat region, electric current is increased rapidly, thus by make flat region cover display device normal working voltage
Range can inhibit the signal voltage of display device to lose.
Specifically, applying negative voltage by the second grid to double gate thin-film transistor TFT, it is thin double grid can be increased
The threshold voltage of film transistor TFT, and then increase the range of the flat region of ESD protection component 10, flat region electric current is effectively reduced,
The electric current for reducing esd protection circuit when display device works normally, inhibits signal voltage to lose.
According to one embodiment of present invention, electrostatic starting point P1 and gate lines G ate or data line Data.That is,
As shown in Fig. 1,3 and 6, the first end of ESD protection component 10 can be connected with gate lines G ate, or be connected with data line Data.
According to one embodiment of present invention, Electro-static Driven Comb end P2 can be connected for benchmark pressure-wire Vref.More specifically, quiet
Electric release end P2 can be connected with the metal layer where public electrode lead-out wire.
According to one embodiment of present invention, first grid G1 can be top-gated, and second grid G2 can be bottom gate.
According to one embodiment of present invention, double gate thin-film transistor TFT can be one, as shown in Fig. 2, ESD protection group
Part 10 includes that the first end of the first double gate thin-film transistor T1, the first double gate thin-film transistor T1 is connected with electrostatic starting point P1,
The second end of first double gate thin-film transistor T1 is connected with Electro-static Driven Comb end P2, the first grid of the first double gate thin-film transistor T1
G1 is connected by first capacitor C1 with the first end of the first double gate thin-film transistor T1, and the first of the first double gate thin-film transistor T1
Grid G 1 is also connected by the second capacitor C2 with the second end of the first double gate thin-film transistor T1.First double gate thin-film transistor T1
Second grid G2 and negative pressure end P3 be provided be connected.
In a specific example, the first end of the first double gate thin-film transistor T1 can be drain electrode, and the first double grid film is brilliant
The second end of body pipe T1 can be source electrode.
In conjunction with the embodiment of Fig. 3-4, the working principle of the esd protection circuit of the embodiment of the present invention is as follows:
It is assumed that it is V that the first end of the first double gate thin-film transistor T1, which receives amplitude,ESDPulse voltage, due to capacitor coupling
It closes, the voltage of the first grid G1 of the first double gate thin-film transistor T1 are as follows:
If VESDIt is positive, then VREF<VG<VESD, wherein VREFFor the voltage of benchmark pressure-wire, VGIt is brilliant for the first double grid film
The voltage of the first grid G1 of body pipe T1, C1For the capacitance of first capacitor, C2For the capacitance of the second capacitor.
When the first double gate thin-film transistor T1 conducting, ESD protection component 10 is opened, and the first double gate thin-film transistor T1 is led
It is logical to need to meet VG-VREF≥Vth, i.e.,
Wherein, VthFor the threshold voltage of the first double gate thin-film transistor T1.
It can be obtained after being converted to above formula:
The positive boundary of flat region is as a result,
If VESDIt is negative, then VREF>VG>VESD, the first double gate thin-film transistor T1, which is connected, to be needed to meet VG-VESD≥Vth,
I.e.
It can be obtained after being converted to above formula:
The negative sense boundary of flat region is as a result,
In conjunction with formulaWithIt can be found that increasing the first double grid
The threshold voltage V of thin film transistor (TFT) T1thThe flat region of ESD protection component 10 can effectively be extended.
As shown in Figure 4, the threshold voltage V of double gate thin-film transistor T1thBy second grid, that is, bottom gate voltage VAG_SControl.
Based on this, as shown in figure 3, applying negative voltage by the second grid to the first double gate thin-film transistor T1, the can be increased
The threshold voltage of one double gate thin-film transistor T1, expands the flat region of ESD protection component 10, and then flat region can be effectively reduced
Electric current.
Further, by using the voltage of T1 couples of the double gate thin-film transistor of different threshold voltages of electrostatic starting point P1
V is emulated with electric current I relationship, and simulation result as shown in Figure 5 can be obtained, from fig. 5, it can be seen that the threshold of double gate thin-film transistor
Threshold voltage VthIt is gradually increased according to shown direction, the threshold voltage V of double gate thin-film transistorthBigger, the range of flat region is got over
Greatly, conversely, the threshold voltage V of double gate thin-film transistorthSmaller, the range of flat region is smaller.
According to another embodiment of the invention, double gate thin-film transistor can be two, specifically, as shown in fig. 6, ESD
Protecting component 10 includes the second double gate thin-film transistor T2 and third double gate thin-film transistor T3, wherein the second double grid film is brilliant
The first end of body pipe T2 is connected with electrostatic starting point P1, second end and the Electro-static Driven Comb end P2 phase of the second double gate thin-film transistor T2
Even, the first grid of the second double gate thin-film transistor T2 is connected with the first end of the second double gate thin-film transistor T2；Third double grid
The first end of thin film transistor (TFT) T3 is connected with electrostatic starting point P1, the second end and Electro-static Driven Comb of third double gate thin-film transistor T3
P2 is held to be connected, the first grid of third double gate thin-film transistor T3 is connected with the second end of third double gate thin-film transistor T3.The
The second grid of two double gate thin-film transistor T2 and third double gate thin-film transistor T3 provide end P3 with negative pressure and are connected.
That is, the second double gate thin-film transistor T2 and third double gate thin-film transistor T3 uses diode connection side
Formula.
In conjunction with the embodiment of Fig. 6, the working principle of the esd protection circuit of the embodiment of the present invention is as follows:
Assuming that it is V that electrostatic starting point P1, which receives amplitude,ESDPulse voltage, due to the second double gate thin-film transistor T2's
First grid G1 is connected with the first end of the second double gate thin-film transistor T2, and the first end of the second double gate thin-film transistor T2 with
Electrostatic starting point P1 is connected, so, the voltage of the first grid G1 of the second double gate thin-film transistor T2 are as follows: VG2=VESD.Also,
Since the first grid G1 of third double gate thin-film transistor T3 is connected with the second end of third double gate thin-film transistor T3, and third
The second end of double gate thin-film transistor T3 is connected with Electro-static Driven Comb end P2, so, the first grid of third double gate thin-film transistor T3
The voltage of pole G1 are as follows: VG3=VREF.Wherein, VREFFor the voltage of benchmark pressure-wire.
If VESD> 0, work as VESD>VREF+Vth_2(Vth_2For the threshold voltage of the second double gate thin-film transistor T2) when, second
Double gate thin-film transistor T2 conducting, voltage VESDReference voltage line is leaked by the second double gate thin-film transistor T2, so, ESD
The positive boundary for protecting the flat region of component 10 is VTP=VREF+Vth_2.If VESD< 0, work as VREF-VESD>Vth_3(Vth_3For third
The threshold voltage of double gate thin-film transistor T3) when, third double gate thin-film transistor T3 is opened, voltage VESDIt is thin by third double grid
Film transistor T3 leaks into reference voltage line, so, it is V that ESD, which protects the negative sense boundary voltage of the flat region of component 10,TN=VREF-
Vth_3。
As above analysis is it is found that Vth_2And Vth_3Bigger, flat region is wider.Also, the second double gate thin-film transistor T2 and third
The threshold voltage V of double gate thin-film transistor T3thControlled by second grid, that is, bottom gate voltage.Based on this, by giving second pair
The second grid of gate thin-film transistors T2 and third double gate thin-film transistor T3 apply negative voltage, and it is thin can to increase the second double grid
The threshold voltage of film transistor T2 and third double gate thin-film transistor T3 expand the flat region of ESD protection component 10, and then can be with
Flat region electric current is effectively reduced.
It should be noted that the mentioned structure of the embodiment of the present invention can need to only draw a foundation grid with top-gated process compatible
Equipotential line, wherein drawing bottom gate equipotential line can be realized by laying out pattern.
To sum up, the esd protection circuit proposed according to embodiments of the present invention, it includes that at least one double grid is thin that ESD, which protects component,
Film transistor, negative pressure provide end and provide negative pressure to the second grid of at least one double gate thin-film transistor to expand ESD protection group
The flat region of part.As a result, by adjusting the voltage of the second grid of double gate thin-film transistor, change the threshold value electricity of thin film transistor (TFT)
Pressure, and then the flat region of ESD protection component is effectively expanded, leakage current is reduced, the signal voltage of display device is inhibited to lose.
Esd protection circuit based on previous embodiment, the invention also provides a kind of array substrates.
The array substrate of the embodiment of the present invention protects electricity including a plurality of grid line, multiple data lines and the ESD of at least one
Road.Array substrate further includes a plurality of source electrode line.
According to one embodiment of present invention, when esd protection circuit is at least two, a portion esd protection circuit
Electrostatic starting point be connected respectively with a plurality of grid line, the electrostatic starting point of another part esd protection circuit respectively with a plurality of number
It is connected according to line.
The array substrate proposed according to embodiments of the present invention passes through the esd protection circuit of aforementioned first aspect embodiment, energy
Enough flat regions for effectively expanding esd protection circuit, reduce leakage current, the signal voltage of display device are inhibited to lose.
Esd protection circuit based on previous embodiment, the invention also provides a kind of display devices.
The display device of the embodiment of the present invention, the array substrate including previous embodiment.
The display device proposed according to embodiments of the present invention can by the array substrate of aforementioned second aspect embodiment
The flat region for effectively expanding esd protection circuit in array substrate, reduces leakage current, the signal voltage of display device is inhibited to lose.
Corresponding with the esd protection circuit of previous embodiment, the invention also provides a kind of protection sides Electro-static Driven Comb ESD
Method.
Fig. 7 is Electro-static Driven Comb ESD guard method flow chart according to an embodiment of the present invention.As shown in fig. 7, Electro-static Driven Comb
ESD guard method the following steps are included:
S1: component is protected to generate electrostatic starting point by the ESD being connected between electrostatic starting point and Electro-static Driven Comb end
Electrostatic be transmitted to Electro-static Driven Comb end, wherein ESD protection component includes at least one double gate thin-film transistor, and double grid film is brilliant
Body pipe has first grid and second grid.
S2: end is provided by negative pressure and provides negative pressure to the second grid of at least one double gate thin-film transistor, to expand ESD
Protect the flat region of component.
The ESD guard method proposed according to embodiments of the present invention, it includes at least one double grid film crystal that ESD, which protects component,
Pipe, negative pressure provide end and provide negative pressure to the second grid of at least one double gate thin-film transistor to expand the flat of ESD protection component
Smooth area.As a result, by the voltage of the second grid of adjusting double gate thin-film transistor, change the threshold voltage of thin film transistor (TFT), into
And the flat region of ESD protection component is effectively expanded, leakage current is reduced, the signal voltage of display device is inhibited to lose.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect
It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary
The interaction relationship of the connection in portion or two elements, unless otherwise restricted clearly.For those of ordinary skill in the art
For, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with
It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists
Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of
First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below "
One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (10)
1. a kind of Electro-static Driven Comb esd protection circuit characterized by comprising
Electrostatic starting point and Electro-static Driven Comb end；
The ESD protection component being connected between the electrostatic starting point and Electro-static Driven Comb end, the ESD protection component will be described quiet
The electrostatic that electrical initiation end generates is transmitted to the Electro-static Driven Comb end, and the ESD protection component includes that at least one double grid film is brilliant
Body pipe, wherein the double gate thin-film transistor has first grid and second grid；
Negative pressure provides end, and the negative pressure provides end and is connected with the second grid of at least one double gate thin-film transistor, described
Negative pressure provides end and is used to provide negative pressure to the second grid of at least one double gate thin-film transistor to expand the ESD protection
The flat region of component, wherein the first grid of at least one double gate thin-film transistor is electrically connected with the electrostatic starting point.
2. Electro-static Driven Comb esd protection circuit according to claim 1, which is characterized in that ESD protection component includes the
One double gate thin-film transistor, the first end of first double gate thin-film transistor are connected with the electrostatic starting point, and described first
The second end of double gate thin-film transistor is connected with the Electro-static Driven Comb end, and the first grid of first double gate thin-film transistor is logical
It crosses first capacitor to be connected with the first end of first double gate thin-film transistor, the first grid of first double gate thin-film transistor
Pole also passes through the second capacitor and is connected with the second end of first double gate thin-film transistor.
3. Electro-static Driven Comb esd protection circuit according to claim 1, which is characterized in that the ESD protection component includes being
Second double gate thin-film transistor and third double gate thin-film transistor, wherein
The first end of second double gate thin-film transistor is connected with the electrostatic starting point, second double gate thin-film transistor
Second end be connected with the Electro-static Driven Comb end, the first grid of second double gate thin-film transistor and second double grid are thin
The first end of film transistor is connected；
The first end of the third double gate thin-film transistor is connected with the electrostatic starting point, the third double gate thin-film transistor
Second end be connected with the Electro-static Driven Comb end, the first grid of the third double gate thin-film transistor and the third double grid are thin
The second end of film transistor is connected.
4. Electro-static Driven Comb esd protection circuit according to any one of claim 1-3, which is characterized in that the electrostatic rises
Beginning is connected with grid line or data line.
5. Electro-static Driven Comb esd protection circuit according to any one of claim 1-3, which is characterized in that the electrostatic is released
End is put to be connected with the metal layer where public electrode lead-out wire.
6. Electro-static Driven Comb esd protection circuit according to any one of claim 1-3, which is characterized in that the first grid
Extremely top-gated, the second grid are bottom gate.
7. a kind of array substrate, which is characterized in that including a plurality of grid line, multiple data lines and at least one such as claim 1-
Esd protection circuit described in any one of 6.
8. array substrate according to claim 7, which is characterized in that when the esd protection circuit is at least two, wherein
The electrostatic starting point of a part of esd protection circuit is connected with a plurality of grid line respectively, the protection of ESD described in another part
The electrostatic starting point of circuit is connected with the multiple data lines respectively.
9. a kind of display device, which is characterized in that including array substrate as claimed in claim 7 or 8.
10. a kind of Electro-static Driven Comb ESD guard method, which comprises the following steps:
Component is protected to generate the electrostatic starting point by the ESD that is connected between electrostatic starting point and Electro-static Driven Comb end quiet
Electrical conduction is to the Electro-static Driven Comb end, wherein the ESD protection component includes at least one double gate thin-film transistor, described double
Gate thin-film transistors have first grid and second grid；
End is provided by negative pressure and provides negative pressure to the second grid of at least one double gate thin-film transistor, described in expanding
The flat region of ESD protection component, wherein the first grid of at least one double gate thin-film transistor and the electrostatic starting point
Electrical connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711271063.0A CN107895942B (en) | 2017-12-05 | 2017-12-05 | Esd protection circuit and method, array substrate, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711271063.0A CN107895942B (en) | 2017-12-05 | 2017-12-05 | Esd protection circuit and method, array substrate, display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107895942A CN107895942A (en) | 2018-04-10 |
| CN107895942B true CN107895942B (en) | 2019-10-08 |
Family
ID=61807133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711271063.0A Active CN107895942B (en) | 2017-12-05 | 2017-12-05 | Esd protection circuit and method, array substrate, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107895942B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114333681B (en) * | 2018-09-27 | 2023-08-18 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109449157A (en) * | 2019-01-28 | 2019-03-08 | 南京中电熊猫平板显示科技有限公司 | Electrostatic discharge protection circuit and manufacturing method, electrostatic protection module and liquid crystal display device |
| CN110415648A (en) * | 2019-07-16 | 2019-11-05 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN113690153B (en) * | 2021-08-10 | 2023-10-31 | 深圳市华星光电半导体显示技术有限公司 | Method for preventing ESD from damaging TFT and preparation method of TFT |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102629049A (en) * | 2011-07-18 | 2012-08-08 | 京东方科技集团股份有限公司 | Electrostatic protection structure, array substrate, liquid crystal panel and display device |
| CN103268876A (en) * | 2012-09-27 | 2013-08-28 | 厦门天马微电子有限公司 | Electrostatic discharge protection circuit, display panel and display device |
| CN103294251A (en) * | 2012-09-25 | 2013-09-11 | 上海天马微电子有限公司 | ESD protecting device for touch screen |
| KR20150011417A (en) * | 2013-07-22 | 2015-02-02 | 엘지디스플레이 주식회사 | Electrostatic discharge protection circuit and method for fabricating the same |
-
2017
- 2017-12-05 CN CN201711271063.0A patent/CN107895942B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102629049A (en) * | 2011-07-18 | 2012-08-08 | 京东方科技集团股份有限公司 | Electrostatic protection structure, array substrate, liquid crystal panel and display device |
| CN103294251A (en) * | 2012-09-25 | 2013-09-11 | 上海天马微电子有限公司 | ESD protecting device for touch screen |
| CN103268876A (en) * | 2012-09-27 | 2013-08-28 | 厦门天马微电子有限公司 | Electrostatic discharge protection circuit, display panel and display device |
| KR20150011417A (en) * | 2013-07-22 | 2015-02-02 | 엘지디스플레이 주식회사 | Electrostatic discharge protection circuit and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107895942A (en) | 2018-04-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107895942B (en) | Esd protection circuit and method, array substrate, display device | |
| US9726952B2 (en) | Liquid crystal display having wide viewing angle | |
| CN102640042B (en) | Liquid crystal indicator | |
| KR100977978B1 (en) | Liquid crystal display and fabricating method thereof | |
| CN102751968B (en) | High-voltage device and overvoltage protection method of high-voltage transistor | |
| CN205450520U (en) | Array substrate and display device | |
| US20130050600A1 (en) | Pixel array substrate | |
| KR20150076405A (en) | Electrostatic discharging device of display device and method of manufacturing the same | |
| US20210043621A1 (en) | Electrostatic protection circuit, array substrate and display device | |
| US9607979B2 (en) | Liquid crystal display device and manufacturing method thereof | |
| JP6370279B2 (en) | Bootstrap compensation circuit and power module | |
| US10720423B2 (en) | ESD protection circuit, display panel, and display device | |
| CN108732839B (en) | Electrostatic protection circuit, electrostatic protection module and liquid crystal display device | |
| CN106200172A (en) | A kind of array base palte and display device | |
| WO2019101133A1 (en) | Detection apparatus, fabrication method thereof, array substrate, and display apparatus | |
| WO2020259012A1 (en) | Electrostatic discharge circuit, display panel, display device, and driving method for electrostatic discharge circuit | |
| CN108761940B (en) | Electrostatic protection circuit, electrostatic protection module and liquid crystal display device | |
| KR20150015608A (en) | Electrostatic discharge circuit and display device having thereof | |
| CN204719374U (en) | A kind of array base palte and display device | |
| CN106710552A (en) | Pixel circuit structure | |
| JP5939840B2 (en) | Semiconductor device | |
| US10101852B2 (en) | Organic light emitting display device | |
| CN106129046A (en) | Array base palte, display floater and display device | |
| CN105308668A (en) | Thin-film transistor array, method for manufacturing same, image display device, and display method | |
| CN207489872U (en) | A kind of ESD protection circuit and structure based on CMOS technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |