CN107888194B - Operational amplifier for pipeline analog-to-digital converter - Google Patents
Operational amplifier for pipeline analog-to-digital converter Download PDFInfo
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- CN107888194B CN107888194B CN201710871483.6A CN201710871483A CN107888194B CN 107888194 B CN107888194 B CN 107888194B CN 201710871483 A CN201710871483 A CN 201710871483A CN 107888194 B CN107888194 B CN 107888194B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
- H03M1/183—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
Abstract
The invention discloses an operational amplifier for a pipeline analog-to-digital converter, which comprises: a first main operational amplifier, a second main operational amplifier; the first main operational amplifier comprises a first cascode P-type transistor pair, a second cascode P-type transistor pair, a first cascode N-type transistor pair and a first common source N-type transistor pair which are sequentially connected, and the source electrode of the first common source N-type transistor pair is connected with a first tail current N-type transistor; the second main operational amplifier comprises a third cascode P-type transistor pair and a second common source N-type transistor pair which are connected in sequence, and the source electrode of the second common source N-type transistor pair is connected with a second tail current N-type transistor; and the drain of the first cascode P-type transistor pair is connected with the drain of the third cascode P-type transistor pair through a compensation capacitor. Compared with the prior art, the invention can greatly improve the gain and the precision of the operational amplifier under the condition of low voltage.
Description
Technical Field
The invention belongs to the field of operational amplifiers, and particularly relates to an operational amplifier for a pipeline analog-to-digital converter.
Background
With the development of the CMOS process, the characteristic size of the MOS transistor is continuously reduced, the characteristic frequency is continuously increased while the intrinsic gain of the MOS transistor is continuously decreased, and the power supply voltage is continuously decreased, which makes the design of the high-gain operational amplifier particularly difficult. The extreme rigor in the pipeline analog-to-digital converter to the operational amplifier in the first stage MDAC makes the design of a high-precision high-speed pipeline ADC particularly difficult.
Conventional pipelined operational amplifiers and each stage's residue operational amplifier are typically implemented using a closed loop high performance amplifier. This structure increases the output impedance and improves the open loop gain by adding an auxiliary operational amplifier, however, the added auxiliary operational amplifier introduces a new parasitic capacitance, thereby increasing the pole and reducing the bandwidth of the entire operational amplifier. The bandwidth of the comparator, noise on the sampling capacitor, and the load capacitance of each stage all affect the precision of the pipeline. In addition, the conventional pipelined operational amplifier cannot realize a high gain in the case where the power supply voltage is low.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an operational amplifier for a pipeline analog-to-digital converter, which can greatly improve the gain and accuracy of an operational amplifier under a low voltage condition.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
an operational amplifier for a pipelined analog-to-digital converter, comprising: a first main operational amplifier, a second main operational amplifier;
the first main operational amplifier comprises a first cascode P-type transistor pair, a second cascode P-type transistor pair, a first cascode N-type transistor pair and a first common source N-type transistor pair which are sequentially connected, and the source electrode of the first common source N-type transistor pair is connected with a first tail current N-type transistor;
the second main operational amplifier comprises a third cascode P-type transistor pair and a second common source N-type transistor pair which are connected in sequence, and the source electrode of the second common source N-type transistor pair is connected with a second tail current N-type transistor;
and the drain of the first cascode P-type transistor pair is connected with the drain of the third cascode P-type transistor pair through a compensation capacitor.
Further, a first additional amplifier is further arranged between the second cascode P-type transistor pair, and the negative electrode and the positive electrode of the input end of the first additional amplifier are respectively connected with the source electrodes of the second cascode P-type transistor pair; and the cathode and the anode of the output end of the first additional amplifier are respectively connected with the grid electrode of the second cascode P-type transistor pair.
Further, a second additional amplifier is further arranged between the first cascode N-type transistor pair, and the cathode and the anode of the input end of the second additional amplifier are respectively connected with the sources of the first cascode N-type transistor pair; and the cathode and the anode of the output end of the second additional amplifier are respectively connected with the grid electrode of the first cascode N-type transistor pair.
The first auxiliary operational amplifier comprises a fourth cascode P-type transistor pair, a fifth cascode P-type transistor pair, a second cascode N-type transistor pair, a third cascode N-type transistor pair and a third cascode N-type transistor pair which are connected in sequence;
the drain of the fourth cascode P-type transistor pair is respectively connected with the drain of the third cascode N-type transistor pair; the source electrode of the third common source N-type transistor pair is connected with a third tail current N-type transistor;
and the grid electrodes of the third common source N-type transistor pair are respectively connected with the grid electrodes of the first common source N-type transistor pair.
Further, a third additional amplifier is further arranged between the fifth cascode P-type transistor pair, and a negative electrode and a positive electrode of an input end of the third additional amplifier are respectively connected with the source electrodes of the fifth cascode P-type transistor pair; and the negative electrode and the positive electrode of the output end of the third additional amplifier are respectively connected with the grid electrode of the fifth cascode P-type transistor pair.
Further, a fourth additional amplifier is further arranged between the second cascode N-type transistor pair, and the negative electrode and the positive electrode of the input end of the fourth additional amplifier are respectively connected with the source electrodes of the second cascode N-type transistor pair; and the negative electrode and the positive electrode of the output end of the fourth additional amplifier are respectively connected with the grid electrode of the second cascode N-type transistor pair.
The second auxiliary operational amplifier comprises a sixth cascode P-type transistor pair, a seventh cascode P-type transistor pair, a fourth cascode N-type transistor pair, a fifth cascode N-type transistor pair and a first cascode P-type transistor pair which are connected in sequence;
the drain of the fifth cascode N-type transistor pair is respectively connected with the drains of the first common-source P-type transistor pair; the source electrode of the first common source P-type transistor pair is connected with a first tail current P-type transistor;
and the gates of the first common source P-type transistor pair are respectively connected with the gates of the first common source N-type transistor pair.
Further, a fifth additional amplifier is further arranged between the seventh cascode P-type transistor pair, and the negative electrode and the positive electrode of the input end of the fifth additional amplifier are respectively connected with the source electrodes of the seventh cascode P-type transistor pair; and the negative electrode and the positive electrode of the output end of the fifth additional amplifier are respectively connected with the grid electrode of the seventh cascode P-type transistor pair.
Further, a sixth additional amplifier is further arranged between the fourth cascode N-type transistor pair, and the negative electrode and the positive electrode of the input end of the sixth additional amplifier are respectively connected with the source electrodes of the fourth cascode N-type transistor pair; and the cathode and the anode of the output end of the sixth additional amplifier are respectively connected with the grid electrode of the fourth cascode N-type transistor pair.
Compared with the prior art, the invention has the beneficial effects that:
in the operational amplifier for the pipeline analog-to-digital converter, the first main operational amplifier is responsible for realizing high gain, the second main operational amplifier is responsible for realizing high output swing amplitude and simultaneously improving gain, and the normal operation of the whole operational amplifier under negative feedback is realized through the cascode compensation of the compensation capacitor Cc. The capacitor Cc is connected with the output end of the second main operational amplifier and the drain end of the PMOS current source of the second main operational amplifier, but not connected with the output of the first-stage operational amplifier, so that the Cc is connected to a low-resistance node, and the zero point of the right half plane is moved to the left half plane. The circuit not only solves the problem of the right half-plane low-frequency zero point of the existing common miller capacitance compensation scheme, but also increases the unit gain bandwidth by adding the left half-plane zero point, and the operational amplifier can realize high bandwidth by larger gm1(M1 tube transconductance) and smaller Cc.
Drawings
FIG. 1 is a circuit diagram of a main operational amplifier for a pipeline analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of an auxiliary operational amplifier for a pipeline ADC according to an embodiment of the present invention;
fig. 3 is a circuit diagram of an auxiliary operational amplifier for a pipeline adc according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.
Example one
Referring to fig. 1, fig. 1 is a circuit diagram of a main operational amplifier for a pipeline analog-to-digital converter according to an embodiment of the present invention, including: a first main operational amplifier, a second main operational amplifier; the first main operational amplifier comprises a first cascode P-type transistor pair M9 and M10, a second cascode P-type transistor pair M7 and M8, a first cascode N-type transistor pair M5 and M6, and a first cascode N-type transistor pair M1 and M2 which are connected in sequence, wherein the sources of the first cascode N-type transistor pair M1 and M2 are connected with a first tail current N-type transistor M0; the second main operational amplifier comprises a third cascode P-type transistor pair M14 and M15 and a second common source N-type transistor pair M12 and M13 which are connected in sequence, and the sources of the second common source N-type transistor pair M12 and M13 are connected with a second tail current N-type transistor M11; the drains of the first cascode P-type transistor pair M9 and M10 are connected to the drains of the third cascode P-type transistor pair M14 and M15 through a compensation capacitor Cc, respectively. A first additional amplifier AN is further arranged between the second cascode P-type transistor pair M7 and M8, and the negative electrode and the positive electrode of the input end of the first additional amplifier AN are respectively connected with the sources of the second cascode P-type transistor pair M7 and M8; and the negative electrode and the positive electrode of the output end of the first additional amplifier AN are respectively connected with the gates of the second cascode P-type transistor pair M7 and M8. A second additional amplifier AP is further arranged between the first cascode N-type transistor pair M5 and M6, and the cathode and the anode of the input end of the second additional amplifier AP are respectively connected with the sources of the first cascode N-type transistor pair M5 and M6; and the cathode and the anode of the output end of the second additional amplifier AP are respectively connected with the gates of the first cascode N-type transistor pair M5 and M6.
In the operational amplifier for the pipeline analog-to-digital converter, the first main operational amplifier is responsible for realizing high gain, the second main operational amplifier is responsible for realizing high output swing amplitude and simultaneously improving gain, and the normal operation of the whole operational amplifier under negative feedback is realized through the cascode compensation of the compensation capacitor Cc. The capacitor Cc is connected with the output end of the second main operational amplifier and the drain end of the PMOS current source of the second main operational amplifier, but not connected with the output of the first-stage operational amplifier, so that the Cc is connected to a low-resistance node, and the zero point of the right half plane is moved to the left half plane. The circuit not only solves the problem of the right half-plane low-frequency zero point of the existing common miller capacitance compensation scheme, but also increases the unit gain bandwidth by adding the left half-plane zero point, and the operational amplifier can realize high bandwidth by larger gm1(M1 tube transconductance) and smaller Cc. The first-stage operational amplifier provides direct current bias through a tail current source MOS tube and an auxiliary operational amplifier. The two-stage operational amplifier structure can increase the gain simultaneously, and the main operational amplifier has 55dB gain and more than 5GHz bandwidth, and has more than 850MHz bandwidth at the position of 24dB gain.
Example two
Fig. 2 is a circuit diagram of an auxiliary operational amplifier for a pipeline analog-to-digital converter according to an embodiment of the present invention, where this embodiment includes the contents of embodiment one, and further includes a first auxiliary operational amplifier, where the first auxiliary operational amplifier includes a fourth cascode P-type transistor pair MAN10, MAN11, a fifth cascode P-type transistor pair MAN8, MAN9, a second cascode N-type transistor pair MAN6, MAN7, a third cascode N-type transistor pair MAN4, MAN5, a third cascode N-type transistor pair MAN1, MAN 2; wherein the drains of the fourth cascode P-type transistor pair MAN10, MAN11 are connected to the drains of the third cascode N-type transistor pair MAN1, MAN2, respectively; the sources of the third common-source N-type transistor pair MAN1, MAN2 are connected to a third tail-current N-type transistor MAN 0; the gates of the third common-source N-type transistor pair MAN1, MAN2 are connected to the gates of the first common-source N-type transistor pair M1, M2, respectively. A third additional amplifier ANN is further arranged between the fifth cascode P-type transistor pair MAN8 and MAN9, and the negative electrode and the positive electrode of the input end of the third additional amplifier ANN are respectively connected with the sources of the fifth cascode P-type transistor pair MAN8 and MAN 9; and the negative electrode and the positive electrode of the output end of the third additional amplifier ANN are respectively connected with the grids of the fifth cascode P-type transistor pair MAN8 and MAN 9. A fourth additional amplifier ANP is further arranged between the second cascode N-type transistor pair MAN6 and MAN7, and the negative electrode and the positive electrode of the input end of the fourth additional amplifier ANP are respectively connected with the sources of the second cascode N-type transistor pair MAN6 and MAN 7; and the cathode and the anode of the output end of the fourth additional amplifier ANP are respectively connected with the gates of the second cascode N-type transistor pair MAN6 and MAN 7.
EXAMPLE III
Fig. 3 is a circuit diagram of an auxiliary operational amplifier for a pipeline analog-to-digital converter according to another embodiment of the present invention, where this embodiment includes the contents of the second embodiment, and further includes a second auxiliary operational amplifier, where the second auxiliary operational amplifier includes a sixth cascode P-type transistor pair MAP10, MAP11, a seventh cascode P-type transistor pair MAP8, MAP9, a fourth cascode N-type transistor pair MAP6, MAP7, a fifth cascode N-type transistor pair MAP4, MAP5, a first cascode P-type transistor pair MAP1, and MAP2, which are connected in sequence; the drains of the fifth cascode N-type transistor pair MAP4 and MAP5 are respectively connected with the drains of the first cascode P-type transistor pair MAP1 and MAP 2; the sources of the first common source P-type transistor pair MAP1 and MAP2 are connected with a first tail current P-type transistor MAP 0; the gates of the first common-source P-type transistor pair MAP1 and MAP2 are respectively connected with the gates of the first common-source N-type transistor pair M1 and M2. A fifth additional amplifier APN is further arranged between the seventh cascode P-type transistor pair MAP8 and MAP9, and the negative electrode and the positive electrode of the input end of the fifth additional amplifier APN are respectively connected with the sources of the seventh cascode P-type transistor pair MAP8 and MAP 9; and the negative electrode and the positive electrode of the output end of the fifth additional amplifier APN are respectively connected with the gates of the seventh cascode P-type transistor pair MAP8 and MAP 9. A sixth additional amplifier APP is further arranged between the fourth cascode N-type transistor pair MAP6 and MAP7, and a negative electrode and a positive electrode of an input end of the sixth additional amplifier APP are respectively connected with sources of the fourth cascode N-type transistor pair MAP6 and MAP 7; and the cathode and the anode of the output end of the sixth additional amplifier APP are respectively connected with the gates of the fourth cascode N-type transistor pair MAP6 and MAP 7.
The first auxiliary operational amplifier adopts a folded cascode structure, an input common-mode clamping MOS tube is added, and a direct current bias is provided through the MOS tube and the auxiliary operational amplifier, so that differential input differential output is realized, the gain is more than 30dB, and the bandwidth is more than 1 GHz. The second auxiliary operational amplifier circuit structure is similar to the first auxiliary operational amplifier circuit structure.
Therefore, under the condition of a narrow channel with very small intrinsic gain, the total operational amplifier gain can be improved by about 60dB-70dB by superposing two layers of auxiliary operational amplifiers. By the superposition of the gains of the main operational amplifier and the auxiliary operational amplifier, the ultrahigh gain of 120dB under a 60nm narrow channel is finally realized. Has a unity gain bandwidth above 5GHz and a bandwidth above 850MHz at 24dB gain.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (3)
1. An operational amplifier for a pipelined analog-to-digital converter, comprising: a first main operational amplifier, a second main operational amplifier, a first auxiliary operational amplifier and a second auxiliary operational amplifier,
the first main operational amplifier comprises a first cascode P-type transistor pair (M9, M10), a second cascode P-type transistor pair (M7, M8), a first cascode N-type transistor pair (M5, M6) and a first cascode N-type transistor pair (M1, M2) which are connected in sequence, and the sources of the first cascode N-type transistor pair (M1, M2) are connected with a first tail current N-type transistor (M0);
the second main operational amplifier comprises a third cascode P-type transistor pair (M14, M15) and a second cascode N-type transistor pair (M12, M13) which are connected in sequence, and the sources of the second cascode N-type transistor pair (M12, M13) are connected with a second tail current N-type transistor (M11);
wherein the drains of the first cascode P-type transistor pair (M9, M10) are connected to the drains of the third cascode P-type transistor pair (M14, M15) through compensation capacitors (Cc), respectively;
the first auxiliary operational amplifier includes a fourth cascode P-type transistor pair (MAN10, MAN11), a fifth cascode P-type transistor pair (MAN8, MAN9), a second cascode N-type transistor pair (MAN6, MAN7), a third cascode N-type transistor pair (MAN4, MAN5), a third cascode N-type transistor pair (MAN1, MAN2) connected in series;
wherein the drains of the fourth cascode P-type transistor pair (MAN10, MAN11) are connected to the drains of the third cascode N-type transistor pair (MAN1, MAN2), respectively; the sources of said third common-source N-type transistor pair (MAN1, MAN2) are connected to a third tail-current N-type transistor (MAN 0);
gates of the third cascode N-type transistor pair (MAN1, MAN2) are respectively connected with gates of the first cascode N-type transistor pair (M1, M2), a third additional Amplifier (ANN) is further arranged between the fifth cascode P-type transistor pair (MAN8, MAN9), and a negative input end and a positive input end of the third additional Amplifier (ANN) are respectively connected with sources of the fifth cascode P-type transistor pair (MAN8, MAN 9); the negative electrode and the positive electrode of the output end of the third additional Amplifier (ANN) are respectively connected with the gates of the fifth cascode P-type transistor pair (MAN8 and MAN 9);
a fourth additional Amplifier (ANP) is further arranged between the second cascode N-type transistor pair (MAN6, MAN7), and the negative electrode and the positive electrode of the input end of the fourth additional Amplifier (ANP) are respectively connected with the sources of the second cascode N-type transistor pair (MAN6, MAN 7); the negative electrode and the positive electrode of the output end of the fourth additional Amplifier (ANP) are respectively connected with the gates of the second cascode N-type transistor pair (MAN6 and MAN 7);
the second auxiliary operational amplifier comprises a sixth cascode P-type transistor pair (MAP10, MAP11), a seventh cascode P-type transistor pair (MAP8, MAP9), a fourth cascode N-type transistor pair (MAP6, MAP7), a fifth cascode N-type transistor pair (MAP4, MAP5), and a first cascode P-type transistor pair (MAP1, MAP2) which are connected in sequence;
wherein the drains of the fifth cascode N-type transistor pair (MAP4, MAP5) are connected to the drains of the first cascode P-type transistor pair (MAP1, MAP2), respectively; the sources of the first common source P-type transistor pair (MAP1, MAP2) are connected with a first tail current P-type transistor (MAP 0);
the gates of the first common source P-type transistor pair (MAP1, MAP2) are respectively connected with the gates of the first common source N-type transistor pair (M1, M2);
a fifth additional Amplifier (APN) is further arranged between the seventh cascode P-type transistor pair (MAP8, MAP9), and the negative electrode and the positive electrode of the input end of the fifth additional Amplifier (APN) are respectively connected with the sources of the seventh cascode P-type transistor pair (MAP8, MAP 9); the negative electrode and the positive electrode of the output end of the fifth additional Amplifier (APN) are respectively connected with the gates of the seventh cascode P-type transistor pair (MAP8 and MAP9), a sixth additional Amplifier (APP) is further arranged between the fourth cascode N-type transistor pair (MAP6 and MAP7), and the negative electrode and the positive electrode of the input end of the sixth additional Amplifier (APP) are respectively connected with the sources of the fourth cascode N-type transistor pair (MAP6 and MAP 7); and the cathode and the anode of the output end of the sixth additional Amplifier (APP) are respectively connected with the gates of the fourth cascode N-type transistor pair (MAP6 and MAP 7).
2. The operational amplifier for pipeline ADC as claimed in claim 1, wherein a first additional Amplifier (AN) is further disposed between the second cascode P-type transistor pair (M7, M8), and the negative and positive input terminals of the first additional Amplifier (AN) are respectively connected to the sources of the second cascode P-type transistor pair (M7, M8); and the cathode and the anode of the output end of the first additional Amplifier (AN) are respectively connected with the gates of the second cascode P-type transistor pair (M7 and M8).
3. Operational amplifier for pipeline analog-to-digital converters according to claim 1, characterized in that a second additional Amplifier (AP) is further arranged between the first cascode N-type transistor pair (M5, M6), and the negative and positive input terminals of the second additional Amplifier (AP) are respectively connected to the sources of the first cascode N-type transistor pair (M5, M6); and the cathode and the anode of the output end of the second additional Amplifier (AP) are respectively connected with the gates of the first cascode N-type transistor pair (M5 and M6).
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| CN110224700A (en) * | 2019-05-05 | 2019-09-10 | 西安电子科技大学 | A kind of high speed complementation type dual power supply operational amplifier |
| CN112564676B (en) * | 2019-09-25 | 2022-09-16 | 江阴圣邦微电子制造有限公司 | Comparator circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105846788A (en) * | 2016-03-25 | 2016-08-10 | 南京德睿智芯电子科技有限公司 | Operational amplifier |
| CN106452380A (en) * | 2016-09-30 | 2017-02-22 | 天津大学 | Gain enhanced full-differential amplifier structure for pipeline ADC |
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| US7852159B2 (en) * | 2007-07-24 | 2010-12-14 | Stmicroelectronics Pvt. Ltd. | Method for adaptive biasing of fully differential gain boosted operational amplifiers |
| JP6582594B2 (en) * | 2015-06-18 | 2019-10-02 | 富士電機株式会社 | Operational amplifier circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105846788A (en) * | 2016-03-25 | 2016-08-10 | 南京德睿智芯电子科技有限公司 | Operational amplifier |
| CN106452380A (en) * | 2016-09-30 | 2017-02-22 | 天津大学 | Gain enhanced full-differential amplifier structure for pipeline ADC |
Non-Patent Citations (2)
| Title |
|---|
| A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology;Thomas Liechti 等;《2008 IEEE Asia Pacific Conference on Circuits and Systems》;20090109;第22页 * |
| Thomas Liechti 等.A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology.《2008 IEEE Asia Pacific Conference on Circuits and Systems》.2009, * |
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