CN107888165B - Low-voltage bus signal latch - Google Patents
Low-voltage bus signal latch Download PDFInfo
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- CN107888165B CN107888165B CN201711362364.4A CN201711362364A CN107888165B CN 107888165 B CN107888165 B CN 107888165B CN 201711362364 A CN201711362364 A CN 201711362364A CN 107888165 B CN107888165 B CN 107888165B
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- 238000000034 method Methods 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 abstract description 12
- 230000007704 transition Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
- H03K3/02335—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a low-voltage bus signal latch, which consists of two low-threshold inverters, wherein a smaller forward feedback current is generated through a second inverter and flows back to the input end of a first inverter, so that the input current in the level transition period can be effectively increased, the circuit can quickly enter into the normal state of an input level, the input level is latched through feedback, and the last level signal is locked in a stable state until the next bus signal arrives. When the circuit has a latch function, the input of the bus node is always maintained in the state of the last input signal even when the bus is in an inactive state. The first and second inverters are formed by CMOS tubes with low threshold voltage, and the Schottky barrier diode used in the second inverter realizes normal operation of the bus signal latch circuit under low-voltage conditions.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a low-voltage bus signal latch.
Background
The bus signal latch is a positive feedback from the input port of the output signal through an inverter, which forms a bi-stable circuit (latched). The bus signal latch is used to prevent the following: the complementary metal oxide semiconductor CMOS gate input gets a floating value when it is connected to the tri-state network. In addition, both transistors in the gate should be turned on, whereby the power supply and ground will be shorted, which will destroy the CMOS gate. The bus signal latch prevents this by pulling the input up to the last valid logic level (0 or 1) on the network. Such circuits are typically arranged together in parallel with a tri-state network.
Bus signal latches composed of conventional threshold devices can operate at TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal Oxide Semicondutor) Logic levels, but with the development of technology and process and the requirements of low power consumption of equipment, power supply voltages are lower and lower, LVTTL (Low Voltage TTL) and LVCMOS (Low Voltage CMOS) are developed on the basis of TTL and CMOS respectively. The common supply voltages of LVTTL and LVMOS are 3.3V, 2.5V and 1.8V, and some high-speed chips such as processors can use lower logic levels.
When the bus signal latch formed by the conventional threshold device is applied to logic levels of LVTTL and LVCMOS or even lower voltage, the functional failure condition can occur. Usually, the minimum working voltage of the inverter must be higher than the sum of the threshold voltage of the N-tube and the threshold voltage of the P-tube, otherwise, the power supply will leak to the ground, and the circuit cannot work normally. The threshold voltage of the conventional device is about 0.7V, which limits the range of the power supply voltage. When the bus signal is from low jump, the pull-up path has no enough feedback current to flow, and has no latch function on the signal. If the bus signal is lost at this time, the port signal is not stationary and cannot remain in the last valid logic level state.
Accordingly, there is a need to provide a bus signal latch that can operate under low voltage power conditions to address the above-mentioned problems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a low-voltage bus signal latch, and in the invention, a Schottky diode with a lower conduction threshold value is used, so that the low-voltage bus signal latch still has a bus data latch function under the condition of lower logic level, and has better high-frequency noise resistance.
The invention adopts the following technical scheme: a low voltage bus signal latch circuit including a transistor P1, a transistor N1, a transistor P2, a transistor N2, and a diode D1;
the grid electrode of the transistor P1 is connected with the grid electrode of the N1 and is used as a data input end of the latch circuit, and the drain electrode of the transistor P1 is connected with the drain electrode of the N1 and is used as a data output end of the latch circuit; the source electrode of the P1 is connected with a power supply, and the source electrode of the N1 is grounded;
the grid electrode of the transistor P2 and the grid electrode of the transistor N2 are connected with the data output end, the source electrode of the transistor P2 is connected with a power supply, the source electrode of the transistor N2 is grounded, and the drain electrode of the transistor P2 is connected with the drain electrode of the transistor N2 and the data input end through the diode D1.
The transistors P1 and P2 are PMOS transistors, and the transistors N1 and N2 are NMOS transistors.
The diode is a schottky diode.
The anode of the diode is connected with the drain electrode of P2, and the cathode is connected with the data input end.
The transistors P1 and N1 constitute a first inverter, and the transistors P2 and N2 constitute a second inverter.
The transistors P1, N1, P2 and N2 are low-threshold devices, and the threshold voltage of the low-threshold devices is 0.2V-0.4V.
A method of latching a low voltage bus signal latch circuit, comprising the steps of:
the signal is input from the data input end, inverted by 180 degrees by the first inverter, and then continuously inverted by 180 degrees by the second inverter; wherein the high level is fed back to the data input end through the P2 tube and the Schottky diode, and the low level is fed back to the data input end through the N2 tube;
the signal is fed back to the data input end after being inverted for 360 degrees, so that the feedback results of the two inverters form a signal latch.
When the signal is changed from high to low, the transistor N2 is started to be locked in a pull-down mode;
when the signal goes from low to high, P2 and D1 start pull-up locking.
The latching method of the low-voltage bus signal latch circuit is used for low-voltage conditions, namely, the voltage range is 1.2V-1.8V.
When the signal input from the data input terminal is unchanged, the data output terminal continuously saves the last input state.
The invention has the beneficial effects and advantages that:
1. the invention combines two low threshold inverters to realize that the inverters can work normally under the condition of low power supply voltage.
2. The invention adopts the series Schottky barrier diode to realize the function of latching bus data under the condition of low power supply voltage.
Drawings
Fig. 1 is a low voltage bus signal latch circuit of the present invention.
FIG. 2 is a graph comparing the feedback current capability of the present invention with the prior art.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 shows a low voltage bus signal latch of the present invention, which includes two pairs of complementary inverters, P1 and N1 are one pair of complementary inverters, P2 and N2 form another pair of inverters, and D1 is a schottky barrier diode with low turn-on voltage. Both groups of inverters are composed of low-threshold devices, the threshold voltage of the low-threshold devices is about 0.3V, and the inverters can still work normally when the power supply is low to 1V. Under the condition of low voltage, assuming that a signal is input from a data input end, the signal is inverted by 180 degrees (node 1-2) by a first pair of inverters, then is continuously inverted by 180 degrees (node 3-4) by a second pair of inverters with a latch function, when the signal is changed from high to low, an N2 pipe is started to play a role in pull-down locking, and when the signal is changed from low to high, P2 and D1 pipes are started to play a role in pull-up locking. The signal is inverted 360 degrees and fed back to the input (node 4→1) so that the feedback results from both inverters form a signal latch that will continuously hold the last input state (either high or low asserted) when no change occurs in the external bus signal.
The invention adopts the Schottky barrier diode to utilize the metal-semiconductor junction as the Schottky barrier so as to generate the rectifying effect. The schottky barrier is a metal-semiconductor device which is made by using a noble metal (gold, silver, aluminum, platinum, etc.) a as a positive electrode, an N-type semiconductor B as a negative electrode, and a rectifying characteristic of the barrier formed on the contact surface of the two. Since a large number of electrons exist in the N-type semiconductor and only a very small number of free electrons exist in the noble metal, electrons diffuse from the B having a high concentration to the a having a low concentration. Obviously, there is no hole in metal a, i.e., there is no diffusion movement of holes from a to B. As electrons continue to diffuse from B to a, the concentration of electrons on the B surface gradually decreases, and the surface neutrality is broken, thus forming a potential barrier, and the electric field direction is b→a. However, under the action of the electric field, electrons in a also generate drift motion from a to B, so that the electric field formed due to diffusion motion is weakened. After a space charge region with a certain width is established, electron drift movement caused by an electric field and electron diffusion movement caused by different concentrations reach relative balance, and a Schottky barrier is formed.
This characteristic of the schottky barrier makes the turn-on voltage of the schottky diode low. When current flows through the common diode, the voltage drop of about 0.7-1.7V is generated, and the voltage drop of the Schottky barrier diode is only 0.15-0.4V. Taking the logic level of LVCMOS-1.8V power supply as an example, the voltage difference between the bus input port and the power supply is only 0.63V, the voltage difference exceeds the conduction voltage drop of the Schottky diode by 0.4V, a pull-up path formed by D1 and P2 is opened, and when the bus signal is high by low jump, feedback current flows through the pull-up path to latch the signal. Even when the bus signal is lost, the port signal will remain high.
This characteristic of the schottky barrier can increase the speed of switching. The schottky diode is switched from an on state, in which a forward current flows, to an off state in which it takes much less time than a conventional diode. The reverse recovery time of a common diode is about hundreds of ns, even a high-speed diode has tens of ns, and a schottky diode has no reverse recovery time, so the switching time of the schottky diode of a small signal is about tens of ps, and the switching time of a special large-capacity schottky diode is also tens of ps. EMI noise is caused by reverse current during the reverse recovery time due to the normal diode. The schottky diode can be switched immediately without reverse recovery time and reverse current, which can improve EMI noise problems of high speed interfaces.
Fig. 1 shows a low voltage bus signal latch circuit of the present invention, where P1, P2 are low threshold PMOS devices, N1, N2 are low threshold NMOS devices, and D1 is a schottky barrier diode.
Fig. 2 is a graph showing the feedback current capability of the bus signal latch of the present invention compared to the prior art bus signal latch during signal transitions at low voltage (vcc=1.8v). As is evident from the figure, the feedback current is only 2.118 mu A at the moment when the signal of the bus signal latch in the prior art is turned from low to high level, and the latch effect is not achieved at all, while the low-voltage bus signal latch in the invention can reach 56.24 mu A, the phase difference between the two is 26 times, and the latch effect is obvious.
Claims (7)
1. A low voltage bus signal latch circuit comprising a transistor P1, a transistor N1, a transistor P2, a transistor N2, and a diode D1;
the grid electrode of the transistor P1 is connected with the grid electrode of the N1 and is used as a data input end of the latch circuit, and the drain electrode of the transistor P1 is connected with the drain electrode of the N1 and is used as a data output end of the latch circuit; the source electrode of the P1 is connected with a power supply, and the source electrode of the N1 is grounded;
the grid electrode of the transistor P2 and the grid electrode of the transistor N2 are connected with the data output end, the source electrode of the transistor P2 is connected with a power supply, the source electrode of the transistor N2 is grounded, and the drain electrode of the transistor P2 is connected with the drain electrode of the transistor N2 and the data input end through a diode D1;
the diode is a Schottky diode;
the transistors P1 and N1 form a first inverter, and the transistors P2 and N2 form a second inverter;
the transistors P1, N1, P2 and N2 are low-threshold devices, and the threshold voltage of the low-threshold devices is 0.2V-0.4V.
2. The low voltage bus signal latch circuit of claim 1 wherein said transistors P1, P2 are PMOS transistors and said transistors N1, N2 are NMOS transistors.
3. The low voltage bus signal latch circuit of claim 1 wherein the diode has an anode connected to the drain of P2 and a cathode connected to the data input.
4. A method of latching a low voltage bus signal latch circuit, the method being implemented based on the low voltage bus signal latch circuit of claim 1, comprising the steps of:
the signal is input from the data input end, inverted by 180 degrees by the first inverter, and then continuously inverted by 180 degrees by the second inverter; wherein the high level is fed back to the data input end through the P2 tube and the Schottky diode, and the low level is fed back to the data input end through the N2 tube;
the signal is fed back to the data input end after being inverted for 360 degrees, so that the feedback results of the two inverters form a signal latch.
5. The latch method of the low voltage bus signal latch circuit according to claim 4, wherein:
when the signal is changed from high to low, the transistor N2 is started to be locked in a pull-down mode;
when the signal goes from low to high, P2 and D1 start pull-up locking.
6. The latch method of the low voltage bus signal latch circuit according to claim 4, wherein the latch method is used for a low voltage condition, i.e., a voltage range of 1.2V to 1.8V.
7. The latch method of the low voltage bus signal latch circuit according to claim 4, wherein the data output terminal continuously holds the last input state when the signal input from the data input terminal is unchanged.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711362364.4A CN107888165B (en) | 2017-12-18 | 2017-12-18 | Low-voltage bus signal latch |
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| CN201711362364.4A CN107888165B (en) | 2017-12-18 | 2017-12-18 | Low-voltage bus signal latch |
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| CN107888165A CN107888165A (en) | 2018-04-06 |
| CN107888165B true CN107888165B (en) | 2024-02-23 |
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| CN101013888A (en) * | 2006-01-31 | 2007-08-08 | 松下电器产业株式会社 | Latch circuit and semiconductor integrated circuit device with the same |
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