CN107887363B - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
CN107887363B
CN107887363B CN201610896700.2A CN201610896700A CN107887363B CN 107887363 B CN107887363 B CN 107887363B CN 201610896700 A CN201610896700 A CN 201610896700A CN 107887363 B CN107887363 B CN 107887363B
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layer
dielectric layer
circuit
electronic
stopper
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CN107887363A (en
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许习彰
刘鸿汶
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

An electronic package and a method for fabricating the same, comprising: the cutting device comprises an insulating layer, an electronic element embedded in the insulating layer, a dielectric layer arranged on the insulating layer, a circuit layer arranged on the dielectric layer and electrically connected with the electronic element, and a stop layer arranged in the dielectric layer and surrounding the circuit layer, so that the stop layer is used as a counterpoint mark in the singulation process, and the problems that the cutting position exceeds the error range and the product loss are solved.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to semiconductor packaging technology, and more particularly, to wafer level packaging technology.
Background
With the rapid development of the electronic industry, electronic products are also gradually moving toward multi-function and high-performance. In order to meet the requirement of miniaturization (miniature) of semiconductor packages, Wafer Level Packaging (WLP) technology is developed.
Fig. 1A to 1D are schematic cross-sectional views illustrating a conventional method for fabricating a wafer level semiconductor package 1.
As shown in fig. 1A, a thermal release tape (thermal release tape)11 is formed on a carrier 10.
Next, a plurality of semiconductor devices 12 are disposed on the thermal release adhesive layer 11, the semiconductor devices 12 have an active surface 12a and a non-active surface 12b opposite to each other, each of the active surfaces 12a has a plurality of electrode pads 120 thereon, and each of the active surfaces 12a is adhered to the thermal release adhesive layer 11.
As shown in fig. 1B, an encapsulant 13 is formed on the thermal release layer 11 to encapsulate the semiconductor device 12.
As shown in fig. 1C, a baking process is performed to harden the encapsulant 13, and the thermal release layer 11 loses its viscosity after being heated, so that the thermal release layer 11 and the carrier 10 can be removed together to expose the active surface 12a of the semiconductor device 12.
As shown in fig. 1D, a Redistribution layer (RDL) process is performed to form a Redistribution structure 14 on the encapsulant 13 and the active surface 12a of the semiconductor device 12, so that the Redistribution structure 14 is electrically connected to the electrode pads 120 of the semiconductor device 12. Next, an insulating passivation layer 15 is formed on the redistribution structure 14, and the insulating passivation layer 15 exposes a portion of the surface of the redistribution structure 14 for bonding with a conductive element 16 such as a solder ball. Finally, a singulation process is performed.
However, in the conventional method for manufacturing the semiconductor package 1, since the insulating passivation layer 15 on the redistribution structure 14 covers the scribe line L in the subsequent singulation process, the singulation process requires additional processes such as exposure, development and etching to remove the material of the insulating passivation layer 15 on the scribe line L, which results in high manufacturing cost of the semiconductor package 1, and the material of the insulating passivation layer 15 is easily remained on the scribe line L, thereby affecting the singulation quality.
In addition, the edge of the insulating protection layer 15 is prone to cause the erroneous recognition during the dicing, thereby causing the yield loss and the reliability problem.
Therefore, how to overcome the various problems of the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package and a method for manufacturing the same, which avoid the problems of cutting position exceeding the error range and product loss.
The electronic package of the present invention includes: an insulating layer; an electronic element embedded in the insulating layer; a dielectric layer formed on the insulating layer and the electronic element; a circuit layer formed on the dielectric layer and electrically connected to the electronic device; and a stop layer formed in the dielectric layer and surrounding the circuit layer.
The invention also provides a method for manufacturing the electronic package, which comprises the following steps: providing an insulating layer embedded with an electronic element; forming a dielectric layer on the insulating layer; and forming a circuit layer electrically connected with the electronic element on the dielectric layer, and forming a stop layer surrounding the circuit layer in the dielectric layer.
In the electronic package and the method for manufacturing the same, the electronic element is exposed at the second side of the insulating layer.
In the electronic package and the method for fabricating the same, the stopper layer is a conductor.
In the electronic package and the method for fabricating the same, the stopper layer is annular.
In the electronic package and the manufacturing method thereof, the stopper layer is electrically connected to the grounding portion of the circuit layer.
In the electronic package and the method for manufacturing the same, a build-up structure is further formed on the dielectric layer and the circuit layer, and the stopper layer is further formed in the build-up structure. For example, the stopper layer may have a cup-like or cylindrical longitudinal cross-sectional shape.
In view of the above, the stop layer is formed in the dielectric layer to serve as the index of the cutting path, so that the electronic package and the manufacturing method thereof of the invention do not need additional processes such as exposure, development and etching, thereby reducing the manufacturing cost and avoiding the problems of the cutting position exceeding the error range and poor yield in the singulation process.
In addition, the stop layer can also be used as a seal ring structure to prevent moisture from entering the dielectric layer, thereby avoiding the oxidation of the circuit layer.
And the stopping layer is formed around the circuit layer, so that when the circuit layer is impacted by external force in the sheet cutting process or after the sheet cutting process, the stopping layer can stop the external force from extending inwards to the circuit layer, thereby effectively avoiding the damage of the circuit layer, and improving the yield of products and the reliability of the products.
Drawings
Fig. 1A to 1D are schematic cross-sectional views illustrating a conventional semiconductor package manufacturing method; and
fig. 2A to 2D are schematic cross-sectional views illustrating a method for fabricating an electronic package according to the present invention;
FIG. 2E is a schematic cross-sectional view of the subsequent process of FIG. 2D;
FIG. 3A is an enlarged view of a portion of the alternate embodiment of FIG. 2B;
FIG. 3B is a partial top view of FIG. 2B; and
fig. 4A to 4B are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to another embodiment of the invention.
Description of the symbols:
1 semiconductor package 10,20 carrier
11 thermalization release glue layer 12 semiconductor element
12a,22a active side 12b,22b inactive side
120,220 electrode pad 13 packaging colloid
14 line redistribution structure 15,253 insulating protective layer
16,26 conductive element 2,4 electronic package
200 bonding layers of a release layer 201
21,41 stop layer 22 electronic component
23 insulating layer 23a first side
23b second side 24 wiring structure
240,250 dielectric layer 241,251 circuit layer
242,252 conductive blind hole 25 build-up structure
260 under bump metal layer 3 electronic device
40 perforation S cutting path
And L, cutting a street.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "first", "second", and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Please refer to fig. 2A to 2D, which are schematic cross-sectional views illustrating a method for fabricating an electronic package 2 according to the present invention.
As shown in fig. 2A, an insulating layer 23 having a first side 23a and a second side 23b opposite to each other is provided, and at least one electronic element 22 is embedded in the insulating layer 23.
In the present embodiment, the insulating layer 23 is formed by a molding compound (molding compound), a dry film (dryfilm), Poly-p-Polyoxazoles (PBO), Polyimide (PI) Ajinomoto build-up film (ABF), epoxy resin (epoxy), or photoresist.
In addition, the electronic component 22 is an active component, a passive component or a combination thereof, wherein the active component is a semiconductor chip and the passive component is a resistor, a capacitor or an inductor. For example, the electronic component 22 is a semiconductor wafer, which has an active surface 22a and an inactive surface 22b opposite to each other, the active surface 22a has a plurality of electrode pads 220, and the inactive surface 22b of the electronic component 22 is flush with the second side 23b of the insulating layer 23. It should be understood that in other embodiments, the second side 23b of the insulating layer 23 may cover the non-active surface 22b of the electronic element 22; alternatively, the electronic component 22 is inverted, i.e., the non-active surface 22b of the electronic component 22 exposes the first side 23a of the insulating layer 23, and the second side 23b of the insulating layer 23 is flush with or covers the active surface 22 a.
The insulating layer 23 and the electronic element 22 can be manufactured in various manners, for example, the insulating layer 23 is formed by molding (molding) or pressing (plating), but the invention is not limited thereto. Specifically, the electronic components 22 may be disposed on a support (not shown), the insulating layer 23 is formed to cover the electronic components 22, and the second side 23b of the insulating layer 23 is bonded to a carrier 20 before the support is removed. Alternatively, the electronic components 22 are disposed on the carrier 20 with their non-active surfaces 22b, and then the insulating layer 23 is formed to cover the electronic components 22.
In addition, a releasing layer 200 and a bonding layer 201 may be sequentially formed on the carrier 20, such that the second side 23b of the insulating layer 23 and the inactive surface 22b of the electronic component 22 are bonded to the bonding layer 201. Specifically, the release layer 200 is, for example, a thermal release tape (thermal release tape), a photosensitive release film or a mechanical release structure, and the bonding layer 201 is, for example, an adhesive.
As shown in fig. 2B, a Redistribution layer (RDL) process is performed to form a circuit structure 24 on the first side 23a of the insulating layer 23 and the electronic element 22, wherein the circuit structure 24 is electrically connected to the electronic element 22, and a stop layer 21 is formed on the circuit structure 24.
In the present embodiment, the circuit structure 24 includes a dielectric layer 240 and a circuit layer 241 disposed on the dielectric layer 240, and the circuit layer 241 is electrically connected to the electrode pad 220 of the electronic element 22 through a conductive via 242 extending in the dielectric layer 240.
In addition, the stopper layer 21 is disposed in the dielectric layer 240 and penetrates through the dielectric layer 240 to contact the first side 23A of the insulating layer 23, or as shown in fig. 3A, the stopper layer 21 does not penetrate through the dielectric layer 240, and the stopper layer 21 is a conductor, so that it can be manufactured together with the circuit layer 241; alternatively, the stop layer 21 and the circuit layer 241 are fabricated by different processes. Therefore, the material of the stop layer 21 and the material of the circuit layer 241 may be the same (e.g. copper) or different.
The stopper layer 21 has a vertical cross-sectional shape that is a cup shape with a wide top and a narrow bottom, but is not limited to the above.
In addition, the overall planar shape of the stopper layer 21 is a ring shape as shown in fig. 3B to surround the periphery of the wiring layer 241, and the dotted line shown in fig. 3B is used to indicate the planar profile of the electronic component 22. It should be understood that the outline and number of the stop layer 21 are not limited to those shown in fig. 3B, and may be other numbers or other shapes.
As shown in fig. 2C, a line redistribution layer (RDL) process is continuously performed to form a build-up structure 25 on the line structure 24, the stop layer 21 is further formed in the build-up structure 25, and a plurality of conductive elements 26 are formed on the build-up structure 25.
In the present embodiment, the build-up structure 25 has an insulating protection layer 253, a plurality of dielectric layers 250, a circuit layer 251 formed on the dielectric layers 250, and a plurality of conductive vias 252 disposed in the dielectric layers 250, and is electrically connected to the circuit layers 241,251 through the conductive vias 252, and the insulating protection layer 253 is formed on the outermost dielectric layer 250 and the circuit layer 251, so that a portion of the outermost circuit layer 251 is exposed out of the insulating protection layer 253, and the conductive elements 26 are bonded to the exposed portion of the circuit layer 251.
In addition, the stopper layer 21 is disposed in the dielectric layer 250, which can be fabricated together with the circuit layer 251, so that the material of the stopper layer 21 can be the same as or different from that of the circuit layer 251, and the longitudinal cross section of the stopper layers 21 is cup-shaped (i.e., the narrow end is stacked on the wide end).
In addition, when the circuit layers 251 and the stopper layers 21 on the same layer are fabricated, the stopper layer 21 on the lower layer can be used as an alignment between the circuit layer 251 and the stopper layer 21 on the upper layer, so as to facilitate the photolithography process (e.g., the process of patterning the circuit layer 251 and the conductive via 252).
In addition, the conductive elements 26 are solder balls, metal bumps or metal pillars, etc., and before forming the conductive elements 26, an Under Bump Metallurgy (UBM) 260 may be formed on the exposed portion of the circuit layer 251 to facilitate bonding the conductive elements 26.
As shown in fig. 2D, the carrier 20, the releasing layer 200 and the bonding layer 201 are removed, such that the non-active surface 22b of the electronic component 22 is exposed to the second side 23b of the insulating layer 23. Thereafter, a singulation process is performed along the dicing path S shown in fig. 2C to complete the fabrication of the electronic package 2, so that in a subsequent process, as shown in fig. 2E, the electronic package 2 can be bonded to an electronic device 3, such as a circuit board, through the conductive elements 26.
In the embodiment, the stopper layer 21 may be selectively electrically connected to the grounding portion of the circuit layer 241,251, so that the stopper layer 21 can be used as a grounding structure of a shielding (shielding) structure for Electromagnetic Interference (EMI).
In another embodiment, as shown in fig. 4A to 4B, the electronic package 4 is manufactured by first fabricating the circuit structure 24 and the build-up structure 25 (without forming the insulating protection layer 253), then penetrating each of the dielectric layers 240 and 250 to form at least one through hole 40, and then forming a filler (e.g., a metal material) in the through hole 40 as a stopper 41, such that the stopper 41 penetrates the circuit structure 24 and the build-up structure 25, or does not penetrate the circuit structure 24 and has a cylindrical longitudinal cross section. Finally, the insulating protection layer 253 and the conductive element 26 are formed and a singulation process is performed.
The manufacturing method of the present invention forms the stop layers 21,41 in the dielectric layers 240,250 to make the stop layers 21,41 as the alignment mark of the cutting path S, so compared with the prior art, the manufacturing method of the present invention does not need to additionally perform the processes of exposure, development and etching, etc., thereby reducing the manufacturing cost and avoiding the problems of the cutting position of the singulation process exceeding the error range and yield loss.
In addition, the stopper layers 21,41 may also serve as a seal ring structure to block moisture from entering the dielectric layers 240,250, thereby preventing the circuit layer 241,251 from being oxidized.
In addition, the stopping layers 21 and 41 are formed around the circuit layer 241,251, so that when the circuit layer is collided by external force during or after singulation, the stopping layers 21 and 41 stop the external force from extending inwards to the circuit layer 241,251, thereby preventing the circuit layer 241,251 from being damaged, and improving the yield and reliability of products.
The present invention provides an electronic package 2,4 comprising: an insulating layer 23, an electronic device 22, a dielectric layer 240, a circuit layer 241 and a stop layer 21, 41.
The electronic component 22 is embedded in the insulating layer 23.
The dielectric layer 240 is formed on the insulating layer 23 and the electronic element 22.
The circuit layer 241 is formed on the dielectric layer 240 and electrically connected to the electronic element 22.
The stopper layers 21,41 are located in the dielectric layer 240 and are annular around the circuit layer 241.
In one embodiment, the stop layers 21,41 are conductors.
In one embodiment, the stop layers 21 and 41 are electrically connected to the grounding portion of the circuit layer 241.
In one embodiment, the electronic packages 2 and 4 further include a build-up structure 25 formed on the dielectric layer 240 and the circuit layer 241, and the stopper layers 21 and 41 are further formed in the dielectric layer 250 of the build-up structure 25. For example, the stopper layer 21 may have a cup-like shape in a longitudinal section or the stopper layer 41 may have a columnar shape in a longitudinal section.
In summary, the electronic package and the manufacturing method thereof of the invention can avoid the problem that the cutting position of the singulation process exceeds the error range and the yield loss by using the design of the stop layer as the alignment mark of the cutting path, and can also be used as a seal ring structure to prevent moisture from entering the dielectric layer to avoid the oxidation of the circuit layer and prevent the external force from extending inwards to the circuit layer to avoid the damage of the circuit layer, thereby improving the yield of the product and the reliability of the product.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (12)

1. An electronic package, characterized in that the electronic package comprises:
an insulating layer;
an electronic element embedded in the insulating layer;
a dielectric layer formed on the insulating layer and the electronic element, wherein the dielectric layer has an upper surface, a lower surface and side surfaces adjacent to the upper surface and the lower surface;
a circuit layer formed on the dielectric layer and electrically connected to the electronic device; and
a stop layer formed in the dielectric layer and surrounding the circuit layer, wherein the stop layer is not exposed out of the side surface of the dielectric layer and is annular.
2. The electronic package of claim 1, wherein the stopper layer is a conductor.
3. The electronic package of claim 1, wherein the stopper layer is electrically connected to the ground portion of the wiring layer.
4. The electronic package of claim 1, further comprising a build-up structure formed on the dielectric layer and the wiring layer, and wherein the stopper layer is further formed in the build-up structure.
5. The electronic package of claim 4, wherein the stopper has a longitudinal cross-sectional shape that is cup-shaped.
6. The electronic package of claim 4, wherein the stopper has a cylindrical longitudinal cross-sectional shape.
7. A method of fabricating an electronic package, the method comprising:
providing an insulating layer embedded with an electronic element;
forming a dielectric layer on the insulating layer, wherein the dielectric layer has an upper surface and a lower surface which are opposite and side surfaces adjacent to the upper surface and the lower surface; and
forming a circuit layer electrically connected with the electronic element on the dielectric layer, forming a stop layer surrounding the circuit layer in the dielectric layer, wherein the stop layer is annular, and the circuit layer is not arranged between the stop layer and the side surface of the dielectric layer and is not exposed out of the side surface of the dielectric layer.
8. The method of claim 7, wherein the stop layer is a conductor.
9. The method of claim 7, wherein the stop layer is electrically connected to the grounding portion of the circuit layer.
10. The method of claim 7, further comprising forming a build-up structure on the dielectric layer and the circuit layer, wherein the stop layer is further formed in the build-up structure.
11. The method of claim 10, wherein the stop layer has a cup-shaped longitudinal cross-sectional shape.
12. The method of claim 10, wherein the stopper has a cylindrical longitudinal cross-sectional shape.
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