CN107885950A - A kind of method that overlapping via is deleted in PCB design - Google Patents
A kind of method that overlapping via is deleted in PCB design Download PDFInfo
- Publication number
- CN107885950A CN107885950A CN201711200343.2A CN201711200343A CN107885950A CN 107885950 A CN107885950 A CN 107885950A CN 201711200343 A CN201711200343 A CN 201711200343A CN 107885950 A CN107885950 A CN 107885950A
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- vias
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- traversed
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- Computer Hardware Design (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The present invention provides a kind of method that overlapping via is deleted in PCB design.The present invention deletes the overlapping via in PCB design with the following method：1) all vias in crawl design, form a via list；2) traversal step 1 successively) in obtained via, by the via traversed compared with other vias coordinate, if the coordinate of via and some other vias traversed is consistent, assert that the via traversed is overlapping via, the via of the traversal is added into processing list；3) after traveling through, all vias in batch delete processing list.This method forms automation tools by programming, one key deletes overlapping via, it instead of artificial macroscopic mode in prior art, deletion speed is fast, the degree of accuracy is high, using the present invention, overlapping via can be quickly deleted, substantially increases design efficiency, human cost is saved, while advantageously ensures that designing quality.
Description
Technical field
The present invention relates to circuit design field, more particularly, to the method that overlapping via is deleted in PCB design.
Background technology
In PCB design, because some maloperations can add overlapping via in the design, because via is to punch board
, overlapping via can increase cost, influence designing quality.Therefore, in the design, it is necessary to check and delete overlapping via,
Existing technical scheme is artificial visual inspection, and the method complex operation, efficiency are low, and is not easy to check, easily there is omission.
Commercially there are more money PCB design softwares at present, Cadence is not only as the most widely used software of industry
It possesses powerful function and more money related softwares support, also as it provides open second development interface and more
Perfect development language storehouse, user can be developed according to the needs of itself.
Skill language is a kind of high-level programming language based on C language and list processing language built in Cadence softwares,
Cadence provides abundant interactive function for skill language, studies skill language then authoring tool, input application can
To greatly improve operating efficiency.
The content of the invention
The present invention provides a kind of method that overlapping via is deleted in PCB design.This method forms automatic chemical industry by programming
Tool, a key delete overlapping via, instead of artificial macroscopic mode in prior art, deletion speed is fast, the degree of accuracy
Height, using the present invention, overlapping via can be quickly deleted, substantially increases design efficiency, human cost is saved, is advantageous to simultaneously
Ensure designing quality.
To achieve the above object of the invention, the present invention deletes the overlapping via in PCB design with the following method：
1) all vias in crawl design, form a via list；
2) traversal step 1 successively) in obtained via, by the via traversed compared with other vias coordinate, if this time
The coordinate for via and some other vias gone through is consistent, then assert that the via traversed is overlapping via, by the traversal
Via adds processing list；
3) after traveling through, all vias in batch delete processing list.
Wherein, need to handle list when traveling through in step 2), when traversing each via, by the via with remaining
Other vias in remaining list compare coordinate, and the remaining list is the list that the via that will be traversed is got rid of.If remaining columns
Table does not get rid of the via traversed, obtains the consistent via of coordinate in itself after the via contrast each traversed, then
Screening can not be realized.
Preferably, it need to be qualified via more than or equal to 5mil to set same network to cross pitch of holes.
Preferably, when software checks that it is 0 to obtain same network via distance values automatically, two vias detected are overlapping
Via,
Preferably, before step 1), in addition to：Write the script for deleting overlapping via；
The script is run in allegro design softwares.
Preferably, the development interface opened using software is programmed, and forms automation tools by programming, a key is deleted
Overlapping via.
The present invention forms automation tools by programming and realizes that a key deletes overlapping via, instead of in prior art
Artificial macroscopic mode, deletion speed is fast, the degree of accuracy is high, using the present invention, substantially increases design efficiency, saves people
Power cost, while advantageously ensure that designing quality.
Brief description of the drawings
Fig. 1 is situation existing for the overlapping via of the present invention；
Fig. 2 is that the present invention is checked to obtain property box using the show element functions of software to DRC ERROR.
Fig. 3 is the specific data of the overlapping via process of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained, belong to what the present invention protected
Scope.
The development interface that the present invention is opened using software is programmed, and forms automation tools by programming, a key is deleted
Overlapping via.Situation existing for overlapping via is illustrated in Fig. 1, contains multiple V＆V DRC ERROR in figure, wherein, DRC
ERROR refers to design rule error detection (DESIGN RULE CHECK ERROR), is the design that software is set according to user
Rule carries out the label symbol added after checking automatically, and V＆V DRC ERROR refer to one between DRC ERROR mesopores and hole
Individual classification.
As shown in Fig. 2 DRC ERROR, which are checked, using the show element functions of software can obtain right side side
Property box shown in frame, it can be seen that the design rule of user's setting in property box.
Constraint in Fig. 2:Thru Via to Thru Via Same Net Spacing are referred to：This DRC
The reason for ERROR occurs is to check to find Thru Via to Thru Via Same Net Spacing, i.e.,：With network via
Spacing does not meet the setting value in interval constraint value.
Specific data, as shown in square frame in Fig. 3, the numerical value that user sets in interval constraint value is 5mil, i.e., same to network
Crossing pitch of holes needs to be more than 5mil, and software checks that obtained actual value is 0 automatically, represents that it is 0 to cross pitch of holes for two, that is, is attached most importance to
Folded via.
The above-mentioned overlapping via that the present invention is directed to, the design procedure of the present invention is described below：
1), all vias in crawl design, form a via list；
2), traversal step 1 successively) in obtained via, by the via traversed compared with other vias coordinate, if this time
The coordinate for via and some other vias gone through is consistent, then assert that the via traversed is overlapping via, by the traversal
Via adds processing list；
3) after, traveling through, all vias in batch delete processing list.
Further, the list obtained in step 1) is the list of all vias composition.
Further, need to handle list when traveling through in step 2), it is when traversing each object, this is right
As the coordinate compared with other objects in the remaining list not comprising itself；If remaining list do not get rid of traverse should
Object, then obtain the consistent object of coordinate in itself after each object contrast, then can not realize screening.
The main implementation steps of the present invention include：
1) script for deleting overlapping via, is write；
2), the Run Script in allegro design softwares；
3) operation result, is checked.
Embodiment 1
For by the present invention application method and advantage sake of clarity, describe embodiment in detailed below：
1) allegro softwares, are opened, load (" del_via.il ") is inputted in order line, wherein, del_via.il is
Source files of program, this is ordered for loading procedure；
2) after, being returned as t in step 1), del_via is inputted in order line, wherein, del_via is to define in a program
Order, input this order after i.e. operation the present invention meaning program；
3) result is checked after, running.
By above step, you can complete to check and delete overlapping via.
The present invention forms automation tools by programming and realizes that a key deletes overlapping via, instead of in prior art
Artificial macroscopic mode, deletion speed is fast, the degree of accuracy is high, using the present invention, substantially increases design efficiency, saves people
Power cost, while advantageously ensure that designing quality.
Embodiment of above is only used for clearly illustrating technical scheme, and protection scope of the present invention includes
But be not limited to above-mentioned embodiment, it is any it is meeting claims of the present invention and any shown in technical field it is common
The appropriate change or replacement that technical staff is done to it, it should all fall into the scope of patent protection of the present invention.
Claims (5)
1. the method for overlapping via is deleted in a kind of PCB design, it is characterised in that comprise the following steps：
1) all vias in crawl design, form a via list；
2) traversal step 1 successively) in obtained via, by the via traversed compared with other vias coordinate, if this is traversed
Via and some other vias coordinate it is consistent, then assert that the via traversed is overlapping via, by the via of the traversal
Add processing list；
3) after traveling through, all vias in batch delete processing list.
2. according to the method for claim 1, it is characterised in that
Need to handle list when traveling through in step 2), when traversing each via, by the via and remaining list
Other vias compare coordinate, the remaining list is the list that the via that will be traversed is got rid of.
3. according to the method for claim 2, it is characterised in that
5mil need to be more than or equal to by crossing pitch of holes with network, then is qualified via.
4. according to the method for claim 2, it is characterised in that
When software checks that it is 0 to obtain same network via distance values automatically, two vias detected are overlapping via.
5. according to the method for claim 1, it is characterised in that
Before step 1), in addition to：Write the script for deleting overlapping via；The script is run in allegro design softwares.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711200343.2A CN107885950A (en) | 2017-11-24 | 2017-11-24 | A kind of method that overlapping via is deleted in PCB design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711200343.2A CN107885950A (en) | 2017-11-24 | 2017-11-24 | A kind of method that overlapping via is deleted in PCB design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107885950A true CN107885950A (en) | 2018-04-06 |
Family
ID=61775327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711200343.2A Pending CN107885950A (en) | 2017-11-24 | 2017-11-24 | A kind of method that overlapping via is deleted in PCB design |
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| Country | Link |
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| CN (1) | CN107885950A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110502848A (en) * | 2019-08-27 | 2019-11-26 | 京信通信系统（中国）有限公司 | Delete method, apparatus, equipment and the storage medium in back drill hole in PCB design figure |
Citations (5)
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| US20080010934A1 (en) * | 2006-07-13 | 2008-01-17 | Infineon Technologies Ag | Method and apparatus for automatic routing yield optimization |
| CN103164489A (en) * | 2011-12-19 | 2013-06-19 | 北京华大九天软件有限公司 | Quick comparative method for integrated circuit domain data base |
| CN103369868A (en) * | 2013-07-10 | 2013-10-23 | 华为技术有限公司 | Manufacturing method of PCB (Printed Circuit Board) and PCB |
| CN104754856A (en) * | 2013-12-30 | 2015-07-01 | 深圳市共进电子股份有限公司 | Method for arranging solder ball on printed circuit board |
| CN107092757A (en) * | 2017-04-28 | 2017-08-25 | 无锡军安电子科技有限公司 | The inspection method of pore pressure cut-off rule is crossed in a kind of PCB design |
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2017
- 2017-11-24 CN CN201711200343.2A patent/CN107885950A/en active Pending
Patent Citations (5)
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|---|---|---|---|---|
| US20080010934A1 (en) * | 2006-07-13 | 2008-01-17 | Infineon Technologies Ag | Method and apparatus for automatic routing yield optimization |
| CN103164489A (en) * | 2011-12-19 | 2013-06-19 | 北京华大九天软件有限公司 | Quick comparative method for integrated circuit domain data base |
| CN103369868A (en) * | 2013-07-10 | 2013-10-23 | 华为技术有限公司 | Manufacturing method of PCB (Printed Circuit Board) and PCB |
| CN104754856A (en) * | 2013-12-30 | 2015-07-01 | 深圳市共进电子股份有限公司 | Method for arranging solder ball on printed circuit board |
| CN107092757A (en) * | 2017-04-28 | 2017-08-25 | 无锡军安电子科技有限公司 | The inspection method of pore pressure cut-off rule is crossed in a kind of PCB design |
Non-Patent Citations (2)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110502848A (en) * | 2019-08-27 | 2019-11-26 | 京信通信系统（中国）有限公司 | Delete method, apparatus, equipment and the storage medium in back drill hole in PCB design figure |
| CN110502848B (en) * | 2019-08-27 | 2023-09-01 | 京信网络系统股份有限公司 | Method, device, equipment and storage medium for deleting back drilling holes in PCB design drawing |
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Application publication date: 20180406 |
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