CN107885301A - Electrification reset circuit - Google Patents
Electrification reset circuit Download PDFInfo
- Publication number
- CN107885301A CN107885301A CN201610876564.0A CN201610876564A CN107885301A CN 107885301 A CN107885301 A CN 107885301A CN 201610876564 A CN201610876564 A CN 201610876564A CN 107885301 A CN107885301 A CN 107885301A
- Authority
- CN
- China
- Prior art keywords
- pmos
- reset circuit
- electrification reset
- resistance
- nmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The invention discloses a kind of electrification reset circuit, including：Electrification reset circuit provided by the invention, including：The electrification reset circuit output end that first~second resistance, the first NMOS, the first~the 2nd PMOS and multiple series connection operational amplifiers are formed；First nmos source is grounded, and its grid is connected between first resistor and second resistance, its connection electrification reset circuit output end that drains；First PMOS source electrode and the second pmos source connection supply voltage, the first PMOS drain electrodes, the first PMOS grids and the 2nd PMOS grids connection second resistance one end, the second resistance other end are grounded by first resistor；2nd PMOS drain electrode connection the first NMOS drain electrodes.The present invention instead of the resistance of big resistance by the use of the first PMOS and the 2nd PMOS composition current mirrors as inverting amplifier load, resistance is greatlyd save under identical power consumption situation, and then reduce electrification reset circuit and take chip area, improve electrification reset circuit applicability.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of electrification reset circuit.
Background technology
All include electrification reset circuit (POR) in many chips of integrated circuit fields, the effect of electrification reset circuit be
System electrification and it is lower electric when produce reset signal, start for digital reset and various IP etc., make analog- and digital- module initial
Change to known state.It is existing to avoid " competing " that basic electrification reset circuit (POR) function can produce an internal reset pulse
As, and device is kept static, until supply voltage reaches a threshold value that can guarantee that normal work.Once supply voltage reaches
Threshold voltage, electrification reset circuit (POR) will discharge internal reset signal, and state machine starts to initialize.Electrification reset circuit
(POR) in system worked well all in open mode, therefore, the power consumption of electrification reset circuit (POR) is required and can not surpassed
Several μ A are crossed, power consumption is strict to be may require that less than 1 μ A.Strict demand of the electrification reset circuit (POR) to power consumption causes its needs
The very big resistance of resistance is set to realize its function as load.
As shown in figure 1, it is a kind of existing to meet power consumption requirements, loaded in 3rd resistor R3 as inverting amplifier, be
Reducing the 2nd NMOS N2 ids as far as possible can only be realized by increasing 3rd resistor R3 resistances, even with megohm (Mohm)
The resistance of rank is realized；Using megohm rank resistance as load, larger chip area can be taken, be unfavorable for device
Miniaturization, reduce the applicability of device.
The content of the invention
It is smaller to take chip area compared with prior art the technical problem to be solved in the present invention is to provide one kind, applicability
Higher electrification reset circuit.
In order to solve the above technical problems, electrification reset circuit provided by the invention, including：First~second resistance R1~
The electrification reset circuit that R2, the first NMOS N1, the first~the 2nd PMOS P1~P2 and multiple series connection operational amplifiers are formed
Output end；
First NMOS N1 source grounds, its grid are connected between first resistor R1 and second resistance R2, its connection that drains
Electrification reset circuit output end；
First PMOS P1 source electrode and the 2nd PMOS P2 source electrodes connection supply voltage, the first PMOS P1 drain electrodes, first
PMOS P1 grids and the 2nd PMOS P2 grids connection second resistance R2 one end, the second resistance R2 other ends pass through first resistor R1
Ground connection；
2nd PMOS P2 drain electrode connection the first NMOS N1 drain electrodes.
Further improve, in addition to be arranged at and be used for the device for improving trigger voltage precision between first resistor R1 and ground.
Wherein, the device for improving trigger voltage precision is the 2nd NMOS being connected between first resistor R1 and ground
First resistor R1 is connected after N2, the 2nd NMOS N2 source grounds, the 2nd NMOS N2 grids and drain electrode short circuit.
Wherein, a first NMOS N1 amplification.
Wherein, the first PMOS P1 and the 2nd PMOS P2 form current mirror.
Wherein, the 2nd PMOS P2 come from the first PMOS P1 as current mirror load, its image current.
Wherein, the first NMOS N1 and the 2nd PMOS P2 form inverting amplifier.
Wherein, electrification reset circuit output end has at least three series connection operational amplifier.
The present invention forms current mirror by the use of the first PMOS and the 2nd PMOS and instead of big resistance as inverting amplifier load
The resistance of value, the first NMOS and the 2nd PMOS form an inverting amplifier, wherein the 2nd PMOS is current mirror load, second
The electric current of PMOS mirror images comes from the first PMOS.The two can realize inverting amplifier function, therefore the first PMOS and the 2nd PMOS
Big valued resistor can be replaced by forming current mirror.It is about 768um^2 (width=according to measuring and calculating 1MOhm resistor areas
0.5um), the present invention greatlys save resistance using current-mirror structure under identical power consumption situation, and then reduces electrification reset electricity
Road takes chip area, improves electrification reset circuit applicability.
Brief description of the drawings
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings：
Fig. 1 is a kind of structural representation of existing electrification reset circuit (POR).
Fig. 2 is the structural representation one of electrification reset circuit of the present invention (POR).
Fig. 3 is the structural representation two of electrification reset circuit of the present invention (POR).
Description of reference numerals
R1~R4 is first~second resistance
N1, N2 are the first~the 2nd NMOS
P1, P2 are the first~the 2nd PMOS
OUT is the electrification reset circuit output end that multiple series connection operational amplifiers are formed
VPWR is supply voltage
Embodiment
As shown in Fig. 2 the embodiment of electrification reset circuit one provided by the invention, including：First~second resistance R1~R2,
The electrification reset circuit output that first NMOS N1, the first~the 2nd PMOS P1~P2 and multiple series connection operational amplifiers are formed
End；
First NMOS N1 source grounds, its grid are connected between first resistor R1 and second resistance R2, its connection that drains
Electrification reset circuit output end；
First PMOS P1 source electrode and the 2nd PMOS P2 source electrodes connection supply voltage, the first PMOS P1 drain electrodes, first
PMOS P1 grids and the 2nd PMOS P2 grids connection second resistance R2 one end, the second resistance R2 other ends pass through first resistor R1
Ground connection；
2nd PMOS P2 drain electrode connection the first NMOS N1 drain electrodes.
As shown in figure 3, another embodiment of electrification reset circuit provided by the invention, including：First~second resistance R1~
R2, the first~the 2nd NMOS N1~N2, the first~the 2nd PMOS P1~P2 and multiple series connection operational amplifiers form upper
Reset circuit output end；
First NMOS N1 source grounds, its grid are connected between first resistor R1 and second resistance R2, its connection that drains
Electrification reset circuit output end；
First PMOS P1 source electrode and the 2nd PMOS P2 source electrodes connection supply voltage, the first PMOS P1 drain electrodes, first
PMOS P1 grids and the 2nd PMOS P2 grids connection second resistance R2 one end, the second resistance R2 other ends pass through first resistor R1
Ground connection；
2nd PMOS P2 drain electrode connection the first NMOS N1 drain electrodes；
Also include being connected to the 2nd NMOS N2 between first resistor R1 and ground, the 2nd NMOS N2 source grounds, second
First resistor R1 is connected after NMOS N2 grids and drain electrode short circuit.
Wherein, a first NMOSN1 amplification.
Wherein, the first PMOS P1 and the 2nd PMOS P2 form current mirror.
Wherein, the 2nd PMOSP2 comes from the first PMOS P1 as current mirror load, its image current.
Wherein, the first NMOS N1 and the 2nd PMOS P2 form inverting amplifier.
Wherein, electrification reset circuit output end has at least three series connection operational amplifier.
Structure shown in two embodiments as described above, current mirror is formed as anti-phase by the use of the first PMOS and the 2nd PMOS
Amplifier load instead of the resistance of big resistance, and the first NMOS and the 2nd PMOS form an inverting amplifier, wherein second
PMOS is current mirror load, and the electric current of the 2nd PMOS mirror images comes from the first PMOS.The two can realize inverting amplifier function,
Therefore the first PMOS and the 2nd PMOS forms current mirror and can replace big valued resistor.According to measuring and calculating 1MOhm resistor areas about
For 768um2 (width=0.5um), 7680um2 chip area, this device that is highly advantageous to can then be saved by saving 10MOhm resistance
The miniaturization of part, the scope of application of electrification reset circuit can be greatly improved, widens application field.
The present invention is described in detail above by embodiment and embodiment, but these are not composition pair
The limitation of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Enter, these also should be regarded as protection scope of the present invention.
Claims (8)
- A kind of 1. electrification reset circuit, it is characterised in that including：First~second resistance (R1~R2), the first NMOS (N1), The electrification reset circuit output end that one~the 2nd PMOS (P1, P2) and multiple series connection operational amplifiers are formed；First NMOS (N1) source ground, its grid are connected between first resistor (R1) and second resistance (R2), its company of drain electrode Connect reset circuit output end；First PMOS (P1) source electrode and the 2nd PMOS (P2) source electrode connection supply voltage, the first PMOS (P1) drain electrodes, first PMOS (P1) grids and the 2nd PMOS (P2) grid connection second resistance (R2) one end, second resistance (R2) other end pass through first Resistance (R1) is grounded；2nd PMOS (P2) drain electrode connection the first NMOS (N1) drain electrodes.
- 2. electrification reset circuit as claimed in claim 1, it is characterised in that also include：It is arranged at first resistor (R1) and ground Between be used to improve the device of trigger voltage precision.
- 3. electrification reset circuit as claimed in claim 1, it is characterised in that：The device for improving trigger voltage precision is to connect It is connected on twoth NMOS (N2) of the first resistor (R1) between ground, the 2nd NMOS (N2) source ground, the 2nd NMOS (N2) grid First resistor (R1) is connected with after drain electrode short circuit.
- 4. electrification reset circuit as claimed in claim 1, it is characterised in that：First NMOS's (N1) plays amplification.
- 5. electrification reset circuit as claimed in claim 1, it is characterised in that：First PMOS (P1) and the 2nd PMOS (P2) is formed Current mirror.
- 6. electrification reset circuit as claimed in claim 5, it is characterised in that：2nd PMOS (P2) is used as current mirror load, its Image current comes from the first PMOS (P1).
- 7. electrification reset circuit as claimed in claim 1, it is characterised in that：First NMOS (N1) and the 2nd PMOS (P2) is formed Inverting amplifier.
- 8. electrification reset circuit as claimed in claim 1, it is characterised in that：Electrification reset circuit output end has at least three Series connection operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610876564.0A CN107885301A (en) | 2016-09-30 | 2016-09-30 | Electrification reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610876564.0A CN107885301A (en) | 2016-09-30 | 2016-09-30 | Electrification reset circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107885301A true CN107885301A (en) | 2018-04-06 |
Family
ID=61769332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610876564.0A Pending CN107885301A (en) | 2016-09-30 | 2016-09-30 | Electrification reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107885301A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115913196A (en) * | 2022-12-30 | 2023-04-04 | 广州慧智微电子股份有限公司 | Power-on reset circuit |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523709A (en) * | 1994-11-30 | 1996-06-04 | Sgs-Thomson Microelectronics, Inc. | Power-on reset circuit and method |
| US20020005740A1 (en) * | 1998-02-27 | 2002-01-17 | Hong Seok Kim | Power-up/power-down detection circuit |
| US20040041601A1 (en) * | 2002-08-30 | 2004-03-04 | Payne James E. | Power-on reset circuit |
| CN102468834A (en) * | 2010-11-08 | 2012-05-23 | 三星电子株式会社 | Power on reset circuit |
| CN103888126A (en) * | 2014-03-04 | 2014-06-25 | 东莞博用电子科技有限公司 | Practical level switching circuit |
| CN204190734U (en) * | 2014-11-05 | 2015-03-04 | 百利通科技（扬州）有限公司 | A kind of electrify restoration circuit |
| CN205377819U (en) * | 2015-10-10 | 2016-07-06 | 意法半导体研发(深圳)有限公司 | Electrify restoration circuit |
| CN105892553A (en) * | 2016-05-06 | 2016-08-24 | 芯原微电子(上海)有限公司 | Power supply voltage electrification detection circuit and achieving method for electrification detection |
-
2016
- 2016-09-30 CN CN201610876564.0A patent/CN107885301A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523709A (en) * | 1994-11-30 | 1996-06-04 | Sgs-Thomson Microelectronics, Inc. | Power-on reset circuit and method |
| US20020005740A1 (en) * | 1998-02-27 | 2002-01-17 | Hong Seok Kim | Power-up/power-down detection circuit |
| US20040041601A1 (en) * | 2002-08-30 | 2004-03-04 | Payne James E. | Power-on reset circuit |
| CN102468834A (en) * | 2010-11-08 | 2012-05-23 | 三星电子株式会社 | Power on reset circuit |
| CN103888126A (en) * | 2014-03-04 | 2014-06-25 | 东莞博用电子科技有限公司 | Practical level switching circuit |
| CN204190734U (en) * | 2014-11-05 | 2015-03-04 | 百利通科技（扬州）有限公司 | A kind of electrify restoration circuit |
| CN205377819U (en) * | 2015-10-10 | 2016-07-06 | 意法半导体研发(深圳)有限公司 | Electrify restoration circuit |
| CN105892553A (en) * | 2016-05-06 | 2016-08-24 | 芯原微电子(上海)有限公司 | Power supply voltage electrification detection circuit and achieving method for electrification detection |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115913196A (en) * | 2022-12-30 | 2023-04-04 | 广州慧智微电子股份有限公司 | Power-on reset circuit |
| CN115913196B (en) * | 2022-12-30 | 2024-02-02 | 广州慧智微电子股份有限公司 | Power-on reset circuit |
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| PB01 | Publication | ||
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Application publication date: 20180406 |