CN107884460B - Method for manufacturing ISFET device sensitive film based on standard CMOS process - Google Patents

Method for manufacturing ISFET device sensitive film based on standard CMOS process Download PDF

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CN107884460B
CN107884460B CN201710981238.0A CN201710981238A CN107884460B CN 107884460 B CN107884460 B CN 107884460B CN 201710981238 A CN201710981238 A CN 201710981238A CN 107884460 B CN107884460 B CN 107884460B
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passivation layer
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杨翎
张雪莲
张强
王琛瑜
节俊尧
俞育德
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Abstract

The invention discloses a method for manufacturing an ISFET device sensitive film based on a standard CMOS process, which comprises the following steps of preparing the sensitive film, wherein the step of preparing the sensitive film comprises the following steps: preparing an ISFET device containing an external passivation layer and a TiN layer structure below the passivation layer; etching part of the passivation layer, all the passivation layer, part of the TiN layer or all the TiN layer downwards from the outside of the ISFET device; and/or depositing a sensitive film. The method of the invention produces the high-quality sensitive film, and simultaneously, the distance between the sensitive film and the top metal layer of the device is proper, thus improving the sensitive capability of the device.

Description

Method for manufacturing ISFET device sensitive film based on standard CMOS process
Technical Field
The invention relates to post-process operation of integrated circuits in the semiconductor industry, in particular to a method for manufacturing an ISFET device sensitive film based on a standard CMOS process and an ISFET device.
Background
ISFET devices were originally proposed and successfully fabricated in 1970 by the netherlands scientist Piet Bergveld. In 1981, Matsuo in japan then tried the sensitivity performance of a sensitive film of various materials on the basis of the original structure. Limited to the semiconductor process level at the time, the fabricated ISFET devices were manually fabricated by researchers in their own laboratories using proprietary semiconductor equipment. With the subsequent innovation of semiconductor technology in industrial mode, the current integrated circuit type semiconductor process combined with circuit is generally performed by the related specialized foundries, such as station integrated circuit (TSMC), global foundation (glob) and core international (SMIC). In view of this model, Luc bouse et al proposed a method of fabricating ISFETs using standard processes, and the final fabrication was successful. After years of development, in 2004, Mark Milgrew firstly made a2 × 2 ISFET array by using a standard, in which various application circuits such as a read circuit, a row and column selection circuit, etc. were added. In the work of Mark Milgrew, it took the approach of borrowing the passivation layer in the standard process on the problem of sensitive film fabrication. The passivation layer materials in the standard process are different, but the topmost layer material is generally silicon oxynitride (SixNyO), and the structure of the silicon oxynitride material is just as different from that of silicon nitride, and the silicon oxynitride material has the sensitivity to hydrogen ions. The borrowing mode can save the manufacturing procedure of the sensitive film. However, since the passivation layer is manufactured in the factory for the purpose of protecting the circuits of the chip itself from the external environment, rather than for such electrochemical applications, it can be said that the passivation layer is not a good sensitive material, and since other materials, such as silicate glass, may be added under the passivation layer, and since the thickness of the passivation layer varies in various colors, the direct use of the passivation layer as a sensitive material is not desirable in many cases. However, most ISFET device researchers have adopted the passivation layer method in fabricating ISFET devices, because the simple deposition of the sensitive film on the passivation layer may not improve the chip sensitivity.
In the environment of standard process manufacturing, the ISFET cannot obtain excellent sensitivity performance due to passivation layer materials, structures and thicknesses.
Disclosure of Invention
Technical problem to be solved
In view of the shortcomings of the prior art, the present invention is directed to a method for fabricating a sensitive film of an ISFET device based on a standard CMOS process, so as to solve at least some of the problems of the prior art.
(II) technical scheme
According to an aspect of the present invention, there is provided a method for fabricating a sensitive film of an ISFET device based on a standard CMOS process, comprising preparing a sensitive film, wherein,
the preparation of the sensitive film comprises the following steps:
preparing an ISFET device containing an external passivation layer and a TiN layer structure below the passivation layer;
etching part of the passivation layer, all the passivation layer, part of the TiN layer or all the TiN layer downwards from the outside of the ISFET device; and/or depositing a sensitive film.
Further, when etching from the outside of the ISFET device to part of the TiN layer or etching the whole TiN layer, depositing the anti-penetration layer material and then depositing the sensitive film.
Further, when etching all passivation layers down from outside the ISFET device, the underlying TiN is used as a sensitive film or a sensitive film is deposited on the TiN layer.
Further, the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is arranged on the topmost layer.
Further, the etching is dry etching, and the thickness of the passivation layer etched when a part of the passivation layer is etched is 85% -95%.
Further, when the sensitive film is manufactured, the method comprises the following steps: and forming a sensitive layer pattern by adopting a photoresist stripping forming mode or a photoetching mode.
Further, when the TiN layer is further etched, the etching mode is dry etching (ICP) for reducing etching power, wet etching or RIE.
Further, the sensitive film is Si3N4，Al2O3，Ta2O5Or NiO.
Furthermore, the anti-seepage layer is TiN or SiO2The thickness of the anti-seepage layer is 10-1000 nm.
Further, if the process before depositing the sensitive film is etching, a sensitive layer pattern is formed by utilizing a stripping mode.
Further, if the process of depositing the sensitive film is depositing a material of the anti-penetration layer, a sensitive layer pattern is formed by utilizing a photoetching process.
According to another aspect of the present invention, there is provided an ISFET device including,
a TiN layer and an overlying outer passivation layer;
etching a part of the passivation layer downwards from the outside of the ISFET device, etching all the passivation layer, and etching to a channel structure formed by a part of the TiN layer or etching all the TiN layer;
and/or a sensitive film formed over the channel structure.
According to a further aspect of the present invention, there is provided a sensing membrane prepared by any one of the above methods.
(III) advantageous effects
The invention produces the high-quality sensitive film, and the distance between the sensitive film and the top metal layer of the device is proper, thereby improving the sensitive capability of the device.
Drawings
Fig. 1 is a structural diagram of a passivation layer in a standard process according to an embodiment of the invention.
Fig. 2 is a structural diagram of an ISFET device in a standard process according to an embodiment of the invention.
FIG. 3 is a diagram illustrating a structure of a passivation layer after most of the passivation layer is etched away according to an embodiment of the invention.
FIG. 4 is a diagram illustrating a structure of etching a passivation layer to a TiN layer according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating the structure of the deposited sensitive film after etching most of the passivation layer according to the embodiment of the present invention.
FIG. 6 is a structural diagram of a sensitive film deposited after etching to a TiN layer according to an embodiment of the invention.
Fig. 7 is a flow chart of the fabrication process of the device sensitive film without etching TiN material in the embodiment of the invention.
Fig. 8 is a structural diagram of a fabricated etched TiN material device sensitive film according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages solved by the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings in combination with the detailed description.
According to the basic concept of the invention, a method for manufacturing a sensitive film of an ISFET device is provided.
In a typical foundry CMOS process, the passivation layer structure generally consists of silicon dioxide and silicon nitride. Wherein silicon nitride is placed on top because of its high degree of compactness and insulation. In certain plant processes, materials such as silicate glass may also be used. In the detailed description of the present invention, the common top silicon nitride and bottom silicon dioxide structures are used as examples. Below the passivation layer is a top metal. The metal layers (all metal layers) are generally in a three-layer sandwich structure, and usually a thick Al/Cu alloy layer is sandwiched between two thin layers of TiN materials. The structure from the passivation layer surface layer to the top metal layer is shown in fig. 1.
Fig. 2 is a structural diagram of an ISFET device based on fig. 1. ISFET devices are almost identical in structure to MOSFETs, differing only in that the gate signal of the ISFET device needs to be chemically sensitive generated, and thus the gate of the ISFET device needs to be kept floating. Because the signal is sensed by the principle of capacitance, the metal layer except the top metal layer is small in area to avoid the influence of other metal layers on the signal. Like a MOSFET, the ISFET gate, after getting a signal, can convert the signal into a current, and this ability to convert from voltage to current is called transconductance. The surface charge is increased or decreased on the surface of the ISFET (passivation layer) due to the exchange and combination of ions. Meanwhile, the effect of the charges induces the top layer metal, and the top layer metal is converted into source-drain current of the ISFET device, so that the change of surface charges is reflected. ISFETs are commonly used for pH detection, and the change in the potential of the top metal due to their surface charge can be expressed as the following equation:
Figure GDA0002612762350000041
where k is the boltzmann constant, T is the temperature, q is the electronic charge, and α is a coefficient related to sensitivity. In general, the closer alpha is to 1, the better the sensitivity. From this courseware, the potential signal changes by a maximum of 59.2mV per unit change in pH, assuming a temperature of 298K.
In the specific process of manufacturing the sensitive film, various directions are selected. Firstly, the TiN material of the metal anti-diffusion impervious layer can be used as a sensitive material for the sensitivity of the hydrogen ion concentration of the solution. One way to make this is to directly etch the passivation layer material clean so that the device exposes the TiN material. Secondly, if it is planned to deposit other sensitive layer materials, such as Si3N4，Al2O3，Ta2O5And the like. The TiN material is not required to be exposed, a further etching process is omitted, and the required sensitive film is directly deposited or sputtered on the surface of the etched device. Besides, after the passivation layer material is etched to expose the TiN material, the sensitive layer is manufactured.
Fig. 3 is a structural view after the passivation layer is etched most. Assuming that the passivation layer has SiO2Material and Si3N4The material composition can be etched at a time under typical etching conditions to a residual thickness of about 10% of the total thickness. Specifically, if the passivation layer thickness is 1.8 μm in total, the etching is performed to the extent of approximately 100 and 200nm of remaining thickness.
Fig. 4 is a structural diagram in which the passivation layer is etched, but the TiN material is left. The TiN material functions in standard processes to prevent out-diffusion of the metal layer material (Al/Cu alloy or other). This property of TiN materials is also required in the process for the deposition of sensitive films. The TiN material in the standard process is very thin, so that with the ordinary etching method, it is likely that the TiN material is completely etched away due to insufficient selectivity. Therefore, when etching, special measures should be taken to prevent TiN from being etched. In a specific embodiment, one method is to use dry etching, such as ICP etching. ICP etching SiO2And Si3N4Etching conditions can be exchanged, most of the passivation layer material can be directly etched downwards at normal speed by using dry etching, then the power of a machine is reduced, the etching rate is slowed down, the etching capability of TiN is weakened, and the TiN material can be stored; another method is to use wet etching. The wet etching tends to have an extremely high selectivity, and has little damage to TiN under the condition of proper time control.
Fig. 5 and 6 are patterns after depositing a sensitive film. In the field of ISFETs, a commonly used sensing film is Si3N4，Al2O3，Ta2O5And the like. There are also a number of materials such as SnO2，WO2NiO and the like have also been studied. In order not to affect the quality of the metal layer in the original chip, a PECVD method can be used for depositing Si3N4The material is used as a sensitive film or Al is formed by using a low-temperature sputtering method2O3，Ta2O5A sensitive film of material. The material thickness may be between tens of nanometers to hundreds of nanometers. Fig. 5 is a deposition of a sensitive film without exposing the TiN, while fig. 6 is a deposition of a sensitive film after exposing the TiN material.
In the process of manufacturing the sensitive film, a lift-off process should be used as much as possible in order to form a desired pattern. Since in a standard CMOS chip there will inevitably be PAD areas that have already been etched, if a photolithographic etching method is used to form the pattern, there may be some damage to this area or chip breakdown due to the effect of charge. Alternatively, if the PAD area is not completely etched after being covered by the sensitive material, poor contact can result when Bonding. Meanwhile, as the etching process in the previous step necessarily has a photoetching process, the stripping process can be directly carried out under the condition that a glue type (such as negative glue) is specially selected, and the process steps are also saved.
Fig. 7 is a flow chart of the fabrication process. As shown in the figure, for a newly obtained CMOS chip, the passivation layer structure is assumed to be SiO2+Si3N4The structure of (2) should first etch most of the passivation layer material by using a normal dry etching process (generally, an ICP etching process), and specifically, it occupies about 90% of the thickness of the passivation layer. As stated above, there are two approaches here, 1) if one plans to use TiN material directly as the sensitive film, the etching power is reduced, or wet etching further etches the passivation layer clean, to get a clean TiN material surface, while avoiding excessive loss of TiN material. 2) If a non-TiN material surface is planned, further etching can be omitted and the required sensitive film materials, such as Si3N4, Al2O3, Ta2O5 and the like, are directly deposited. In addition, if desired under certain experimental conditions, the sensitive film can also be deposited after exposing the TiN material.
In addition to all the above fabrication methods, another method for fabricating the sensitive film is to directly over-etch the exposed Al/Cu (pure Al material or pure Cu material in some processes) alloy while etching the passivation layer. Since the device operates in a liquid environment, permeation effects may result if the sensitive layer is not sufficiently dense. The permeation effect may in turn lead to short circuits or inaccurate testing. It is therefore necessary to first deposit a barrier layer. Considering here the specific function of the TiN material itself (or other barrier material, such as TiW) in the standard process (preventing diffusion between the silicon substrate and the metal), it should be endeavored to continue to use the TiN material (or other barrier material, such as TiW). Fig. 8 shows a model of the device structure made by this method.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (4)

1. A method for preparing sensitive film of ISFET device based on standard CMOS process comprises preparing sensitive film,
the preparation of the sensitive film comprises the following steps:
preparing an ISFET device containing an external passivation layer and a TiN layer structure below the passivation layer;
etching all the passivation layer downwards from the outside of the ISFET device or etching to a part of the TiN layer, and using the TiN layer as a sensitive film;
wherein the etching comprises:
etching part of the passivation layer, wherein the thickness of the passivation layer is 85% -95% by dry etching;
and further etching the TiN layer, wherein the further etching mode comprises reducing etching power, dry etching, wet etching or reactive ion etching.
2. The method of claim 1, wherein the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is disposed on a topmost layer.
3. An ISFET device, comprising,
a TiN layer and an overlying outer passivation layer;
etching all the passivation layer downwards from the outside of the ISFET device or etching to a channel structure formed by a part of TiN layer; utilizing the TiN layer as a sensitive film;
wherein the etching comprises:
etching part of the passivation layer, wherein the thickness of the passivation layer is 85% -95% by dry etching;
and further etching the TiN layer, wherein the further etching mode comprises reducing etching power, dry etching, wet etching or reactive ion etching.
4. A sensitive film prepared by the method of any one of claims 1-2.
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US8642371B2 (en) * 2011-04-06 2014-02-04 Shamsoddin Mohajerzadeh Method and system for fabricating ion-selective field-effect transistor (ISFET)
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