CN107872282A - Receiver debugging apparatus - Google Patents
Receiver debugging apparatus Download PDFInfo
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- CN107872282A CN107872282A CN201610853050.3A CN201610853050A CN107872282A CN 107872282 A CN107872282 A CN 107872282A CN 201610853050 A CN201610853050 A CN 201610853050A CN 107872282 A CN107872282 A CN 107872282A
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- memory cell
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
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- Computer Networks & Wireless Communication (AREA)
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Abstract
The invention provides a kind of receiver debugging apparatus, including：Host computer, there is provided the test data tested corresponding to digital baseband signal；Memory cell, test data is stored；And switch unit, follow-up signal processing unit is connected between memory cell, RF processing unit and switched, wherein, PC control switch unit connects memory cell with follow-up signal processing unit when need to debug, for to follow-up signal processing unit input test data, in the case that data transfer bit wide between the storage bit wide and host computer of memory cell or between follow-up signal processing unit is inconsistent, in addition to：Bit wide format converting unit, memory cell is stored in for test data or carries out correspondingly bit width conversion when being read from memory cell, according to the receiver debugging apparatus provided, additional hardware entity circuit realiration debugging quantification, intensive is not increased, for quantitatively accurately debugging digital receiver baseband processing unit is highly effective.
Description
Technical field
The invention belongs to receiver technical field in communication system, more particularly to one kind is by storing playback mode to wireless
The receiver debugging apparatus that receiver is debugged.
Background technology
, it is necessary to carry out upper plate checking to the Base-Band Processing program of receiver in the development process of wireless communication receiver,
However, due to being communication, the sampled data that receiver baseband processing unit receives from radio frequency reception end every time is all
Random, uncertain value, this results in the place that when receiver system is debugged, can not accurately, quantitatively judge receiver
Manage program whether normal work, some small bug that report an error in processing routine are difficult to be found, for example, sampled data is in itself
When randomness, uncertainty cause that to data qualitative analysis need to be carried out, some small bug that report an error can not but be embodied, and be located
These small bug in reason program are but possible to seriously affect the Performance And Reliability of wireless digital receiver.
The content of the invention
The purpose of the present invention aims to provide a kind of receiver debugging apparatus, come solve the debugging process of wireless receiver due to
The problem of random, uncertain sampled data causes the Performance And Reliability of wireless digital receiver impacted.
According to above-mentioned purpose, implement a kind of receiver debugging apparatus of the present invention, connection is in receivers for exporting number
Between the RF processing unit and follow-up signal processing unit of word baseband signal, including：Host computer, there is provided corresponding to digital baseband
The test data that signal is tested；Memory cell, test data is stored；And switch unit, at follow-up signal
Reason unit, which is connected between memory cell, RF processing unit, to be switched, wherein, PC control switch unit will be deposited when need to debug
Storage unit connects with follow-up signal processing unit, for being deposited to follow-up signal processing unit input test data, memory cell
In the case that the wide data transfer bit wide between host computer or between follow-up signal processing unit of storage space is inconsistent, also wrap
Include：Bit wide format converting unit, it is stored in memory cell for test data or carries out correspondingly bit wide when being read from memory cell
Conversion.
Further, according to the receiver debugging apparatus of the present invention, also have the feature that, wherein, bit wide format turns
Unit is changed to include：Storage control；With in input data format converter, output data format converter one of or two,
Storage control, it is connected with memory cell；Input data format converter, is connected between storage control and host computer；
And output data format converter, it is connected between storage control and switch unit.
Further, according to the receiver debugging apparatus of the present invention, also have the feature that, wherein, storage control,
Input data format converter, and output data format converter, and switch unit and follow-up signal processing unit are set
In same integrated circuit, integrated circuit uses the chip of FPGA field programmable gate arrays.
Further, according to the receiver debugging apparatus of the present invention, also have the feature that, storage control, be used for
Produce to memory cell read control signal, write control signal；The test data exported by input data format converter is controlled to write
Enter memory cell；Test data is read from memory cell when need to debug.
Further, according to the receiver debugging apparatus of the present invention, also have the feature that, wherein, at follow-up signal
Reason unit includes at least one sub- subsequent processing units, and host computer includes upper pusher side memory cell, for storing test and debugging
Corresponding table, the test and debugging corresponding table include：At least one subelement debugging mode, correspond to needs specific aim debugging wherein respectively
Make a reservation for some sub- subsequent processing units；And different test datas corresponding to distinguishing from subelement debugging mode are defeated by memory cell
The playback mode gone out.
Further, according to the receiver debugging apparatus of the present invention, also have the feature that, playback mode is at least wrapped
Include：Speed control, include at the uniform velocity playback mode, burst playback mode；And/or playback mode control, comprising playback cycle pattern,
Single playback mode.
Further, according to the receiver debugging apparatus of the present invention, also have the feature that, wherein, memory cell is adopted
With any one in SDRAM, DDR, DDR2, DDR3.
Further, according to the receiver debugging apparatus of the present invention, also have the feature that, wherein, when starting debugging,
Host computer sends debugging mode switching command, makes switch unit connect memory cell with follow-up signal processing unit so that after
The input data of continuous signal processing module is the data that memory cell plays back out；Host computer sends out play-back command again, single from storage
The data read in member are sent to follow-up signal processing unit after necessary bit width conversion；Playback is sent in host computer to stop
Before instruction, memory cell will play back all test datas in a manner of predetermined playback.
The effect of the present invention and effect
The debugging that the data randomness received to solve wireless receiver is brought is uncertain, and existing usual way is volume
Outer one data transmitting/receiving equipment for being used for test and debugging of exploitation, the equipment send the sampled data determined and give receiver Base-Band Processing
Module, so that the input data determinization of receiver, and then the various performances of receiver processing routine are debugged, in search program
Potential bug.But the shortcomings that testing scheme is to need to develop extra test equipment, and cost is high, cycle length；When receiver
When Radio frequency Processing Unit, RF Processing Unit and baseband processing portion are in same circuit board, there is provided it is determined that test data it is particularly difficult.
Receiver debugging apparatus of the present invention, need not both develop extra test equipment, moreover it is possible to so that numeral
The test data determinization that the baseband processing portion of receiver is inputted, like this, easier find receiver processing journey
Small bug in sequence, the both debugging for digital base band processor part provide determination foundation, because multiplexing is utilized in receiver now
The same integrated circuit having, development cost is reduced again without developing extra test data transmission equipment, shortens exploitation week
Phase.
Brief description of the drawings
Fig. 1 is the structured flowchart of receiver debugging apparatus in a kind of debugging system of the invention.
Embodiment
Technical scheme is further illustrated with reference to the accompanying drawings and examples.
A kind of receiver debugging apparatus is present embodiments provided, connection is used to export digital baseband signal in receivers
Between RF processing unit and follow-up signal processing unit, including：Host computer, there is provided carried out corresponding to the digital baseband signal
The test data of test；Memory cell, the test data is stored；And switch unit, at the follow-up signal
Reason unit, which is connected between the memory cell, the RF processing unit, to be switched, wherein, PC control when need to debug
The switch unit connects the memory cell with the follow-up signal processing unit, for single to follow-up signal processing
Member inputs the test data, and the switch unit and the follow-up signal processing unit are set in same integrated circuit.
Fig. 1 is the structured flowchart of receiver debugging apparatus in a kind of debugging system of the invention.
In Fig. 1, receiver debugging apparatus connection RF processing unit in receivers and follow-up signal processing unit it
Between, the RF processing unit receives radio frequency signal from antenna, and down coversion, AD samplings etc. are carried out to the radio frequency signal
Reason, export digital baseband signal.
In receiver debugging apparatus, comprising host computer, memory cell, switch unit, further, examined in the present embodiment
Consider the data transfer bit wide between the storage bit wide of memory cell and host computer or between follow-up signal processing unit to differ
The situation of cause, receiver debugging apparatus also include bit wide format converting unit, bit wide format conversion it is single comprising storage control,
Input data format converter, and output data format converter.
Wherein, host computer using one be equipped with upper computer software computer, by physical connection interface (USB interface or
Ethernet interface etc.) it is connected with digital receiver baseband processing unit, there is provided tested corresponding to the digital baseband signal
Test data.
Memory cell, test data is stored, memory cell uses SDRAM memory in the present embodiment, the present invention
Middle memory cell is not limited using memories such as SDRAM, DDR, DDR2, DDR3 by this embodiment.
Switch unit, follow-up signal processing unit is connected between memory cell, RF processing unit and switched.Follow-up letter
The function that number processing unit is used to complete the digital base band processor algorithm of receiver is realized.
In the present embodiment, the storage bit wide and data transfer bit wide of memory cell are inconsistent, thus test data is write
Bit width conversion need to be carried out when reading memory cell.
Wherein, input data format converter is used for：The test data that host computer is transmitted is done necessary bit wide and become
Change, so as to be converted into the 16bit data that SDRAM memory cell can be stored directly, the 16bit data are issued into " SDRAM controls
Device " module.
Wherein, output data format converter is used for：The 16bit SDRAM playback of data of sdram controller output is turned
Change the test data of bit wide needed for the follow-up signal processing module of rear end into.
SDRAM storage controls are used for：Reading to SDRAM memory cell, the generation for the control signal such as writing out；Work as input
When data format conversion module has the test data to send, the test data of 16bit bit wides is write into SDRAM memory cell；When need
When being tested the playback test data from memory cell, 16bit test datas, realization pair are read from SDRAM memory cell
Read speed (at the uniform velocity or burst) and playback mode (circulation or single playback) control of 16bit data.
Switch unit switches switch and is used for：Debugged when receiver is in SDRAM memory cell playback test data
When, by " data of output data format converter output issue follow-up signal processing unit；When receiver is in normal work mould
During formula, the data that RF processing unit exports are issued into follow-up signal processing module.
Embodiment 1：
The RF processing unit output of receiver side is one group of parallel I/Q data, and I/Q bit wides are respectively 10bit；
In the present embodiment, test data needs a complete physical frame, amounts to 2647040 groups of I/Q datas；Test data
Need the data of one complete physical frame of continuous playback cycle at the uniform velocity.Specific playback mode of the invention for test data is not
Limit.
In the present embodiment, host computer, memory cell, switch unit and follow-up signal processing module and storage are controlled
Device, input data format converter, output data format converter are arranged on the circuit of the digital baseband processing unit of receiver
On plate, the chip of same FPGA field programmable gate arrays is multiplexed.
The interface shape of host computer and digital baseband processing unit is USB interface；The wide data bus of SDRAM memory cell
It is 4M to spend for 16bit, depth, and total memory capacity is 64Mbits.
When needing to debug receiver Base-Band Processing program, test data is handed down to storage by host computer by USB interface
Unit.Test data is stored in host computer with document form, and I/Q data are unsigned numbers in file, and each data account for a line,
I/Q data is interspersed.Specific form is as follows：
587 (I circuit-switched datas)
666 (Q circuit-switched datas)
983 (I circuit-switched datas)
337 (Q circuit-switched datas)
……
488 (I circuit-switched datas)
533 (Q circuit-switched datas)
Test data amounts to 5294080 (2647040*2=5294080) OK.Host computer procedure reads I/Q data line by line,
Digital baseband processing unit is issued with each I/Q data 16bit bit wides by USB interface.Due to the number of data lines for needing to store
(5294080) it is more than SDRAM storage depth (4M), if the 16bit data for directly transmitting USB interface are stored in
The data of one complete physical frame of inadequate storage are needed to return 10bit's to 16bit data convert by SDRAM, memory space
Data, bit width conversion is carried out, then all 10bit data are stitched together and are stored into SDRAM, in such cases
SDRAM enough (the 5294080*10bit of memory space<64M bit).Input data format converting module completes 10bit
Splicing function of the data to 16bit data.
The 16bit data spliced are stored in SDRAM memory cell under the control of SDRAM storage controls, wait completion one
After the storage of individual complete physical frame, SDRAM memory cell is in automatic Flushing status.
When starting debugging, host computer sends debugging mode switching command, makes switch unit by memory cell and follow-up signal
Processing unit connects so that the input data of follow-up signal processing module is the data that memory cell plays back out；
Host computer sends out play-back command again, and the 16bit data read from SDRAM memory cell turn by output data form
Mold changing block splits into each 10bit I/Q data, is at the uniform velocity sent to follow-up signal processing unit.
Before host computer sends playback halt instruction, memory cell will play back all test numbers in a manner of predetermined playback
According to.In the present embodiment, before host computer sends SDRAM playback halt instructions, SDRAM stores playback cycle always all
Test data.
As described above so far, the receiver debugging apparatus that the present embodiment is provided, predetermined way is completed to test data
Quantitative accurate send.
Embodiment 2：
Present invention also provides a kind of receiver debugging apparatus further to have the advantage that, when follow-up signal processing unit
When at least one FFT submodules are included during comprising at least one sub- subsequent processing units, such as in " follow-up signal processing unit ",
Receiver debugging apparatus can be realized carries out individually quantitative essence to some wherein predetermined or more sub- subsequent processing units
Really analysis.
Need to be that FFT submodules are adjusted to a sub- subsequent processing units in follow-up signal processing unit in the present embodiment 2
Examination test, the data bit width of the input data of the FFT submodules is respectively 12bit；Test data needs a complete 4K FFT
Input data, i.e. 4096*12=49152bit.
The input data that FFT submodules need is arranged to what non-at the uniform velocity burst mode cycled through by the application, will be tested
The playback mode of data is arranged to：The FFT submodules for having continuous 4096 clock cycle in every 10000 clock cycle input
Data.
In the present embodiment 2, by host computer, memory cell, switch unit and follow-up signal processing module, reception is arranged on
On the circuit board of the digital baseband processing unit of machine, the chip of same FPGA field programmable gate arrays is multiplexed.Host computer and number
The interface shape of word baseband processing unit is USB interface；The data of SDRAM memory cell on digital baseband processing unit plate are total
Line width is 16bit, and depth is 4M, and total memory capacity is 64Mbits.
In this case, when needing to debug the Base-Band Processing program of receiver, host computer is by USB interface test data
It is handed down to memory cell.Test data is stored in host computer with document form, and 4K FFT input datas are no symbols in file
Number, each data account for a line.Specific form is as follows：
1881
1000
1530
……
2047
1989
4096 row altogether.Host computer reads the input data of FFT submodules line by line, by USB interface with each data
16bit bit wides issue digital baseband processing unit.Because the number of data lines (4096) for needing to store is less than SDRAM memory cell
Storage depth (4M), therefore the 16bit data that directly can be transmitted USB interface are stored in SDRAM, thus in the present embodiment 2,
Above-mentioned input data format converter is not provided with, or sets but is needed without operation.
When starting debugging, host computer sends debugging mode switching command, and order switching switch switches over so that follow-up signal
The input data of processing module is the test data that SDRAM memory cell plays back out；After the completion of switching, host computer configuration is follow-up
The sub- subsequent processing units i.e. FFT submodules for needing debugging to test in signal processing unit, make the test data that playback goes out directly enter
Enter the FFT submodules；Finally, host computer sends burst cycle play-back command to SDRAM memory cell, and has configured burst-length
(4096) and interval time (10000 clock cycle), continuously from SDRAM memory cell in hereafter every 10000 clock cycle
4096 16bit test datas of middle reading, then 12bit data are split into by output data format converting module, after being sent to
Continuous signal processing module simultaneously enters FFT submodules.Before host computer sends SDRAM playback halt instructions, SDRAM memory cell
To all test datas of playback cycle always.
This process is to complete the quantitative accurate debugging to making a reservation for some FFT submodules in wireless communication receiver.
The actual conditions of the storage bit wide of foundation memory cell and the data transfer bit wide of writing, reading, to set bit wide
Format conversion unit, when without bit width conversion demand, the test data of host computer can be directly stored in memory cell, when write-in,
Wherein side or both sides are read, when having bit wide conversion demand, then storage control, and the conversion of input data form are set
In device, output data format converter one of or two.
The playback mode of above-mentioned test data is " burst cycle playback ", but the application is not so limited fixed, it is necessary to right
When one or more predetermined sub- subsequent processing units carry out test and debugging in follow-up signal processing unit, the application by with
Under targetedly play back mode to realize.
Host computer is stored with upper pusher side memory cell, for storing test and debugging corresponding table.The test and debugging corresponding table
Comprising：At least one subelement debugging mode；And different playback modes corresponding to distinguishing from subelement debugging mode.
Playback mode refers to the mode that test data is exported by memory cell, each seed units debugging mode difference
Corresponding to need wherein predetermined some sub- subsequent processing units that specific aim is debugged, corresponding playback mode, which can be preset, deposits
Storage is in the test and debugging corresponding table.The playback mode comprises at least：Speed control and/or playback mode control, the two difference
It is independent to participate in control or combine to participate in.Wherein, speed control includes at the uniform velocity playback mode, burst playback mode.Playback
Mode is controlled comprising playback cycle pattern, single playback mode.
The receiver debugging apparatus of the application, wireless receiver debugging efforts can be caused not increase additional hardware entity
In the case of circuit, the determinization of the test data of input is realized, so as to realize debugging quantification, intensive；Can also basis
Actual test needs, and freely converts the content and form of test data, single so as to difference of follow-up signal processing unit
Member carries out individually test checking, for quantitatively accurately debugging digital receiver baseband processing unit is highly effective.
It will be understood to one skilled in the art that the specification of the above is only one kind in the numerous embodiments of the present invention
Or several embodiments, and not use limitation of the invention.Any equivalent change for embodiment described above, modification with
And the technical scheme such as equivalent substitute, as long as meeting the spirit of the present invention, will all fall in claims of the present invention
In the range of protecting.
Claims (8)
1. a kind of receiver debugging apparatus, the RF processing unit that connection is used to export digital baseband signal in receivers is with after
Between continuous signal processing unit, including：
Host computer, there is provided the test data tested corresponding to the digital baseband signal；
Memory cell, the test data is stored；And
Switch unit, the follow-up signal processing unit is connected between the memory cell, the RF processing unit and cut
Change,
Wherein, switch unit described in the PC control is handled the memory cell and the follow-up signal single when need to debug
Member connection, for inputting the test data to the follow-up signal processing unit,
Data between the storage bit wide of the memory cell and the host computer or between the follow-up signal processing unit
In the case that transmission bit wide is inconsistent, in addition to：Bit wide format converting unit, it is single for the test data deposit storage
Member or from the memory cell reads when progress correspondingly bit width conversion.
2. receiver debugging apparatus as claimed in claim 1, it is characterized in that,
Wherein, the bit wide format converting unit includes：Storage control；With input data format converter, output data lattice
In formula converter one of or two,
Storage control, it is connected with the memory cell；
Input data format converter, it is connected between the storage control and the host computer；And
Output data format converter, it is connected between the storage control and the switch unit.
3. receiver debugging apparatus as claimed in claim 2, it is characterized in that,
Wherein, the storage control, the input data format converter, and the output data format converter, and
The switch unit and the follow-up signal processing unit are set in same integrated circuit, and the integrated circuit uses FPGA
The chip of field programmable gate array.
4. receiver debugging apparatus as claimed in claim 2, it is characterized in that,
Storage control, for producing to the memory cell read control signal, write control signal；Control is by input data form
The test data of converter output writes the memory cell；When need to debug test data is read from the memory cell.
5. receiver debugging apparatus as claimed in claim 1, it is characterized in that,
Wherein, the follow-up signal processing unit includes at least one sub- subsequent processing units,
Host computer includes upper pusher side memory cell, and for storing test and debugging corresponding table, the test and debugging corresponding table includes：
At least one subelement debugging mode, the wherein predetermined some sub- subsequent processing units for needing specific aim to debug are corresponded to respectively；
And
From the subelement debugging mode respectively corresponding to the playback side that is exported by the memory cell of the different test datas
Formula.
6. receiver debugging apparatus as claimed in claim 7, it is characterized in that,
The playback mode comprises at least：
Speed control, include at the uniform velocity playback mode, burst playback mode；And/or
Playback mode controls, and includes playback cycle pattern, single playback mode.
7. receiver debugging apparatus as claimed in claim 1, it is characterized in that,
Wherein, the memory cell uses any one in SDRAM, DDR, DDR2, DDR3.
8. receiver debugging apparatus as claimed in claim 1, it is characterized in that,
Wherein, when starting debugging, the host computer sends debugging mode switching command, make switch unit by the memory cell and
The follow-up signal processing unit connection so that the input data of the follow-up signal processing module is the memory cell playback
Data out；
Host computer sends out play-back command again, and the data read from memory cell are sent to follow-up letter after necessary bit width conversion
Number processing unit；
Before host computer sends playback halt instruction, memory cell will play back all test datas in a manner of predetermined playback.
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|---|---|---|---|
| CN201610853050.3A CN107872282A (en) | 2016-09-26 | 2016-09-26 | Receiver debugging apparatus |
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|---|---|---|---|
| CN201610853050.3A CN107872282A (en) | 2016-09-26 | 2016-09-26 | Receiver debugging apparatus |
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| CN107872282A true CN107872282A (en) | 2018-04-03 |
Family
ID=61752011
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Cited By (1)
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Application publication date: 20180403 |