CN107846222B - Gain self-calibration circuit of digital-analog converter - Google Patents
Gain self-calibration circuit of digital-analog converter Download PDFInfo
- Publication number
- CN107846222B CN107846222B CN201711133897.5A CN201711133897A CN107846222B CN 107846222 B CN107846222 B CN 107846222B CN 201711133897 A CN201711133897 A CN 201711133897A CN 107846222 B CN107846222 B CN 107846222B
- Authority
- CN
- China
- Prior art keywords
- dac
- circuit
- counter
- frequency point
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1019—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error by storing a corrected or correction value in a digital look-up table
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Abstract
The invention discloses a digital-to-analog converter (DAC) gain self-calibration circuit, comprising: the first counter counts an output clock of a crystal oscillator (XTAL for short) and controls the state jump of the DAC gain calibration circuit; the DAC control circuit outputs an input signal of the DAC; the frequency division circuit is used for completing the frequency division of an output clock of a voltage controlled oscillator (VCO for short); the second counter finishes counting the output clock of the frequency dividing circuit; the first lookup table outputs DAC gain control words corresponding to preset frequency points; the second lookup table outputs a DAC gain control word difference value of the target frequency point and the central frequency point; and the fine adjustment control circuit outputs the DAC gain control words of the target frequency point. The invention can change the capacitance value of the capacitance tube in the inductance capacitance oscillator by calibrating the DAC gain, finally change the frequency tuning curve of the VCO to obtain a target frequency signal, and can automatically finish the rapid calibration of the DAC gain of a plurality of frequency tuning curves according to the DAC gain calibration results of three frequency tuning curves.
Description
Technical Field
The invention relates to a gain self-calibration circuit of a digital-to-analog converter (hereinafter referred to as DAC), which is mainly applied to the fast self-calibration of the DAC gain in one or more frequency tuning curves in a direct modulation system in FSK modulation communication.
Background
The direct modulation method is a modulation method commonly used for frequency shift keying modulation, and in the direct modulation method, in order to obtain a modulation signal near a carrier wave meeting requirements, certain requirements are provided for the amplitude of a DAC output signal.
The current method for calibrating the DAC gain is to calibrate each frequency point respectively, and the calibration time is very long.
Disclosure of Invention
The invention aims to solve the technical problem of providing a DAC gain self-calibration circuit, which can calculate the DAC gain control words of all frequency points by only performing DAC gain calibration on three frequency points.
In order to solve the above technical problem, the DAC gain self-calibration circuit of the present invention comprises:
the first counter counts clocks output by the XTAL and controls a DAC gain self-calibration process; the counter is provided with five output signals, namely an output signal HF _ WAIT, an output signal HF, an output signal LF _ WAIT, an output signal LF and an output signal COMP;
after the VCO calibrates to a certain fixed frequency point, if the DAC gain self-calibration enable is turned on, the output signal HF _ WAIT is 1, the output signals HF, LF _ WAIT, LF and COMP are 0, and the counter starts to carry out accumulation counting on the input clock; when the count value is a first preset value, resetting the counter, accumulating and counting the input clock again, wherein the output signal HF is 1, and HF _ WAIT, LF and COMP are 0; when the count value reaches a second preset value, the counter is cleared, the input clock is accumulated and counted again, the output signal LF _ WAIT is 1, and HF _ WAIT, HF, LF _ WAIT and COMP are 0; when the count value is a first preset value, resetting the counter, accumulating and counting the input clock again, wherein the output signal LF is 1, and HF _ WAIT, HF, LF _ WAIT and COMP are 0; when the count value is a second preset value, resetting the counter, accumulating and counting the input clock again, wherein an output signal COMP is 1, and HF _ WAIT, HF, LF _ WAIT and LF are 0;
the DAC control circuit is used for controlling the DAC input signal; setting the DAC input signal to a maximum value when the first counter output signal HF _ WAIT is 1; switching the DAC input signal to a minimum value when LF _ WAIT is 1;
the frequency division circuit completes frequency division of a VCO output signal pll _ clk; the output signal of the frequency dividing circuit is pll _ div;
the second counter is cleared when the output signals HF _ WAIT and LF _ WAIT of the first counter are 1; accumulating and counting the output signal pll _ div of the frequency dividing circuit when the output signals HF and LF of the first counter are 1;
the first lookup table circuit saves the result acc _ cnt of the second counter when the output signal LF _ WAIT of the first counter is 1; when a first counter output signal COMP is 1, obtaining a DAC gain control word dacref of a preset frequency point (a highest frequency point, a lowest frequency point and a central frequency point in sequence); the lookup table is obtained by dividing the counting difference value of the two target frequency signals by the twice counting difference value of the second counter;
the second lookup table circuit outputs a DAC gain control word difference value dacref _ delta of the target frequency point relative to the central frequency point; because the frequency tuning curves of the phase-locked loop are multiple, the first lookup table only completes the calibration of three frequency points, and the lookup table completes the dacref _ delta value of each frequency tuning curve relative to the frequency tuning curve of the central frequency point through interpolation according to the gain control words corresponding to the highest frequency point, the central frequency point and the lowest frequency point;
one input signal of the fine adjustment control circuit is an output signal decref of the first lookup table circuit, the other output signal is an output signal dacref _ delta of the second lookup table circuit, and a gain control word final _ dacref of a target frequency point is output through addition operation;
fast calibration of DAC gain is required in a directly modulated FSK modulated communication system; therefore, the core idea of the invention is to calibrate the three frequency points, complete the DAC gain control word difference between any frequency point and the central frequency point by an interpolation method, then complete the DAC gain calibration of any frequency point by storing the DAC gain control word corresponding to the varactor of the central frequency point and the DAC gain control word difference of the target frequency point and the central frequency point, and when the frequency points are switched, can preset the DAC gain control word corresponding to the target frequency point to realize the fast calibration of the DAC gain.
Drawings
FIG. 1 is a circuit schematic of a DAC gain self-calibration circuit.
Detailed Description
FIG. 1 is a schematic block diagram of an embodiment of a DAC gain self-calibration circuit, which includes:
the first counter 1 counts the XTAL output clock and controls the DAC gain self-calibration process. The counter has five output signals, namely an output signal HF _ WAIT, an output signal HF, an output signal LF _ WAIT, an output signal LF and an output signal COMP.
After the VCO calibrates to a certain fixed frequency point, if the DAC gain self-calibration enable is turned on, the output signal HF _ WAIT is 1, the output signals HF, LF _ WAIT, LF and COMP are 0, and the counter starts to carry out accumulation counting on the input clock. When the count value is a first preset value, the counter is cleared, the input clock is accumulated and counted again, the output signal HF is 1, and HF _ WAIT, LF and COMP are 0. When the count value reaches a second preset value, the counter is cleared, the input clock is accumulated and counted again, the output signal LF _ WAIT is 1, and HF _ WAIT, HF, LF _ WAIT and COMP are 0. When the count value is a first preset value, the counter is cleared, the input clock is accumulated and counted again, the output signal LF is 1, and HF _ WAIT, HF, LF _ WAIT and COMP are 0. When the count value is a second preset value, the counter is cleared, the input clock is accumulated and counted again, the output signal COMP is 1, and HF _ WAIT, HF, LF _ WAIT and LF are 0.
The DAC control circuit 2 is used for controlling the DAC input signal. The DAC input signal DAC _ in is set to a maximum value, i.e. all bits are set to all 1, when the first counter output signal HF _ WAIT is 1. The DAC input signal DAC _ in is switched to a minimum value when LF _ WAIT is 1, i.e. all bits are set to all 0's.
The frequency dividing circuit 3 performs frequency division of the VCO output signal. The divider circuit output signal is pll _ div.
The second counter 4 clears the first counter output signals HF _ WAIT and LF _ WAIT when the counter is 1. The frequency divider circuit output signal pll _ div is counted up when the first counter output signals HF and LF are 1.
The first lookup table circuit 5 saves the result of the second counter when the first counter output signal LF _ WAIT is 1. And when the output signal COMP of the first counter is 1, obtaining the DAC gain control word dacref corresponding to the preset frequency point. The gain lookup table is obtained by dividing the theoretical count difference by the difference between two counts of the second counter. Because the frequency tuning curve of the phase-locked loop is multi-strip, in order to save time, the lookup table circuit only calibrates the highest frequency point, the lowest frequency point and the central frequency point.
The second lookup table circuit 6 outputs the DAC gain control word difference dacref _ delta of the target frequency point with respect to the center frequency point. The lookup table completes dacref _ delta values of each frequency tuning curve relative to the frequency tuning curve of the central frequency point through interpolation according to gain control words corresponding to the highest frequency point, the central frequency point and the lowest frequency point.
One input signal of the fine adjustment control circuit 7 is the first lookup table circuit output signal decref, and the other output signal is the second lookup table circuit output signal dacref _ delta, and the output signal is final _ dacref of the target frequency bin by the addition operation.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (3)
1. A digital-analog converter gain self-calibration circuit comprises a first counter, a DAC control circuit, a frequency division circuit, a second counter circuit, a first lookup table circuit, a second lookup table circuit and a fine tuning control circuit, and is characterized in that:
the input end of the first counter is connected with the XTAL output clock, the XTAL output clock is counted, and the DAC gain self-calibration process is controlled; the first counter is provided with five output signals which are an output signal HF _ WAIT, an output signal HF, an output signal LF _ WAIT, an output signal LF and an output signal COMP respectively;
the DAC control circuit is controlled by the output signals HF _ WAIT and LF _ WAIT of the first counter and is used for controlling an input signal DAC _ in of the DAC; setting dac _ in to a maximum value when the first counter output signal HF _ WAIT is 1; setting dac _ in to a minimum value when LF _ WAIT is 1;
the frequency division circuit is used for completing frequency division of a VCO output signal pll _ clk;
the second counter is controlled by output signals HF _ WAIT, HF, LF _ WAIT and LF of the first counter, and the counter is cleared when the output signals HF _ WAIT and LF _ WAIT of the first counter are 1; when the output signals HF and LF of the first counter are 1, accumulating and counting the output signals of the frequency division circuit;
the first lookup table circuit is controlled by an output signal COMP of the first counter, and outputs a DAC gain control word dacref of a preset frequency point when the output signal COMP of the first counter is 1; the first lookup table is obtained by dividing the counting difference of the two target frequency signals by the twice counting difference of the second counter;
the second lookup table circuit outputs a difference value dacref _ delta of the DAC gain control words of the target frequency point and the central frequency point;
and the fine adjustment control circuit outputs a DAC gain control word final _ dacref of a target frequency point by adding the output signal dacref of the first lookup table circuit and the output signal dacref _ delta of the second lookup table circuit.
2. The digital-to-analog converter gain self-calibration circuit of claim 1, wherein the second lookup table circuit outputs a difference value of the DAC gain control word of the target frequency point relative to the center frequency point; the first lookup table circuit completes DAC gain self-calibration of one frequency point at one time; and the second lookup table circuit completes the dacref _ delta value of each frequency tuning curve relative to the frequency tuning curve of the central frequency point by an interpolation method according to the gain control words of the highest frequency point, the lowest frequency point and the lowest frequency point output by the first lookup table circuit.
3. The digital-to-analog converter gain self-calibration circuit of claim 1, wherein: the DAC gain calibration of all the frequency points can be completed only by carrying out DAC gain calibration on the highest frequency point, the lowest frequency point and the central frequency point; and when the frequency points are switched, presetting the DAC gain control words corresponding to the target frequency points according to the stored DAC gain control words corresponding to the central frequency points and the difference value of the DAC gain control words of the target frequency points and the central frequency points, and realizing the quick calibration of the DAC gain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711133897.5A CN107846222B (en) | 2017-11-16 | 2017-11-16 | Gain self-calibration circuit of digital-analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711133897.5A CN107846222B (en) | 2017-11-16 | 2017-11-16 | Gain self-calibration circuit of digital-analog converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107846222A CN107846222A (en) | 2018-03-27 |
| CN107846222B true CN107846222B (en) | 2021-02-12 |
Family
ID=61678858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711133897.5A Active CN107846222B (en) | 2017-11-16 | 2017-11-16 | Gain self-calibration circuit of digital-analog converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107846222B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690899B (en) * | 2019-09-18 | 2023-03-31 | 广州粒子微电子有限公司 | Gain calibration method and module of high-pass path in two-point modulation phase-locked loop |
| CN113824444B (en) * | 2021-09-29 | 2023-07-28 | 天津津航计算技术研究所 | DAC output self-adaptive calibration device under wide temperature environment |
| CN113824445B (en) * | 2021-09-29 | 2023-07-28 | 天津津航计算技术研究所 | DAC output self-adaptive calibration method in wide temperature environment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1703831A (en) * | 2002-09-26 | 2005-11-30 | 阿纳洛格装置公司 | Integrated digital calibration circuit and digital to analog converter (DAC) |
| CN201623700U (en) * | 2009-12-30 | 2010-11-03 | 上海迦美信芯通讯技术有限公司 | Adjustable frequency synthesizer |
| CN102025373A (en) * | 2009-09-16 | 2011-04-20 | 复旦大学 | Digital background calibration circuit |
| CN102062618A (en) * | 2009-10-26 | 2011-05-18 | 福禄克公司 | System and method for calibrating a high resolution data acquisition system with a low resolution digital to analog converter |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6834183B2 (en) * | 2002-11-04 | 2004-12-21 | Motorola, Inc. | VCO gain tracking for modulation gain setting calibration |
| TWI419471B (en) * | 2010-11-19 | 2013-12-11 | Mstar Semiconductor Inc | Phase-locked loop with calibration function and calibration method thereof |
| GB2502557B8 (en) * | 2012-05-30 | 2015-10-21 | Cirrus Logic Int Semiconductor Ltd | Analogue-to-digital converter |
| CN103346787A (en) * | 2013-06-14 | 2013-10-09 | 浙江大学 | Phase-locked loop frequency synthesizer structure with automatic frequency correction |
| US9762250B2 (en) * | 2013-11-27 | 2017-09-12 | Silicon Laboratories Inc. | Cancellation of spurious tones within a phase-locked loop with a time-to-digital converter |
| US9413319B2 (en) * | 2014-03-24 | 2016-08-09 | Analog Devices, Inc. | Gain calibration |
| CN107005244B (en) * | 2017-02-08 | 2020-05-05 | 香港应用科技研究院有限公司 | Gain calibration of direct modulation synthesizer using look-up table search by decreasing count of overflow counter |
-
2017
- 2017-11-16 CN CN201711133897.5A patent/CN107846222B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1703831A (en) * | 2002-09-26 | 2005-11-30 | 阿纳洛格装置公司 | Integrated digital calibration circuit and digital to analog converter (DAC) |
| CN102025373A (en) * | 2009-09-16 | 2011-04-20 | 复旦大学 | Digital background calibration circuit |
| CN102062618A (en) * | 2009-10-26 | 2011-05-18 | 福禄克公司 | System and method for calibrating a high resolution data acquisition system with a low resolution digital to analog converter |
| CN201623700U (en) * | 2009-12-30 | 2010-11-03 | 上海迦美信芯通讯技术有限公司 | Adjustable frequency synthesizer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107846222A (en) | 2018-03-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8169270B2 (en) | Overlapping, two-segment capacitor bank for VCO frequency tuning | |
| EP2140549B1 (en) | Oscillator signal stabilization | |
| WO2018145326A1 (en) | Gain calibration for direct modulation synthesizer using look-up table searched by reduced count from overflow counter | |
| CN105577178B (en) | A kind of broadband low phase noise Sigma-Delta phaselocked loop | |
| US20150381344A1 (en) | Semiconductor device | |
| CN101090263B (en) | Frequency switching method | |
| CN107846222B (en) | Gain self-calibration circuit of digital-analog converter | |
| US7602256B2 (en) | Systems and techniques for auto-calibration and fast tuning of voltage controlled oscillators in phase-lock loops | |
| US20120013375A1 (en) | Frequency synthesizer device and modulation frequency displacement adjustment method | |
| JP4629310B2 (en) | Phase synchronization circuit | |
| US8004367B2 (en) | VCO control and methods therefor | |
| US9438301B2 (en) | PLL circuit, calibration method, and wireless communication apparatus | |
| US20080238495A1 (en) | Frequency synthesizer and wireless communication device utilizing the same | |
| WO2021212554A1 (en) | Advanced multi-gain calibration for direct modulation synthesizer | |
| CN105827238B (en) | System and method for calibrating dual-port phase-locked loop | |
| US10236898B2 (en) | Digital synthesizer, communication unit and method therefor | |
| US11356108B2 (en) | Frequency generator and associated method | |
| CN106817126B (en) | High-precision digital frequency locking ring with wide output frequency range and high frequency locking speed | |
| CN107005244B (en) | Gain calibration of direct modulation synthesizer using look-up table search by decreasing count of overflow counter | |
| CN101465645A (en) | Decimals/integer frequency divider | |
| WO2011152881A2 (en) | Dynamic voltage-controlled oscillator calibration and selection | |
| JP4335733B2 (en) | PLL frequency synthesizer, automatic frequency selection method of oscillator | |
| CN104242930A (en) | Frequency synthesizer for wireless receiving and sending system | |
| CN104092459A (en) | Fast locking frequency locking ring with automatic frequency control circuit | |
| US8222965B1 (en) | Radio frequency modulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information |
Inventor after: Zhou Yali Inventor after: Xiao Feng Yi Inventor after: Shu Haijun Inventor before: Zhou Yali Inventor before: Xiao Feng Yi |
|
| CB03 | Change of inventor or designer information |