CN107845682B - 对mos晶体管的衬底区域进行偏置 - Google Patents

对mos晶体管的衬底区域进行偏置 Download PDF

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CN107845682B
CN107845682B CN201710100661.5A CN201710100661A CN107845682B CN 107845682 B CN107845682 B CN 107845682B CN 201710100661 A CN201710100661 A CN 201710100661A CN 107845682 B CN107845682 B CN 107845682B
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A·蒙罗伊阿奎里
G·伯特兰德
P·卡瑟琳
R·保兰
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Abstract

公开了对MOS晶体管的衬底区域进行偏置。集成电子器件具有绝缘体上硅类型的衬底或者至少一个晶体管(TR)，该至少一个晶体管被形成在该衬底的半导体膜(1)中和该半导体膜上并且具有：第一导电类型的漏极区域(D)和源极区域(S)；第二导电类型的位于栅极区域下方的衬底区域(5)；以及在该源极区域(S)、该栅极区域(G)和该漏极区域(D)上的多个接触区。该晶体管(TR)还包括延伸区域(6)，该延伸区域横向地延续该衬底区域超出该源极区域(S)和该漏极区域(D)并且通过具有该第一导电类型的邻接区域(61)与该源极区域(S)相接触地邻接，从而电连接该源极区域和该衬底区域。

Description

对MOS晶体管的衬底区域进行偏置
技术领域
本发明的实施例涉及集成电路，并且更具体地涉及形成在绝缘体上硅类型(SOI)、尤其是部分耗尽型绝缘体上硅类型(PDSOI)的衬底上的MOS晶体管，并且更具体地涉及对这种类型的晶体管的性能的改善。
背景技术
通常，可以通过对晶体管的衬底区域进行偏置来改善晶体管的性能。例如，对晶体管的衬底区域进行偏置可以调节晶体管的阈值电压。
如众所周知的，SOI类型的衬底通常包括位于掩埋绝缘层(一般由术语BOX指代)下方的载体衬底，该掩埋绝缘层自身位于典型为硅的半导体膜下方。
在某些情况下，硅膜可以是完全耗尽型的，在这种情况下衬底被称为是完全耗尽型绝缘体上硅类型(FDSOI)。
在其他情况下，硅膜可以是部分耗尽型的，在这种情况下衬底被称为是部分耗尽型绝缘体上硅类型(PDSOI)。
无论SOI衬底的类型如何，晶体管的衬底区域(或更简单地“衬底”或“本体”)都位于SOI衬底类型的半导体膜中。
在PDSOI类型的衬底的情况下，晶体管的衬底(本体)可以是浮动的或者被连接成使得可以对其进行偏置。
在某些类似应用中，对晶体管的衬底(本体)具有良好控制是特别有利的。
存在多种用于对形成在绝缘体上硅类型、尤其是PDSOI类型的衬底上的晶体管的衬底进行偏置的解决方案，例如，在半导体膜的延伸超出晶体管的栅极区域的区域上形成触头。
然而，这种类型的解决方案具有缺点。一方面，该触头能够生成寄生效应(例如，寄生电容和电阻)，并且另一方面，为衬底形成特定接触区在表面占用和集成电路设计方面、尤其是对于互连而言并不有利。
在半导体膜的延伸超出栅极区域的区域上形成接触区妨碍了在栅极线的任一侧上对称地形成栅极接触区。然而，这种类型的安排允许对栅极区域的统一偏置。
针对控制晶体管的衬底(本体)的电势的良好折衷是使用其源极和衬底相连的晶体管。这被称为“连接本体(tied body)”，其通常被本领域技术人员使用并且避免了浮动衬底的缺点。
在这种连接本体的上下文中，如在图1中所展示的，用于减少接触区的数量的一种现有解决方案由晶体管T组成，该晶体管包括形成在与衬底区域接触的其源极区域RS中的区域R，该区域在这种情况下是p掺杂的，该源极区域在这种情况下是n掺杂的，该衬底区域在这种情况下是p掺杂的。
因此，常规地借助于形成在源极区域RS上的触头C对该源极区域进行偏置也可以使衬底偏置，而不必形成特定触头。
然而，这种解决方案与较小尺寸的晶体管不兼容，例如以0.13微米技术生产的晶体管。
这是因为现有注入技术不可以在源极区域RS中形成p掺杂区域R而不侵占漏极区域RD下方。此外，这将在晶体管的运行过程中冒很大的使晶体管降级的风险。
发明内容
因此，一个实施例提供了一种晶体管，该晶体管包括衬底区域，该衬底区域能够被偏置而不产生特定接触区，因此具有简化的互连布线、减小的寄生效应、并且与0.13微米或更小的技术兼容。
一个方面提供了一种集成电子器件，该集成电子器件包括绝缘体上硅类型的衬底，该衬底具有被安排在掩埋绝缘层上的半导体膜，该器件具有被安排在该半导体膜中和该半导体膜上的至少一个晶体管，该晶体管具有：第一导电类型的漏极区域和源极区域；属于第二导电类型并且位于栅极区域下方的膜区域(该膜区域形成该晶体管的衬底区域)；以及在该源极区域、该栅极区域和该漏极区域上的多个接触区。
根据此方面的一个一般特性，该晶体管还包括延伸区域，该延伸区域横向地延续该膜区域超出该源极区域和该漏极区域并且通过具有该第一导电类型的邻接区域与该源极区域相接触地邻接，从而电耦合该源极区域和该衬底区域。
因此，在晶体管的源极上形成至少一个触头与包括与该源极区域相接触地邻接的这个延伸区域的特定架构(布局)结合可以同时对源极和衬底区域进行偏置而不形成额外的接触区(其将需要产生特定互连)，并且这样做同时与例如130nm或更小的先进技术兼容。
该延伸区域例如包括与该衬底区域属于相同导电类型的连接部分以及导电区域，该连接部分将该衬底区域连接至该邻接区域，该导电区域至少部分地覆盖该邻接区域和该连接部分。
该导电区域可以包括具有非常低的电阻率(例如为小于5×10-5欧姆-厘米)的金属硅化物。
该连接部分可以具有第一部分和第二部分，该第一部分横向地延续该衬底区域，该第二部分垂直于该第一部分延伸并且接触该邻接区域。
根据一个实施例，该器件可以包括至少一对晶体管，所述至少一对晶体管中的每个晶体管的连接部分的第二部分从其对应的第一部分朝彼此延伸，从而形成公共第二连接部分，该器件还包括对这两个晶体管的公共邻接区域，该公共邻接区域从该公共第二连接部分延伸并且与这两个晶体管的源极区域相接触地邻接，从而电耦合这两个晶体管的源极区域以及其膜区域。
该器件可以包括多个晶体管，这些晶体管的栅极通过栅极材料线来互相电耦合，所述栅极材料线在每个晶体管的任一侧上垂直于这些晶体管的栅极区域延伸。
将还可以通过位于电路的互连部分中的金属层来连接这些晶体管的栅极。这个互连部分常规地已知为首字母缩略词BEOL(后段制程)。这些栅极材料区域可以接收触头，从而可以对晶体管的栅极进行偏置，并且因此有利地允许在互连的生产中有更大的灵活性。
附图说明
本发明的其他优点和特性将基于学习全部非限制性实施例的详细说明和附图而变得明显，在附图中
-图1如上所述展示了现有技术，
-图2至图5展示了本发明的实施例。
具体实施方式
图2、图3和图4根据一个实施例示意性地展示了具有晶体管TR的器件DIS。
图2是晶体管TR的从上来看的视图，图3是晶体管TR的在沿图2的轴线III-III的截面中的视图，并且图4是沿图2的轴线IV-IV的截面中的视图。
晶体管TR形成在部分耗尽型绝缘体上硅类型(PDSOI)的衬底上，该衬底具有弱掺杂的(在此为p类型的)半导体膜1，该半导体膜位于通常被本领域技术人员称为首字母缩略词BOX(掩埋氧化物)的掩埋绝缘层2上方，该掩埋绝缘层位于在这种情况下具有半导体本体50的载体衬底上方。
晶体管TR以常规方式具有栅极区域G、漏极区域D和源极区域S，并且由例如属于浅沟槽类型的绝缘区域RIS界定(STI：浅沟槽隔离)。
源极区域S和漏极区域D是通过在栅极区域G的任一侧上掺杂硅膜并且因为衬底在这种情况下具有部分耗尽型绝缘体上硅的类型而通过恢复外延来产生。源极区域S和漏极区域D重掺杂有第一导电类型，在这种情况下是n+型的导电性。
栅极区域G具有形成在绝缘栅级氧化物层41上的多晶硅区域40，该绝缘栅极氧化物层自身形成在半导体膜1上方。
多个绝缘间隔物42和43(出于简化原因在图2中未表示)形成在栅极区域G的任一侧上。
栅极区域G横向地(也就是说在晶体管的沟道区域的宽度W的方向上)在晶体管TR的源极区域和漏极区域的任一侧上延伸，从而形成第一栅极头部44和第二栅极头部45。该第一栅极头部和该第二栅极头部比栅极区域G的位于源极S与漏极D之间的部分更宽。这些栅极头部44和45有利地可以产生接触区从而对栅极区域G进行偏置。
常规地，源极区域S、漏极区域D和栅极区域G各自的上部分S1、D1和G1被硅化以形成接触区。
晶体管TR还具有膜区域5，该膜区域位于栅极区域下方并且掺杂有第二导电类型，在这种情况下是p型导电性。这个膜区域5形成晶体管TR的衬底区域。晶体管TR的沟道区域是在这个衬底区域5中形成的。
这个衬底区域5由延伸区域6横向地延续，该延伸区域延伸直到源极区域S。
延伸区域6具有p导电性的连接部分60和n导电性的邻接区域61。部分60和区域61相接触。
连接部分60包括第一部分601，该第一部分在第一栅极头部44下方并超出第一栅极头部44来延伸。
连接部分60还包括第二部分602，该第二部分从第一部分601垂直地延伸并且比衬底区域5和第一部分601掺杂得更重。
邻接区域61是n掺杂的并且从第二部分602垂直地延伸，从而相接触地将源极区域S在其整个长度上定界。因此，源极区域S和邻接区域61电连接(或耦合)。
导电区域7覆盖第二部分602并且部分地覆盖邻接区域61，从而使由连接部分602和邻接区域61形成的PN结短路。这个区域7在这种情况下是硅化区域，该硅化区域包括金属硅化物并且具有非常低的电阻率，典型地为小于5×10-5欧姆-厘米的电阻率。
另外，在硅化区域7下方的邻接区域61和第一部分601比这个邻接区域61和该第一部分601的位于硅化区域7之外的区掺杂得更重。这可以通过常规的方式改善电耦合。
因此，连接部分60邻接区域61相互电连接。另外，因为源极区域S和邻接区域61电连接(耦合)，借助于接触区S1对源极区域S的偏置还可以对位于源极S与漏极D之间的掺杂衬底区域5进行偏置。
因此有利地可以对衬底区域5进行偏置而不形成额外的接触区，同时与例如130nm或更小的先进技术兼容。
图5展示了具有第一晶体管TR1和第二晶体管TR2的器件DIS2，该第一晶体管和该第二晶体管类似于以上描述的并由图2和图3展示的晶体管TR。
第一晶体管TR1和第二晶体管TR2并排形成，因此其源极区域S2和S3面朝彼此。在这个实例中，这两个晶体管的栅极区域借助于两个栅极材料线L1和L2相互电连接，这两个栅极材料线在这两个晶体管的栅极头部上方垂直于这些栅极区域地在这两个晶体管TR1和TR2的任一侧上延伸。
这些晶体管的每一者的延伸区域的连接部分包括第二公共部分80，该第二公共部分在这两个晶体管TR1与TR2之间垂直于各个晶体管的连接部分的第一部分延伸。
这两个晶体管TR1和TR2还具有公共邻接区域81，该公共邻接区域从第二公共部分80延伸同时相接触地将这两个源极区域S1和S2的每一者定界。
在这种情况下包括非常低的电阻率的金属硅化物的导电区域9形成在第二公共部分80上，部分地在公共邻接区域81之上并且部分地在各个晶体管的第一部分之上。这个导电区域9可以使由第二公共部分80和公共邻接区域81形成的PN结短路。
因此，使用公共于两个晶体管的延伸区域可以有利地经由形成在源极区域上的触头对衬底进行偏置，同时节省甚至更多的空间。
具体地，通过避免产生常规的衬底接触区，简化了互连的布线，并且例如可以在晶体管TR1和TR2的栅极G1和G2的任一侧上(例如在垂直于每个晶体管的栅极区域延伸的这两个栅极材料线L1和L2上)产生更对称的接触区。

Claims (16)

1.一种集成电子器件，所述集成电子器件包括部分耗尽型绝缘体上硅类型的衬底，所述衬底具有被布置在掩埋绝缘层上的半导体膜(1)，所述器件具有被布置在所述半导体膜中和所述半导体膜上的至少一个晶体管(TR)，所述晶体管具有第一导电类型的漏极区域(D)和源极区域(S)；属于第二导电类型并且位于栅极区域(G)下方的膜区域(5)；以及在所述源极区域(S)、所述栅极区域(G)和所述漏极区域(D)上的多个接触区，所述晶体管(TR)还具有延伸区域(6)，所述延伸区域横向地延续所述膜区域超出所述源极区域(S)和所述漏极区域(D)并且通过具有所述第一导电类型的邻接区域(61)与所述源极区域(S)相接触地邻接，其中所述延伸区域(6)包括与所述膜区域属于相同导电类型的连接部分(601，602)以及导电区域(7)，所述连接部分将所述膜区域(5)连接至所述邻接区域(61)，所述导电区域至少部分地覆盖所述邻接区域(61)和所述连接部分(601，602)。
2.根据权利要求1所述的器件，其中，所述导电区域(7)包括金属硅化物并且具有小于5×10-5欧姆-厘米的电阻率。
3.根据权利要求1和2之一所述的器件，其中，所述连接部分具有第一部分(601)和第二部分(602)，所述第一部分横向地延续所述膜区域，所述第二部分垂直于所述第一部分延伸并且接触所述邻接区域(61)。
4.根据权利要求3所述的器件，包括至少一对晶体管(TR1，TR2)，所述至少一对晶体管中的每个晶体管的连接部分的第二部分从其对应的第一部分朝彼此延伸，从而形成公共第二连接部分(80)，所述器件还包括对这两个晶体管的公共邻接区域(81)，所述公共邻接区域从所述公共第二连接部分(80)延伸并且与这两个晶体管(TR1，TR2)的源极区域(S1，S2)相接触地邻接，从而电耦合这两个晶体管(TR1，TR2)的源极区域(S2，S3)以及其膜区域。
5.根据权利要求1所述的器件，其中所述至少一个晶体管包括一对晶体管，其中所述一对晶体管中的每个晶体管的栅极区域通过垂直于所述晶体管的所述栅极区域延伸的栅极材料线来互相电耦合。
6.根据权利要求1至2之一所述的器件，包括多个晶体管，所述晶体管的栅极区域通过栅极材料线(L1，L2)来互相电耦合，所述栅极材料线在每个晶体管的任一侧上垂直于所述晶体管的栅极区域延伸。
7.一种集成电子器件，包括：
晶体管，具有在部分耗尽型绝缘体上硅(PDSOI)衬底的半导体层内的源极区域、漏极区域和体区域，所述体区域位于所述源极区域与所述漏极区域之间，其中所述源极区域的第一侧面向所述体区域；
边界区域，在所述半导体层内并且与所述源极区域接触，其中所述源极区域的与所述第一侧相对的第二侧面向所述边界区域；以及
连接区域，在所述半导体层内在第一端处与所述体区域接触、以及在第二端处与所述边界区域进一步接触；
其中所述源极区域和所述边界区域掺杂有第一导电类型，并且所述体区域和所述连接区域掺杂有第二导电类型；以及
电连接，与所述连接区域的至少一部分和所述边界区域的至少一部分两者接触。
8.根据权利要求7所述的器件，其中所述连接区域的所述部分比所述体区域更重掺杂。
9.根据权利要求7所述的器件，其中所述边界区域的所述部分比所述边界区域的与所述源极区域相邻的剩余部分更重掺杂。
10.根据权利要求7所述的器件，其中所述电连接是金属硅化物，其具有小于5×10-5欧姆-厘米的电阻率。
11.根据权利要求7所述的器件，其中所述体区域、所述源极区域和所述边界区域具有在第一方向上彼此平行延伸的较长侧，并且其中所述连接区域具有在垂直于所述第一方向的第二方向上延伸的较长侧。
12.一种集成电子器件，包括：
第一晶体管，具有在部分耗尽型绝缘体上硅(PDSOI)衬底的半导体层内的第一源极区域、第一漏极区域和第一体区域，所述第一体区域位于所述第一源极区域与所述第一漏极区域之间，其中所述第一源极区域的第一侧面向所述第一体区域；
第二晶体管，具有在所述PDSOI衬底内的第二源极区域、第二漏极区域和第二体区域，所述第二体区域位于所述第二源极区域与所述第二漏极区域之间，其中所述第二源极区域的第一侧面向所述第二体区域；
边界区域，在所述半导体层内并且与所述第一源极区域和所述第二源极区域中的每一个接触，其中所述第一源极区域和所述第二源极区域中的每一个的、与所述第一侧相对的第二侧面向所述边界区域；以及
连接区域，在所述半导体层内在第一端处与所述第一体区域接触、在第二端处与所述第二体区域接触、以及在中间与所述边界区域进一步接触；
其中所述第一源极区域和所述第二源极区域以及所述边界区域掺杂有第一导电类型，并且所述第一体区域和所述第二体区域以及所述连接区域掺杂有第二导电类型；以及
电连接，与所述连接区域的至少一部分和所述边界区域的至少一部分两者接触。
13.根据权利要求12所述的器件，其中所述连接区域的所述部分比所述第一体区域和所述第二体区域更重掺杂。
14.根据权利要求12所述的器件，其中所述边界区域的所述部分比所述边界区域的与所述第一源极区域和所述第二源极区域相邻的剩余部分更重掺杂。
15.根据权利要求12所述的器件，其中所述电连接是金属硅化物，其具有小于5×10-5欧姆-厘米的电阻率。
16.根据权利要求12所述的器件，其中所述第一体区域和所述第二体区域、所述第一源极区域和所述第二源极区域、以及所述边界区域具有在第一方向上彼此平行延伸的较长侧，并且其中所述连接区域具有在垂直于所述第一方向的第二方向上延伸的较长侧。
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