CN107845567A - Graphene double heterojunction and preparation method thereof - Google Patents

Graphene double heterojunction and preparation method thereof Download PDF

Info

Publication number
CN107845567A
CN107845567A CN201710876844.6A CN201710876844A CN107845567A CN 107845567 A CN107845567 A CN 107845567A CN 201710876844 A CN201710876844 A CN 201710876844A CN 107845567 A CN107845567 A CN 107845567A
Authority
CN
China
Prior art keywords
sic
graphene
preparation
double heterojunction
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710876844.6A
Other languages
Chinese (zh)
Inventor
辛斌
王香灵
杨文耀
刘文波
夏继宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing University of Arts and Sciences
Original Assignee
Chongqing University of Arts and Sciences
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chongqing University of Arts and Sciences filed Critical Chongqing University of Arts and Sciences
Priority to CN201710876844.6A priority Critical patent/CN107845567A/en
Publication of CN107845567A publication Critical patent/CN107845567A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02527Carbon, e.g. diamond-like carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02609Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Abstract

The present invention relates to a kind of graphene double heterojunction and preparation method thereof, wherein, preparation method includes:(a) backing material is chosen;(b) 3C SiC epitaxial layers are grown in the substrate material surface;(c) the 3C SiC epitaxial layers are pyrolyzed and form graphene layer to complete the preparation of the graphene double heterojunction.Graphene prepared by the present invention/3C SiC/4H SiC double-heterostructures, band difference is different very big, but the Lattice Matching between graphene/3C SiC/4H SiC threes is very good, therefore it is prepared by the double heterojunction that low defect can be achieved that transition zone is not needed between three;All growth courses of the present invention can be completed with an equipment, be advantageous to the drop of cost.

Description

Graphene double heterojunction and preparation method thereof
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of graphene double heterojunction and a kind of graphene are double heterogeneous The preparation method of knot.
Background technology
The contact transition region appellation hetero-junctions that a kind of semiconductor material growing is formed on another semi-conducting material, according to It is divided into homotype hetero-junctions (Pp or Nn) or special-shaped (Pn or Np) hetero-junctions according to the conduction type of two kinds of materials.Due to two kinds of heterogeneous materials Material has different the physical-chemical parameters (such as electron affinity, band structure, dielectric constant and lattice constant etc.), makes hetero-junctions With a series of unexistent characteristic of homojunctions, it will obtain that there is the irrealizable function of some homojunctions on a device design. For example, very high injection ratio can be obtained by doing emitter stage with broadband side in heterojunction transistor, therefore can be obtained higher Multiplication factor.
The unique physicochemical properties of graphene, are expected in semiconductor, photovoltaic, lithium battery, biology, medical treatment, display etc. Tradition and new industry bring revolutionary advancement.The preparation method of wafer level graphene has CVD epitaxial growth methods and SiC high at present Warm solution.CVD epitaxial growth method shortcomings are that energy resource consumption is big, and the graphene sheet layer of acquisition and substrate interaction are strong, mostly When metal substrate on graphene need carry out being transferred on dielectric (such as SiO2Deng substrate), recycle its electrology characteristic Carry out device preparation.Therefore whole process complexity is higher, and material property loss is serious, and material is easily contaminated, also thus brings A series of problems, such as process repeatability.SiC high temperature pyrolytic cracking (HTP)s are under UHV condition, pass through electron bombardment, acid cleaning etc. Means remove oxide on monocrystalline 4H/6H-SiC substrates, then by substrate under vacuum or protective gas environment (1250-1450 DEG C) Heating, makes surface of SiC Si atoms distil, and the C atoms left reconstruct to form graphene.
With the extensive use of graphene, how to improve its manufacture craft and reduce the increasingly heavier of its cost of manufacture change Will.
The content of the invention
Therefore, to solve technological deficiency and deficiency existing for prior art, the present invention proposes a kind of graphene double heterojunction And preparation method thereof.
Specifically, An embodiment provides a kind of preparation method of graphene double heterojunction, including:
(a) backing material is chosen;
(b) 3C-SiC epitaxial layers are grown in the substrate material surface;
(c) processing is carried out to the 3C-SiC epitaxial layers using pyrolysismethod and forms graphene layer.
Wherein, the backing material is 4H-SiC or 6H-SiC.
In one embodiment of the invention, step (b) includes:
(b1) backing material is cleaned using standard cleaning technique;
(b2) backing material is put into epitaxial furnace, introduces Si sources, be heated to 1350 DEG C~1400 DEG C;
(b3) keeping temperature is constant and closes Si sources, removes the Si sources in epitaxial furnace, introduces silane and propane as growth Source gas, epitaxial growth is to form the 3C-SiC epitaxial layers.
In one embodiment of the invention, the 3C-SiC epitaxy layer thickness is 0.1-1 μm.
In one embodiment of the invention, the C members in the Si elements and the propane described in step (b3) in silane Plain ratio is 1:1.
In one embodiment of the invention, the flow of the silane is 21sccm, and the flow of the propane is 7sccm; The epitaxial growth time is 30min;The 3C-SiC epitaxy layer thickness is 0.5 μm.
In one embodiment of the invention, processing is carried out to the 3C-SiC epitaxial layers using pyrolysismethod and forms graphene Layer, including:At a temperature of 1300~1500 DEG C, in argon atmosphere, using chlorine as auxiliary gas, the 3C-SiC layers are entered Row pyrolysis processing in the 3C-SiC epitaxial layers to form the graphene layer.
Another embodiment of the present invention provides a kind of graphene double heterojunction, including:SiC substrate, 3C-SiC layers, graphite Alkene layer;Wherein, the graphene double heterojunction is prepared as the method described in any of the above-described embodiment forms
Compared with prior art, the invention has the advantages that:
1) graphene provided by the invention/3C-SiC/4H-SiC double-heterostructures, wherein, above three's band difference is different It is very big, but the Lattice Matching between three is very good, therefore it is the double different of achievable low defect that transition zone is not needed between three It is prepared by matter knot;
2) all growth courses of the present invention can be completed with an equipment, be advantageous to the drop of cost.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this For the those of ordinary skill of field, on the premise of not paying creative work, it can also be obtained according to these accompanying drawings other Accompanying drawing.
Fig. 1 is a kind of preparation method flow chart for graphene double heterojunction that one embodiment of the invention provides;
Fig. 2 a- Fig. 2 c are a kind of preparation technology schematic diagram for graphene double heterojunction that another embodiment of the present invention provides;
Fig. 3 a- Fig. 3 d are a kind of graphene double heterojunction based on pre-etching substrate that yet another embodiment of the invention provides Preparation technology schematic diagram;
Fig. 4 is a kind of structural representation for graphene double heterojunction that further embodiment of this invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of preparation method flow chart of graphene double heterojunction provided in an embodiment of the present invention, Including:
(a) backing material is chosen;
(b) 3C-SiC epitaxial layers are grown in the substrate material surface;
(c) processing is carried out to the 3C-SiC epitaxial layers using pyrolysismethod and forms graphene layer.
Wherein, the backing material is 4H-SiC or 6H-SiC.
Preferably, step (b) can include:
(b1) backing material is cleaned using standard cleaning technique;
(b2) backing material is put into epitaxial furnace, introduces Si sources, be heated to 1350 DEG C~1400 DEG C;
(b3) keeping temperature is constant and closes Si sources, removes the Si sources in epitaxial furnace, introduces silane and propane as growth Source gas, epitaxial growth is to form the 3C-SiC epitaxial layers.
Wherein, the 3C-SiC epitaxy layer thickness is 0.1-1 μm.
Wherein, the C element ratio in the Si elements and the propane described in step (b3) in silane is 1:1.
Preferably, the flow of the silane is 21sccm, and the flow of the propane is 7sccm;The epitaxial growth time is 30min;The 3C-SiC epitaxy layer thickness is 0.5 μm.
Further, processing is carried out to the 3C-SiC epitaxial layers using pyrolysismethod and forms graphene layer, including:1300 At a temperature of~1500 DEG C, in argon atmosphere, using chlorine as auxiliary gas, to the 3C-SiC layers carry out pyrolysis processing with The graphene layer is formed in the 3C-SiC epitaxial layers.
Graphene provided by the invention/3C-SiC/4H-SiC double-heterostructures, wherein, above three's band difference is different very Greatly, the Lattice Matching but between three is very good, therefore it is the double heterogeneous of achievable low defect that transition zone is not needed between three It is prepared by knot.
Embodiment two
Specifically, the present embodiment is so that the Si in 4H-SiC substrates looks unfamiliar long graphene as an example;Graphene/3C- is discussed in detail The preparation method of SiC/4H-SiC double heterojunctions;
Further, the preparation method is equally applicable to the C of 4H-SiC substrates and looked unfamiliar long graphene or 6H-SiC substrate The look unfamiliar C of long graphene or 6H-SiC substrate of Si look unfamiliar long graphene.
Refer to Fig. 2 a- Fig. 2 c, Fig. 2 a- Fig. 2 c is a kind of preparation of graphene double heterojunction provided in an embodiment of the present invention Process schematic representation, the preparation method comprise the following steps:
S201,4H-SiC substrates 201 are chosen, as shown in Figure 2 a.
S202, using RCA standard cleaning techniques, cleaning treatment is carried out to the material of substrate 201;
S203, Si sources are introduced in epitaxial furnace, under the Si element atmosphere in epitaxial furnace, by including the substrate 201 Whole material is heated to 1350~1400 DEG C;Keeping temperature is constant and closes Si sources 3min, then removes the Si members in epitaxial furnace Element.
S204, as shown in Figure 2 b, introduces 21sccm silane and 7sccm propane, epitaxial growth successively in epitaxial furnace 30min;To obtain 3C-SiC epitaxial layer 202 of the thickness as 500nm.Wherein, can during growing 3C-SiC epitaxial layers 202 Outer layer doping concentration and type are adjusted in growth course as needed.
S206, as shown in Figure 2 c, close hydrogen, Sources gas and impurity gas;In argon atmosphere, temperature is At 1300~1500 DEG C;Using chlorine as auxiliary gas, pyrolysis processing is carried out to the 3C-SiC epitaxial layers, makes the 3C-SiC The Si atoms distillation of layer surface, the C atoms left are reconstructed to form the graphene layer 203.Wherein, when graphene target is adulterated When type and concentration and inconsistent 3C-SiC layers, graphene layer can be entered by the mode such as annealing under ion implanting and particular atmosphere Row doping adjustment.
Forbidden band is widely different between graphene, 3C-SiC and 4H-SiC in the present invention;Wherein, graphene is pyramid type energy Band, an energy gap can be opened on sic substrates;3C-SiC is non-polarized semiconductor material with wide forbidden band, and its energy gap is 2.3eV;4H-SiC is polarization wide bandgap semiconductor, and its energy gap is 3.2eV.According to the difference of 4H-SiC polarization characteristics, 3C-SiC epitaxial layers are grown on Si faces or C faces can produce SQW in valence band or conduction band respectively, so as to formed two-dimensional electron gas or Hole gas.And then it is that three's band difference is different very big to form a great advantage, but the Lattice Matching between three is very good, because It is prepared by the double heterojunction that low defect can be achieved that transition zone is not needed between this three.For example, between 3C-SiC and 4H-SiC Lattice mismatch can be ignored.It is seldom the defects of between lattice because incorgruous matching degree is very good between graphene and 3C-SiC.
The doping concentration on doping way in situ regulation SiC top layers can be used.Simultaneously because the doping concentration and SiC of graphene The doping concentration of layer is relevant, therefore the doping concentration of final graphene layer can also be adjusted by 3C-SiC layers doping concentration.With VP508 Exemplified by epitaxial furnace, when 3C-SiC epitaxial layers are identical with graphene layer doping type, all flows can be in same growth chamber Complete;When extension 3C-SiC layers and graphene layer doping type difference, it is necessary to which transforming growth chamber completes extension.It is all to grow Cheng Jun can be completed with an equipment.Be advantageous to the reduction of cost.
Embodiment three
Further, the present embodiment carries out pre-etching to backing material on the basis of above-described embodiment and forms pre-etching lining Bottom.
Specifically, it is double heterogeneous for a kind of graphene provided in an embodiment of the present invention that Fig. 3 a- Fig. 3 d, Fig. 3 a- Fig. 3 d be refer to The preparation technology schematic diagram of knot, the preparation method comprise the following steps:
S301,4H-SiC substrates 301 are chosen, as shown in Figure 3 a.
S302, the etching 4H-SiC substrates 301 form pre-etching substrate 302, as shown in Figure 3 b.
S3021, in the consecutive deposition metal of 4H-SiC substrates 301 and photoresist;
S3022, using standard development technique, using mask plate, etch the photoresist, form the pre-etching figure;
S3023, using ICP or RIE etching technics, form the pre-etching lining in the 4H-SiC substrate etchings table top Bottom 302, wherein, the mesa dimensions are 500 μm of 500 μ m to 5mm × 5mm;Depth is 3 μm.
S303, using RCA standard cleaning techniques, the whole material including the pre-etching substrate 302 is carried out at cleaning Reason;Wherein, introduce RCA standard cleanings technique and can remove the pollution that dry etching is brought.
S304, introduce Si sources in epitaxial furnace, under the Si element atmosphere in epitaxial furnace, the pre-etching substrate will be included 302 whole material is heated to 1350~1400 DEG C;Keeping temperature is constant and closes Si sources 3min, then removes in epitaxial furnace Si elements.
S305, as shown in Figure 3 c, introduces 21sccm silane and 7sccm propane, epitaxial growth successively in epitaxial furnace 30min;To obtain 3C-SiC epitaxial layer 303 of the thickness as 500nm.Wherein, can during growing 3C-SiC epitaxial layers 303 Outer layer doping concentration and type are adjusted in growth course as needed.
S306, as shown in Figure 3 d, close hydrogen, Sources gas and impurity gas;In argon atmosphere, temperature is At 1300~1500 DEG C;Using chlorine as auxiliary gas, pyrolysis processing is carried out to the 3C-SiC epitaxial layers, makes the 3C-SiC The Si atoms distillation of layer surface, the C atoms left are reconstructed to form the graphene layer 304.Wherein, when graphene target is adulterated When type and concentration and inconsistent 3C-SiC layers, graphene layer can be entered by the mode such as annealing under ion implanting and particular atmosphere Row doping adjustment.
The present embodiment realizes the preparation of large area, uniformly continuous, highly crystalline quality graphene by pre-etching SiC substrate; Influencing each other between defect can be effectively isolated, so as to can be different to reduce with the more preferable grapheme material of production quality on table top The defects of matter junction structure.
Example IV
Fig. 4 is refer to, Fig. 4 is a kind of structural representation of graphene double heterojunction provided in an embodiment of the present invention.The stone Black alkene double heterojunction is made of the above-mentioned preparation method as shown in Fig. 2 a- Fig. 2 c.Specifically, the graphene double heterojunction bag Include:4H-SiC substrates 401,3C-SiC layers 402 and graphene layer 403.
To sum up, specific case used herein is set forth to the principle and embodiment of the present invention, and the above is implemented The explanation of example is only intended to help the method and its core concept for understanding the present invention;Meanwhile for the general technology people of this area Member, according to the thought of the present invention, there will be changes in specific embodiments and applications, to sum up, in this specification Appearance be should not be construed as limiting the invention, and protection scope of the present invention should be defined by appended claim.

Claims (8)

  1. A kind of 1. preparation method of graphene double heterojunction, it is characterised in that including:
    (a) backing material is chosen;
    (b) 3C-SiC epitaxial layers are grown in the substrate material surface;
    (c) the 3C-SiC epitaxial layers are pyrolyzed and form graphene layer to complete the preparation of the graphene double heterojunction.
  2. 2. preparation method according to claim 1, it is characterised in that the backing material is 4H-SiC or 6H-SiC.
  3. 3. preparation method according to claim 1, it is characterised in that step (b) includes:
    (b1) backing material is cleaned using standard cleaning technique;
    (b2) backing material is put into epitaxial furnace, introduces Si sources, be heated to 1350 DEG C~1400 DEG C;
    (b3) keeping temperature is constant and closes Si sources, removes the Si sources in epitaxial furnace, introduces silane and propane as growth source gas Body, epitaxial growth is to form the 3C-SiC epitaxial layers.
  4. 4. the preparation method according to claim 1 or 3, it is characterised in that the 3C-SiC epitaxy layer thickness is 0.1-1 μ m。
  5. 5. preparation method according to claim 3, it is characterised in that the Si elements in silane and institute described in step (b3) It is 1 to state the C element ratio in propane:1.
  6. 6. preparation method according to claim 3, it is characterised in that the flow of the silane is 21sccm, the propane Flow be 7sccm;The epitaxial growth time is 30min;The 3C-SiC epitaxy layer thickness is 0.5 μm.
  7. 7. preparation method according to claim 1, it is characterised in that carried out using pyrolysismethod to the 3C-SiC epitaxial layers Processing forms graphene layer, including:
    At a temperature of 1300~1500 DEG C, in argon atmosphere, using chlorine as auxiliary gas, heat is carried out to the 3C-SiC layers Solution is handled to form the graphene layer in the 3C-SiC epitaxial layers.
  8. A kind of 8. graphene double heterojunction, it is characterised in that including:SiC substrate, 3C-SiC layers, graphene layer;Wherein, it is described Graphene double heterojunction is prepared as the method described in any one of claim 1~7 and formed.
CN201710876844.6A 2017-09-25 2017-09-25 Graphene double heterojunction and preparation method thereof Pending CN107845567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710876844.6A CN107845567A (en) 2017-09-25 2017-09-25 Graphene double heterojunction and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710876844.6A CN107845567A (en) 2017-09-25 2017-09-25 Graphene double heterojunction and preparation method thereof

Publications (1)

Publication Number Publication Date
CN107845567A true CN107845567A (en) 2018-03-27

Family

ID=61661930

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710876844.6A Pending CN107845567A (en) 2017-09-25 2017-09-25 Graphene double heterojunction and preparation method thereof

Country Status (1)

Country Link
CN (1) CN107845567A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116514112A (en) * 2023-06-09 2023-08-01 中电科先进材料技术创新有限公司 Preparation method of large-area graphene on silicon surface

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102560414A (en) * 2012-01-03 2012-07-11 西安电子科技大学 Method for preparing graphene on 3C-SiC substrate
CN102933491A (en) * 2010-06-07 2013-02-13 电子材料技术研究所 Method of graphene manufacturing
CN105826173A (en) * 2015-01-07 2016-08-03 北京华进创威电子有限公司 In-situ etching method for SiC hetero epitaxial growth

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102933491A (en) * 2010-06-07 2013-02-13 电子材料技术研究所 Method of graphene manufacturing
CN102560414A (en) * 2012-01-03 2012-07-11 西安电子科技大学 Method for preparing graphene on 3C-SiC substrate
CN105826173A (en) * 2015-01-07 2016-08-03 北京华进创威电子有限公司 In-situ etching method for SiC hetero epitaxial growth

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
张晨旭: "在3C-SiC上外延生长石墨烯的工艺研究", 《基于3C-SIC外延生长石墨烯的方法与侧栅石墨烯晶体管模拟的研究》 *
辛斌: "Si面3C/4H-SiC异质外延", 《基于CVD工艺的3C/4H-SIC异质外延:缺陷表征及演化》 *
郝昕: "热解SiC法制备石墨烯的原理", 《SIC热裂解外延石墨烯的可控制备及性能研究》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116514112A (en) * 2023-06-09 2023-08-01 中电科先进材料技术创新有限公司 Preparation method of large-area graphene on silicon surface
CN116514112B (en) * 2023-06-09 2023-12-19 中电科先进材料技术创新有限公司 Preparation method of large-area graphene on silicon surface

Similar Documents

Publication Publication Date Title
US11955373B2 (en) Gallium oxide semiconductor structure and preparation method therefor
US8324631B2 (en) Silicon carbide semiconductor device and method for manufacturing the same
CN104718601A (en) SiC substrate with SiC epitaxial film
CN105161578B (en) The growing method of GaN film and compound GaN film on Si substrates
CN107634089B (en) A kind of graphene-selenizing niobium superconduction heterojunction device and preparation method thereof
CN105140102B (en) A kind of method of the beta-silicon carbide thin film of epitaxial growth on a silicon substrate of optimization
JP6264768B2 (en) Semiconductor structure, semiconductor device, and method of manufacturing the semiconductor structure
CN102449734A (en) Silicon carbide substrate production method and silicon carbide substrate
JP6758491B2 (en) SiC epitaxial wafer and its manufacturing method
CN105441902A (en) Epitaxial silicon carbide-graphene composite film preparation method
Xie et al. Preferential growth of Si films on 6H-SiC (0 0 0 1) C-face
CN104561926B (en) A kind of method for preparing beta -sic film on a silicon substrate
Huang et al. Conducting channel at the LaAlO 3/SrTiO 3 interface
Lianbi et al. Hetero-epitaxy and structure characterization of Si films on 6H-SiC substrates
CN107845567A (en) Graphene double heterojunction and preparation method thereof
CN107611221A (en) The method for improving the class super crystal lattice material quality of antimonide base II
Feng et al. SiC based Si/SiC heterojunction and its rectifying characteristics
CN107845566A (en) Double heterojunction based on pre-etching substrate and preparation method thereof
CN102674317B (en) C injection-based Ni film assisted SiC substrate graphene nanoribbon preparation method
Sun et al. Graphene on silicon: Effects of the silicon surface orientation on the work function and carrier density of graphene
Yang et al. The epitaxial growth of (1 1 1) oriented monocrystalline Si film based on a 4: 5 Si-to-SiC atomic lattice matching interface
CN107895685A (en) The preparation method of highly crystalline quality graphene
CN107546299B (en) Modified Ge material of direct band gap based on GeSiC selective epitaxy and preparation method thereof
Zhu et al. Epitaxial growth of SnO2 films on 6H-SiC (0 0 0 1) by MOCVD
CN102674319B (en) Preparation method for Ni film assisted annealing graphene nano belt based on C injection

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180327