CN107818977A - Strain GeSn PMOS devices and preparation method thereof - Google Patents

Strain GeSn PMOS devices and preparation method thereof Download PDF

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Publication number
CN107818977A
CN107818977A CN201711112534.3A CN201711112534A CN107818977A CN 107818977 A CN107818977 A CN 107818977A CN 201711112534 A CN201711112534 A CN 201711112534A CN 107818977 A CN107818977 A CN 107818977A
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materials
gesn
layers
substrate
layer
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张洁
宋建军
任远
胡辉勇
宣荣喜
舒斌
张鹤鸣
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Abstract

The present invention relates to one kind strain GeSn PMOS devices and preparation method thereof.The PMOS device includes：Single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and strain GeSn layers.The PMOS device of the present invention has very high hole and electron mobility, can be obviously improved the speed and frequency characteristic of transistor.

Description

Strain GeSn PMOS devices and preparation method thereof
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of strain GeSn PMOS devices and preparation method thereof.
Background technology
Computer (computer) is commonly called as computer, is a kind of electronic computer device for supercomputing, can enter line number Value calculates, and logical calculated can be carried out again, also with store-memory function.It is that can be run according to program, automatic, high speed processing The modernization intelligent electronic device of mass data.It is made up of hardware system and software systems, is fitted without the meter of any software Calculation machine is referred to as bare machine.Supercomputer, industrial control computer, network computer, personal computer, embedding assembly can be divided into The class of machine five, more advanced computer have biocomputer, photonic computer, quantum computer etc..
The many components of computer form by integrated circuit, and integrated circuit is such as MOS device half by the bottom Conductor device forms.And as the continuous diminution of MOS device characteristic size, the complexity of manufacturing process are also being continuously increased, Correspondingly realize that the equipment investment scale of production in enormous quantities is also increasing.By improving device architecture, technique or using green wood Material, the mobility of raceway groove carriers is improved, by existing characteristic size, MOS devices are processed using existing production equipment condition Part, not only reach the purpose for improving device performance, can also extend the service life of existing production line.Therefore, high mobility is developed The MOS device of raceway groove, the performance to improving device and integrated circuit, promotes the long term growth of microelectronics and integrated circuit technique With highly important application value and meaning.
The way provided with the development of integrated circuit technique, the integrated circuit based on silicon CMOS along " Moore's Law " Footpath, develop to smaller size of direction, the also more and more higher of the requirement for device performance and operating rate.But current spy Size is levied close to the limit of Si materials, by reduce device feature size improve chip operation speed, increase integrated level with And reduce cost and become extremely difficult.The increase of nanoprocessing process costs, short-channel effect reduce grid-control ability, and Si The factors such as the limitation of material mobility itself reject the possibility for continuing to zoom out device size.Conventional CMOS technology has been difficult to tie up Hold Moore's Law to continue to develop, inexorable trend had become using new device technology.To solve chip high-performance and ultralow The contradiction of power consumption, introduce the key solution that new high mobility material is current large scale integrated circuit research.
The content of the invention
Therefore, to solve technological deficiency and deficiency existing for prior art, the present invention proposes a kind of strain GeSn PMOS devices Part and preparation method thereof.
A kind of preparation method for strain GeSn PMOS devices that one embodiment of the present of invention proposes, including：
S101, choose single crystal Si substrate；
S102, at a temperature of 275 DEG C~325 DEG C, grow 40~50nm's on the single crystal Si substrate using CVD techniques First Ge inculating crystal layers；
S103, at a temperature of 500 DEG C~600 DEG C, using CVD techniques the first Ge seed crystal surfaces grow 150 ~250nm the 2nd Ge body layers；
S103, using CVD techniques 150nm SiO are deposited in the 2nd Ge main body layer surfaces2Layer；
S104, the single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and the SiO will be included2 The whole backing material of layer is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, laser wave A length of 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
Whole backing material described in S105, natural cooling；
S106, utilize the dry etch process etching SiO2Layer, form Ge/Si void backing materials；
S107, at a temperature of 350 DEG C, be using depressurizing CVD technique growth thickness in the Ge/Si void substrate material surface 20nm strain GeSn materials；
S108, in the case where temperature is 400~500 DEG C, in strain GeSn material surfaces injection P ion, injection length is 200s, form N-type strain GeSn materials；
S109, at a temperature of 370 DEG C, using Si in situ2H6Surface passivation technique strains GeSn materials to the N-type and carried out Surface passivation；
S110, at a temperature of 250 DEG C, utilize atomic layer deposition processes deposition thickness be 4nm HfO2Material；
S111, in the HfO2Material surface utilizes reactive sputtering system depositing technics deposit TaN materials；
S112, utilize the chlorine based plasma etching technics etching TaN materials and the HfO2Material forms gate regions.
S113, using self-registered technology, inject BF different from the region of the gate regions on bulk substrate surface2 +Form source and drain Area；
S114, the Ni materials using electron beam evaporation process in whole substrate surface deposition thickness for 10nm；
S115, use concentration to remove part Ni materials using selective wet processing for 96% concentrated sulfuric acid, ultimately form The strain GeSn PMOS devices.
A kind of strain GeSn PMOS devices that another embodiment of the invention proposes, including：Single crystal Si substrate, the first Ge Inculating crystal layer, the 2nd Ge body layers and strain GeSn layers；Wherein, the strain GeSn PMOS devices are provided by above-described embodiment Preparation method is formed.
Above-described embodiment, the present invention pass through the continuous laser thin Ge/Si void substrate of crystallization again using laser crystallization technique, can The dislocation density of Ge/Si void substrates is effectively reduced, and then the strain Ge of subsequent growth can be improved1-xSnxAlloy firm quality；Even Crystallization process selectivity is high again for continuous laser, acts only on Ge epitaxial layers, control is accurate, avoids the problem of Si-Ge mutually expands；Continuously The crystallization process time is short again, heat budget is low for laser, can be lifted and strain Ge on Si substrates1-xSnxThe technique effect of the whole processing procedure of film Rate.In addition, by the raceway groove of GeSn, Ge, InGaAs MOS device, there is very high hole and electron mobility, can significantly carry Rise the speed and frequency characteristic of transistor.And then the collection that the nmos device or cmos device provided by above-described embodiment is formed The chip and computer formed into circuit and by integrated circuit, more existing chip and equipment have more excellent feature.
By the detailed description below with reference to accompanying drawing, other side of the invention and feature become obvious.But it should know Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, because it should refer to Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale accompanying drawing, they only try hard to concept Ground illustrates structure and flow described herein.
Brief description of the drawings
Below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.
Fig. 1 a- Fig. 1 l are a kind of schematic diagram of strain GeSn nmos device preparation technologies provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic diagram of laser crystallization technique provided in an embodiment of the present invention；
Fig. 3 is a kind of structural representation of Laser crystallization equipment provided in an embodiment of the present invention；
The technique that Fig. 4 a- Fig. 4 x are a kind of strain GeSn cmos device preparation technologies provided in an embodiment of the present invention is illustrated Figure；
The technique that Fig. 5 a- Fig. 5 x are a kind of strain GeSn cmos device preparation technologies provided in an embodiment of the present invention is illustrated Figure；
The technique that Fig. 6 a- Fig. 6 l are a kind of strain GeSn PMOS device preparation technologies provided in an embodiment of the present invention is illustrated Figure；
Fig. 7 is a kind of structural representation of computer provided in an embodiment of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention Embodiment be described in detail.
Embodiment one
Fig. 1 is referred to, Fig. 1 a- Fig. 1 l are a kind of strain GeSn nmos device preparation technologies provided in an embodiment of the present invention Schematic diagram.This method comprises the following steps：
S101, such as Fig. 1 a, choose single crystal Si substrate 201；
S102, such as Fig. 1 b, at a temperature of 275 DEG C~325 DEG C, grow 40 on the single crystal Si substrate using CVD techniques ~50nm the first Ge inculating crystal layers 202；
S103, such as Fig. 1 b, at a temperature of 500 DEG C~600 DEG C, using CVD techniques in the table of the first Ge inculating crystal layers 202 150~250nm of length of looking unfamiliar the 2nd Ge body layers 202 (it should be noted that check the first Ge inculating crystal layers for convenience in figure One layer is combined into the 2nd Ge body layers, 202) overall naming number is；
S103, such as Fig. 1 c, 150nm SiO are deposited on the surface of the 2nd Ge body layers 202 using CVD techniques2Layer 203；
S104, the single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and the SiO will be included2 The whole backing material of layer is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, laser wave A length of 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
Whole backing material described in S105, natural cooling；
S106, such as Fig. 1 d, the SiO is etched using dry etch process2Layer 203, form Ge/Si void backing materials；
S107, such as Fig. 1 e, at a temperature of 350 DEG C, the Ge/Si void substrate material surface using depressurize CVD techniques life Long thickness is 20nm strain GeSn materials 204；
S108, in the case where temperature is 400~500 DEG C, in the surface of strain GeSn materials 204 injection boron ion, during injection Between be 200s, formed p-type strain GeSn materials；
S109, such as Fig. 1 f, at a temperature of 370 DEG C, using Si in situ2H6Surface passivation technique strains GeSn materials to the p-type Material carries out surface passivation, forms passivation layer 205；
S110, such as Fig. 1 g, at a temperature of 250 DEG C, utilize the HfO that atomic layer deposition processes deposition thickness is 4nm2Material 206；
S111, such as Fig. 1 h, in the HfO2The surface of material 206 utilizes reactive sputtering system depositing technics deposit TaN materials Material 207；
S112, such as Fig. 1 i, the TaN materials 207 and the HfO are etched using chlorine based plasma etching technics2Material 206 form gate regions.
S113, such as Fig. 1 j, using self-registered technology, bulk substrate surface different from the region of the gate regions inject phosphorus from Son forms source-drain area；
S114, such as Fig. 1 k, using electron beam evaporation process in the Ni materials that whole substrate surface deposition thickness is 10nm 208；
S115, such as Fig. 1 l, concentration is used to remove part Ni materials using selective wet processing for 96% concentrated sulfuric acid, most End form is into the strain GeSn nmos devices.
In the present embodiment and following examples, the GeSn materials can be：Ge0.99Sn0.01。
The present invention Ge/Si void backing materials principle and beneficial effect be specially：
Relaxation Ge cushion relative maturities are prepared on Si substrates, and most common method is two-step growth method.This method First low-temperature epitaxy a thin layer Ge, suppresses the island growth caused by big lattice mismatch.Afterwards again outside high growth temperature main body Ge Prolong layer.Compared with traditional graded buffer layer growth method, graded layer thickness is this approach reduce, and cause Ge epi-layer surfaces Roughness significantly reduces.
But two-step growth method still can not solve the appearance of a large amount of helical dislocations in Ge epitaxial layers, so also often needing to tie Cycle annealing technique is closed to reduce Ge epitaxial layer threading dislocation densities.However, cycle annealing technique is only applicable to several micron thickness Ge epitaxial layers, for thin Ge epitaxial layers, it may appear that Si-Ge exclusive problems.In addition, the introducing of cycle annealing technique exists While reducing dislocation density, the increase of Ge/Si buffer-layer surface roughness is also resulted in.Meanwhile also there is technique in this method The shortcomings of cycle is grown, and heat budget is high.
The essence for being difficult to acquisition low-dislocation-density Ge/Si void substrates is due to that the misfit dislocation between Si and Ge is big, interface Dislocation defects can extend longitudinally to Ge surface during epitaxial layer progressive additive, and then cause Ge/Si void substrate crystals Quality reduces.Therefore, in order to eliminate dislocation defects caused by longitudinal extension, the fast speed heats of Ge/Si can be used to melt the side of recrystallization Method, the dislocation mismatch between Ge and Si is laterally discharged, and then the Ge/Si void substrate of high quality is strain Ge1-xSnxEpitaxial film Growth provide advantage.
Therefore, referring to Fig. 2, Fig. 2 is a kind of schematic diagram of laser crystallization technique provided in an embodiment of the present invention.First use magnetic Control sputtering technology or CVD techniques form thin Ge epitaxial layers through two-step method, then laterally discharge Ge and Si with continuous laser crystallization Between dislocation mismatch, so as to reduce the dislocation caused by lattice mismatch in epitaxial layer, it is empty to prepare Ge/Si best in quality Substrate.
Fig. 3 is referred to, Fig. 3 is a kind of structural representation of Laser crystallization equipment provided in an embodiment of the present invention；The present invention Laser crystallization process can use 808nm semiconductor lasers, LIMO 806nm, 140MWm-2 lasers can also be used, Device is as shown in Figure 3.Laser is pointed into sample stage by total reflection prism, and by convex lens focus to sample, so as to prevent Liquid after film melts in thermal histories is affected by gravity and flowed on influence caused by crystallization.During laser crystallization, step Stepper motor drives sample stage movement, makes sample block-by-block crystallization.
Using laser, crystallization LRC technologies auxiliary prepares high quality void Ge substrates again, it is desirable to empty Ge layers temperature under laser action At least up to fusing point, and close proximity to scorification point, reach the nearly complete molten condition of preferable crystallization, ensure the follow-up complete of Ge crystal grain U.S.'s crystallization.Meanwhile the Si substrate layers below epitaxial layer can not reach fusing point, it ensure that laser crystallization does not have an impact to substrate. Accordingly, it is determined that rational laser crystallization related process parameters (such as laser power density, translational speed), control epitaxial layer temperature Distribution, will be the key of the technique success or failure.
The present embodiment, by above-mentioned processing technology, at least possesses following advantage：
1) present invention prepares Ge/Si void substrates by continuous laser auxiliary crystallization, can effectively reduce the position of Ge/Si void substrates Dislocation density, and then the strain Ge of subsequent growth can be improved1-xSnxAlloy firm quality；
2) present invention uses laser crystallization process has the advantages of crystallization time is short, heat budget is low again, can lift Si and serve as a contrast Ge is strained on bottom1-xSnxThe process efficiency of the whole processing procedure of film.
3) using strain GeSn, InGaAs, Ge material be used as NMOS, the raceway groove of cmos device, have very high hole with Electron mobility, the speed and frequency characteristic of transistor can be obviously improved；
4) possesses more preferable switching characteristic using NMOS, CMOS of present invention integrated circuits formed and chip；By these The computer of integrated circuit and chip composition has more excellent working characteristics.
Embodiment two
Fig. 4 a- Fig. 4 x, Fig. 4 a- Fig. 4 x are referred to as a kind of strain GeSn cmos device systems provided in an embodiment of the present invention The process schematic representation of standby technique, this method include：
S101, such as Fig. 4 a, choose single crystal Si substrate 201；
S102, such as Fig. 4 b, at a temperature of 275 DEG C~325 DEG C, grow 40 on the single crystal Si substrate using CVD techniques ~50nm the first Ge inculating crystal layers 202；
S103, such as Fig. 4 b, at a temperature of 500 DEG C~600 DEG C, using CVD techniques in the first Ge seed crystal surfaces 150~250nm the 2nd Ge body layers 202 are grown (it should be noted that being checked the first Ge inculating crystal layers for convenience in figure One layer is combined into the 2nd Ge body layers, 202) overall naming number is；
S104, such as Fig. 4 c, 150nm SiO are deposited in the 2nd Ge main body layer surfaces using CVD techniques2Layer 203；
S105, the single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and the SiO will be included2 The whole backing material of layer is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, laser wave A length of 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
Whole backing material described in S106, natural cooling；
S107, such as Fig. 4 d, the SiO is etched using dry etch process2Layer 203, form Ge/Si void backing materials；
S108, such as Fig. 4 e, at a temperature of 350 DEG C, given birth in the Ge/Si void substrate material surface using CVD techniques are depressurized Long 20nm strain GeSn materials 204；
S109, in the case where temperature is 400~500 DEG C, in strain GeSn material surfaces injection boron ion, injection length is 200s, form N-type strain GeSn materials；
S110, such as Fig. 4 f, photoetching shallow trench isolation region, etching depth in whole substrate surface using dry etch process is 100~150nm shallow slot 205；
S111, such as Fig. 4 g, at a temperature of 750~850 DEG C, using CVD techniques whole substrate surface deposition thickness be 30 ~50nm SiO2Material 206 will fill up in the shallow slot；
S112, such as Fig. 4 h, using CVD techniques in the SiO2The surface deposition thickness of material 206 is 20~30nm Si3N4 Material 207；
S113, such as Fig. 4 i, the part Si is removed using CMP3N4Material 207 and the SiO2Material 206, remove Thickness is equal to the Si of deposit3N4The thickness of material；
S114, such as Fig. 4 j, the SiO on bulk substrate surface is etched away using anisotropic dry etch process2Material Material, form shallow-trench isolation；
S115, such as Fig. 4 k, NMOS is formed in whole substrate surface specific region injection boron ion using ion implantation technology Well region；Photoresist 208 is molded to stop ion implanting, reinjects high energy boron ion, local p type island region domain is formed, for manufacturing NMOS tube；
S116, such as Fig. 4 l, at a temperature of 250~300 DEG C, thickness is deposited in whole substrate surface using atomic layer deposition processes Spend the HfO for 2~10nm2Material 209；
S117, such as Fig. 4 m, at a temperature of 750~850 DEG C, using CVD techniques in the HfO2Material surface deposition thickness For 110nm TaN materials 210；
S118, such as Fig. 4 n, the TaN materials and the HfO are etched using etching technics2Material formed NMOS gate and PMOS grids；Photoresist 211 is molded, and etches away unnecessary TaN210 and HfO2209；Such as Fig. 4 o, photoresist 211 is removed；
S119, such as Fig. 4 p, in the NMOS gate and PMOS gate surfaces growth SiO2Protective layer 212；Nitrogenizing Tantalum surface grows thin oxide layer 212, isolates tantalum nitride for buffering, then in designated area gluing；
S120, such as Fig. 4 q, inject As ions on the NMOS well regions surface using ion implantation technology and form NMOS source and drain Area, and form NMOS source-drain electrodes 213 using rapid thermal anneal process annealing 30s under 250~300 DEG C of nitrogen environments；
S121, such as Fig. 4 r, BF is carried out on PMOS well regions surface using ion implantation technology2 +Injection forms PMOS source drain region, And form PMOS source drain electrode 214 using rapid thermal anneal process annealing 30s under 250~300 DEG C of nitrogen environments；That is, remove The photoresist in original region, in designated area gluing；Using ion implantation technology, BF is carried out to PMOS source-drain area2 +Injection, shape Into source-drain area, rapid thermal annealing (RTA) 30s under 250~300 DEG C of nitrogen environments, forms source-drain electrode 214 afterwards；Remove photoetching Glue；
S122, such as Fig. 4 s, the SiO of whole substrate surface is removed using HF solution2Protective layer 212；
S123, such as Fig. 4 t, using CVD techniques in the BPSG 215 that whole substrate surface deposition thickness is 20~30nm；
S124, such as Fig. 4 u, NMOS source and drain contact hole is formed using BPSG described in nitric acid and hf etching and PMOS source is leaked Contact hole；
S125, such as Fig. 4 v, it is that 10~20nm metal Ws 216 form NMOS source and drain using electron beam evaporation process deposition thickness Contact and PMOS source drain contact；
S126, such as Fig. 4 w, the metal W 216 of selective eating away designated area is carved using etching technics, and utilizes CMP Carry out planarization process；
S127, such as Fig. 4 x, the SiN materials 217 using CVD techniques in whole substrate surface deposition thickness for 20~30nm, To form the strain GeSn cmos devices.
Embodiment three
Fig. 5 a- Fig. 5 x, Fig. 5 a- Fig. 5 x are referred to as a kind of strain GeSn cmos device systems provided in an embodiment of the present invention The process schematic representation of standby technique, this method include：
S101, such as Fig. 5 a, choose single crystal Si substrate 101；
S102, such as Fig. 5 b, at a temperature of 275 DEG C~325 DEG C, using CVD techniques the growth 50nm the first Ge seeds Crystal layer 102；
S103, such as Fig. 5 c, at a temperature of 500 DEG C~600 DEG C, using CVD techniques in the first Ge seed crystal surfaces 150nm the 2nd Ge body layers 102 are grown (it should be noted that being checked the first Ge inculating crystal layers and second for convenience in figure Ge body layers are combined into one layer, 102) overall naming number is；
S104, such as Fig. 5 d, 100nm SiO are deposited on the surface of the 2nd Ge body layers 102 using CVD techniques2Layer 103；
S105, whole backing material is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, Wherein, optical maser wavelength 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed is 25mm/s；
S106, such as Fig. 5 e, the SiO is etched using dry etch process2Layer, the Ge layers 104 formed after crystallization；
S107, such as Fig. 5 f, Ge/Si substrates described in nitric acid and hf etching are used to form groove of the depth for 200nm；
S108, such as Fig. 5 g, SiO is deposited in the single crystal Si substrate using CVD techniques2Material 105 forms field oxide；
S109, such as Fig. 5 h, at a temperature of 650 DEG C, with H2For carrier gas, it is anti-to use trimethyl indium, trimethyl to sow with arsine Ying Yuan, diethyl zinc are P-type dopant, and MOCVD techniques extension on the 2nd Ge body layers is utilized in the NMOS grooves 20nm P type GeSn layers 106；
S110, such as Fig. 5 i, at a temperature of 500~600 DEG C, it is grown in the PMOS grooves using depressurizing CVD techniques The 2nd Ge body layer surface depositions thickness is 20nm N-type Ge layers 107；
S111, such as Fig. 5 j, in the p-type GeSn layer surfaces growth thickness it is 2nm using rapid thermal oxidation process GeSnO2Boundary layer 108；
S112, such as Fig. 5 k, the N-type Ge layers are placed on to 75 DEG C of H2O2In solution, it is 10 minutes to immerse the time, in the N Type Ge layer surfaces form a GeO2Passivation layer 109；
S113, such as Fig. 5 l, at a temperature of 250 DEG C, atomic layer is used in the p-type GeSn layers and the N-type Ge layer surfaces Depositing technics deposition thickness is 3nm HfO2Material 110；
S114, such as Fig. 5 m, utilize the Ni materials 111 that electron beam evaporation process deposition thickness is 10nm；
S115, such as Fig. 5 n, concentration is used to remove part Ni material shapes using selective wet processing for 96% concentrated sulfuric acid Into NMOS metal gates and PMOS metal gates；
S116, such as Fig. 5 o, it is 10 to the NMOS groove surfaces implantation concentration using self-registered technology17/cm3N-type it is miscellaneous Matter, NMOS source-drain areas 112 are formed in the p-type GeSn layers；
S117, such as Fig. 5 p, it is 10 to the PMOS groove surfaces implantation concentration using self-registered technology17/cm3P-type it is miscellaneous Matter, PMOS source drain region 113 is formed in the N-type Ge layers；
S118, such as Fig. 5 q, the NMOS source-drain areas and institute are activated using rapid thermal anneal process under 250 DEG C of nitrogen environments State the impurity in PMOS source-drain areas；
S119, such as Fig. 5 r, using on NMOS source-drain areas described in nitric acid and hf etching and PMOS source drain region surface The HfO2Material 114；
S120, such as Fig. 5 s, the formation isolated material of PSG materials 114 that growth thickness is 200nm in bulk substrate, and Flow back 1min under 200 DEG C of nitrogen environments, reaches planarization, such as Fig. 5 t；
S121, such as Fig. 5 u, source and drain contact hole is formed using PSG materials 114 described in nitric acid and hf etching；
S122, such as Fig. 5 v, it is 10nm Ni 115 using electron beam evaporation process deposition thickness, forms the contact of NMOS source and drain Contacted with PMOS source and drain；
S123, such as Fig. 5 w, concentration is used to remove subregion using selective wet processing for 96% concentrated sulfuric acid Ni 115；
S124, such as Fig. 5 x, using CVD techniques deposition thickness be 20nm SiN materials 116 with formed NMOS isolation and PMOS Isolation, ultimately forms the strain GeSn cmos devices.
Example IV
Fig. 6 a- Fig. 6 l, Fig. 6 a- Fig. 6 l are referred to as a kind of strain GeSn PMOS device systems provided in an embodiment of the present invention The process schematic representation of standby technique；This method can include：
S101, such as Fig. 6 a, choose single crystal Si substrate 201；
S102, such as Fig. 6 b, at a temperature of 275 DEG C~325 DEG C, grow 40 on the single crystal Si substrate using CVD techniques ~50nm the first Ge inculating crystal layers 202；
S103, such as Fig. 6 b, at a temperature of 500 DEG C~600 DEG C, using CVD techniques in the table of the first Ge inculating crystal layers 202 150~250nm of length of looking unfamiliar the 2nd Ge body layers 202 (it should be noted that check the first Ge inculating crystal layers for convenience in figure One layer is combined into the 2nd Ge body layers, 202) overall naming number is；
S103, such as Fig. 6 c, 150nm SiO are deposited on the surface of the 2nd Ge body layers 202 using CVD techniques2Layer 203；
S104, the single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and the SiO will be included2 The whole backing material of layer is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, laser wave A length of 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
Whole backing material described in S105, natural cooling；
S106, such as Fig. 6 d, the SiO is etched using dry etch process2Layer 203, form Ge/Si void backing materials；
S107, such as Fig. 6 e, at a temperature of 350 DEG C, the Ge/Si void substrate material surface using depressurize CVD techniques life Long thickness is 20nm strain GeSn materials 204；
S108, temperature be 400~500 DEG C at, the surface of strain GeSn materials 204 injection P ion, injection length For 200s, N-type strain GeSn materials are formed；
S109, such as Fig. 6 f, at a temperature of 370 DEG C, using Si in situ2H6Surface passivation technique strains GeSn materials to the N-type Material carries out surface passivation, forms passivation layer 205；
S110, such as Fig. 6 g, at a temperature of 250 DEG C, utilize the HfO that atomic layer deposition processes deposition thickness is 4nm2Material 206；
S111, such as Fig. 6 h, in the HfO2The surface of material 206 utilizes reactive sputtering system depositing technics deposit TaN materials Material 207；
S112, such as Fig. 6 i, the TaN materials 207 and the HfO are etched using chlorine based plasma etching technics2Material 206 form gate regions.
S113, such as Fig. 6 j, using self-registered technology, inject BF different from the region of the gate regions on bulk substrate surface2 + Form source-drain area；
S114, such as Fig. 6 k, using electron beam evaporation process in the Ni materials that whole substrate surface deposition thickness is 10nm 208；
S115, such as Fig. 6 l, concentration is used to remove part Ni materials using selective wet processing for 96% concentrated sulfuric acid 208, ultimately form the strain GeSn PMOS devices.
Embodiment five
Fig. 7 is referred to, Fig. 7 is a kind of structural representation of computer provided in an embodiment of the present invention.The computer 70 can With including：Mainboard 71, video card 73, CPU75 and memory 77, the video card 73, the CPU75 and the memory 77 are arranged at On the mainboard 71, and the mainboard includes BIOS chips, I/O backplane interfaces, keyboard and panel control switch interface, internal memory Slot, CMOS batteries, north and south bridge chip, PCI slot (not shown)；Wherein, the video card 73, the CPU75 and described Memory 77 includes being made up of the integrated circuit that above-described embodiment provides.And the MOS device in integrated circuit, as NMOS, PMOS, CMOS device, it can be realized by above-mentioned process of preparing.
In summary, instantiation used herein is set forth to the principle and embodiment of the present invention, the above The explanation of embodiment is only intended to help the method and its core concept for understanding the present invention；Meanwhile for the general skill of this area Art personnel, according to the thought of the present invention, there will be changes in specific embodiments and applications, in summary, this Description be should not be construed as limiting the invention, and protection scope of the present invention should be defined by appended claim.

Claims (2)

  1. A kind of 1. preparation method of strain GeSn PMOS devices, it is characterised in that including：
    S101, choose single crystal Si substrate；
    S102, at a temperature of 275 DEG C~325 DEG C, the first of 40~50nm is grown on the single crystal Si substrate using CVD techniques Ge inculating crystal layers；
    S103, at a temperature of 500 DEG C~600 DEG C, using CVD techniques the first Ge seed crystal surfaces grow 150~ 250nm the 2nd Ge body layers；
    S103, using CVD techniques 150nm SiO are deposited in the 2nd Ge main body layer surfaces2Layer；
    S104, the single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge body layers and the SiO will be included2Layer Whole backing material is heated to 700 DEG C, continuously uses whole backing material described in laser technology crystallization, wherein, optical maser wavelength is 808nm, laser spot size 10mm × 1mm, laser power 1.5kW/cm2, laser traverse speed 25mm/s；
    Whole backing material described in S105, natural cooling；
    S106, utilize the dry etch process etching SiO2Layer, form Ge/Si void backing materials；
    S107, at a temperature of 350 DEG C, in the Ge/Si void substrate material surface using to depressurize CVD techniques growth thickness be 20nm Strain GeSn materials；
    S108, temperature be 400~500 DEG C at, the strain GeSn material surfaces injection P ion, injection length 200s, Form N-type strain GeSn materials；
    S109, at a temperature of 370 DEG C, using Si in situ2H6Surface passivation technique strains GeSn materials to the N-type and carries out surface Passivation；
    S110, at a temperature of 250 DEG C, utilize atomic layer deposition processes deposition thickness be 4nm HfO2Material；
    S111, in the HfO2Material surface utilizes reactive sputtering system depositing technics deposit TaN materials；
    S112, utilize the chlorine based plasma etching technics etching TaN materials and the HfO2Material forms gate regions.
    S113, using self-registered technology, inject BF different from the region of the gate regions on bulk substrate surface2 +Form source-drain area；
    S114, the Ni materials using electron beam evaporation process in whole substrate surface deposition thickness for 10nm；
    S115, use concentration to remove part Ni materials using selective wet processing for 96% concentrated sulfuric acid, ultimately form described Strain GeSn PMOS devices.
  2. 2. one kind strain GeSn PMOS devices, it is characterised in that including：Single crystal Si substrate, the first Ge inculating crystal layers, the 2nd Ge master Body layer and strain GeSn layers；Wherein, the strain GeSn PMOS devices are prepared as the method described in claim 1 forms.
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