CN107817954B - NAND Flash storage reliability evaluation method - Google Patents

NAND Flash storage reliability evaluation method Download PDF

Info

Publication number
CN107817954B
CN107817954B CN201711175059.4A CN201711175059A CN107817954B CN 107817954 B CN107817954 B CN 107817954B CN 201711175059 A CN201711175059 A CN 201711175059A CN 107817954 B CN107817954 B CN 107817954B
Authority
CN
China
Prior art keywords
chip
programming
erasing
nand flash
data block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201711175059.4A
Other languages
Chinese (zh)
Other versions
CN107817954A (en
Inventor
魏德宝
乔立岩
李绪金
郝梦琪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harbin Institute of Technology Shenzhen
Original Assignee
Harbin Institute of Technology Shenzhen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harbin Institute of Technology Shenzhen filed Critical Harbin Institute of Technology Shenzhen
Priority to CN201711175059.4A priority Critical patent/CN107817954B/en
Publication of CN107817954A publication Critical patent/CN107817954A/en
Application granted granted Critical
Publication of CN107817954B publication Critical patent/CN107817954B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0632—Configuration or reconfiguration of storage systems by initialisation or re-initialisation of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

A NAND Flash storage reliability assessment method relates to the field of solid state storage. The invention aims to solve the problem that a method for testing the reliability of a NAND Flash chip is lacked at present. Selecting a new NAND Flash chip, and establishing a model of the programming time of the chip changing along with the erasing and programming times; selecting a test chip with the same model as the first step, selecting a data block to be tested from the chip, erasing and programming the data block, and recording the programming time of each data block; and substituting the programming time obtained in the step two into the model in the step one to obtain the erasing and programming times of the test chip, comparing the obtained erasing and programming times with the programming and erasing times allowed by the chip in a chip manual, and if the erasing and programming times of the test chip are more than the erasing and programming times allowed by the chip, indicating that the reliability of the data stored in the test chip is reduced. For testing chip reliability.

Description

一种NAND Flash存储可靠性评估方法A kind of NAND Flash storage reliability evaluation method

技术领域technical field

本发明涉及一种NAND Flash存储可靠性评估方法。属于固态存储领域。The invention relates to a NAND Flash storage reliability evaluation method. It belongs to the field of solid-state storage.

背景技术Background technique

固态硬盘(Solid State Drives,SSDs)其内部是由多片NAND Flash(与非闪存)芯片组成的。SSDs具有抗震性强、速写速度快等优良特性，目前已经广泛应用于大规模数据中心、个人电脑和移动存储设备等领域。为提高SSDs的存储容量和降低其单位存储成本，NANDFlash也逐渐从单层单元(Single Level Cell,SLC)发展到多层单元(Multi-levelCell,MLC)。在相同体积下，MLC/TLC临近状态的阈值电压间距会明显变小。Solid State Drives (SSDs) are internally composed of multiple NAND Flash (and non-flash memory) chips. SSDs have excellent characteristics such as strong shock resistance and fast writing speed, and have been widely used in large-scale data centers, personal computers and mobile storage devices. In order to improve the storage capacity of SSDs and reduce the unit storage cost, NANDFlash has gradually developed from a single-level cell (SLC) to a multi-level cell (MLC). Under the same volume, the threshold voltage spacing of MLC/TLC adjacent states will be significantly smaller.

NAND Flash芯片生产工艺的提高在降低单位存储成本带来高性价比的同时，导致相邻阈值电压间距逐渐变小，不可避免地带来NAND Flash存储可靠性的降低。SLC型芯片P/E(擦写)次数为10000次，而MLC型芯片P/E次数为5000次。在芯片使用寿命周期内，随着磨损程度的不断加强，可靠性不断降低，胞元内氧化层逐渐变薄，芯片编程速度必然会发生比较明显的变化。基于上述原因，现在缺少一种测试NAND Flash芯片可靠性的方法。The improvement of the production process of NAND Flash chips not only reduces the unit storage cost and brings high cost performance, but also leads to the gradual reduction of the adjacent threshold voltage spacing, which inevitably reduces the storage reliability of NAND Flash. The SLC type chip P/E (erase and write) times is 10,000 times, while the MLC type chip P/E times are 5,000 times. During the service life of the chip, as the wear level continues to increase, the reliability continues to decrease, the oxide layer in the cell gradually becomes thinner, and the chip programming speed will inevitably change significantly. Based on the above reasons, there is currently a lack of a method for testing the reliability of NAND Flash chips.

发明内容SUMMARY OF THE INVENTION

本发明是为了解决现在缺少一种测试NAND Flash芯片可靠性的方法的问题。现提供一种NAND Flash存储可靠性评估方法。The present invention is to solve the problem that there is currently a lack of a method for testing the reliability of NAND Flash chips. A method for evaluating the reliability of NAND Flash storage is provided.

一种NAND Flash存储可靠性评估方法，所述方法包括以下步骤：A NAND Flash storage reliability evaluation method, the method comprises the following steps:

步骤一、选取新的NAND Flash芯片，建立该芯片的编程时间随擦除及编程次数变化的模型；Step 1. Select a new NAND Flash chip, and establish a model in which the programming time of the chip varies with erasing and programming times;

步骤二、选取与步骤一型号相同的测试芯片，从该芯片中选取需要测试的数据块，对该数据块进行擦除及编程操作，并记录各数据块的编程时间；Step 2, select the test chip with the same model as step 1, select the data block to be tested from the chip, carry out erasing and programming operations on the data block, and record the programming time of each data block;

步骤三、将步骤二中得到的编程时间带入步骤一中的模型中，得到测试芯片的擦除及编程次数，将得出的擦除及编程次数与芯片手册中该芯片所允许的编程及擦除次数比较，如果测试芯片的擦除及编程数次数大于芯片所允许的擦除及编程次数，说明测试芯片存储数据的可靠性降低。Step 3. Bring the programming time obtained in step 2 into the model in step 1 to obtain the erasing and programming times of the test chip, and compare the obtained erasing and programming times with the programming and programming allowed by the chip in the chip manual. Comparing the erasing times, if the erasing and programming times of the test chip are greater than the erasing and programming times allowed by the chip, it means that the reliability of the data stored in the test chip is reduced.

优选地，步骤一中，建立新的NAND Flash芯片的编程时间随擦除及编程次数的变化模型的具体过程为：Preferably, in step 1, the specific process of establishing a model of the change of the programming time of the new NAND Flash chip with the erasing and programming times is as follows:

从新的NAND Flash芯片中选取一定数量的数据块，对各个数据块进行不同次数的擦除及编程操作，相当于对芯片进行不同程度的人为磨损后，再对各数据块进行一次擦除及编程操作，并记录每个数据块的编程时间，从而绘制编程时间随擦除及编程次数的变化曲线，对曲线进行拟合，建立NAND Flash芯片的编程时间随擦除及编程次数的变化模型。Select a certain number of data blocks from the new NAND Flash chip, and perform different times of erasing and programming operations on each data block, which is equivalent to different degrees of artificial wear on the chip, and then erase and program each data block once. operation, and record the programming time of each data block, so as to draw the change curve of programming time with erasing and programming times, fit the curve, and establish the change model of NAND Flash chip programming time with erasing and programming times.

本发明的有益效果为：The beneficial effects of the present invention are:

本申请针对芯片编程时间与擦除及编程次数之间的关系，擦除及编程次数越多，芯片磨损程度越高，其可靠性越差，编程时间也就越短，利用这一关系选取新的NAND Flash芯片，建立该芯片的编程时间随擦除及编程次数变化的模型。对于要评估可靠性的测试芯片，只需对其进行一次擦除及编程操作，记录编程时间，将该时间带入由该型号的新芯片建立的模型中，就可以得到测试芯片的擦除及编程次数。随着擦除及编程次数的增加，芯片编程速度逐渐降低，测试芯片的磨损程度也会逐渐增加，从而测试芯片的存储数据的可靠性会越差。本发明申请可以方便快捷的评估芯片可靠性。This application aims at the relationship between the chip programming time and the erasing and programming times. A NAND Flash chip is used to establish a model of the change of the programming time of the chip with the number of erasing and programming. For the test chip to be evaluated for reliability, it is only necessary to perform an erasing and programming operation on it, record the programming time, and bring the time into the model established by the new chip of this type, and then the erasure and programming of the test chip can be obtained. programming times. With the increase of erasing and programming times, the chip programming speed gradually decreases, and the wear degree of the test chip also increases gradually, so that the reliability of the stored data of the test chip will be worse. The application of the present invention can easily and quickly evaluate the reliability of the chip.

1.该NAND Flash可靠性评估方法建模过程比较简单，只用少量的数据块即可建立芯片编程时间与可靠性之间的模型；1. The modeling process of the NAND Flash reliability evaluation method is relatively simple, and a model between chip programming time and reliability can be established with only a small number of data blocks;

2.该可靠性评估方法不用预先存储芯片已经历的擦除及编程次数，只需对要测试的芯片进行一次擦除及编程操作，记录编程时间，即可评估出芯片已经历的擦除及编程次数，也就是芯片的磨损程度，进而芯片可靠性就能评估出来。2. This reliability evaluation method does not need to pre-store the erasing and programming times that the chip has experienced. It only needs to perform an erasing and programming operation on the chip to be tested and record the programming time to evaluate the erasing and programming times that the chip has experienced. The number of programming, that is, the degree of wear and tear of the chip, and the reliability of the chip can be evaluated.

3.该可靠性评估方法可用于鉴别二手NAND Flash或者翻新NAND Flash的磨损程度。3. The reliability evaluation method can be used to identify the wear level of used NAND Flash or refurbished NAND Flash.

附图说明Description of drawings

图1为具体实施方式一所述的一种NAND Flash存储可靠性评估方法的流程图；1 is a flowchart of a method for evaluating the reliability of a NAND Flash storage according to Embodiment 1;

图2为MLC型芯片数据块编程时间随擦除及编程次数变化曲线图，其中，附图标记1表示拟合后的曲线；附图标记2表示根据实验数据绘制出的编程时间随擦除及编程次数的变化曲线。Fig. 2 is a graph showing the change of programming time of MLC chip data block with erasing and programming times, wherein reference numeral 1 represents the curve after fitting; reference numeral 2 represents the programming time drawn according to experimental data with erasing and programming times. Variation curve of programmed times.

具体实施方式Detailed ways

具体实施方式一：参照图1具体说明本实施方式，本实施方式所述的一种NANDFlash存储可靠性评估方法，所述方法包括以下步骤：Embodiment 1: This embodiment is described in detail with reference to FIG. 1. A method for evaluating the reliability of NAND Flash storage described in this embodiment includes the following steps:

步骤一、选取新的NAND Flash芯片，建立该芯片的编程时间随擦除及编程次数变化的模型；Step 1. Select a new NAND Flash chip, and establish a model in which the programming time of the chip varies with erasing and programming times;

步骤二、选取与步骤一型号相同的测试芯片，从该芯片中选取需要测试的数据块，对该数据块进行擦除及编程操作，并记录该数据块的编程时间；Step 2, select the test chip with the same model as step 1, select the data block to be tested from the chip, erase and program the data block, and record the programming time of the data block;

步骤三、将步骤二中得到的编程时间带入步骤一中的模型中，得到测试芯片的擦除及编程次数，将得出的擦除及编程次数与芯片手册中该芯片所允许的编程及擦除次数比较，如果测试芯片的擦除及编程数次数大于芯片所允许的擦除及编程次数，说明测试芯片存储数据的可靠性降低。Step 3. Bring the programming time obtained in step 2 into the model in step 1 to obtain the erasing and programming times of the test chip, and compare the obtained erasing and programming times with the programming and programming allowed by the chip in the chip manual. Comparing the erasing times, if the erasing and programming times of the test chip are greater than the erasing and programming times allowed by the chip, it means that the reliability of the data stored in the test chip is reduced.

本实施方式中，目前的固态存储以MLC型NAND Flash存储芯片为主，其存储可靠性与芯片编程(Program,P)及擦除(Erase,E)次数、擦写频度、工作温度、工作电压、工作时长等参数密切相关。芯片在寿命周期中随着磨损程度的不断加强，可靠性不断降低，其编程速度也随之发生变化。因此NAND Flash存储芯片的编程速度可作为芯片可靠性评估的依据。In this embodiment, the current solid-state storage is dominated by MLC-type NAND Flash memory chips. Parameters such as voltage and working time are closely related. As the chip becomes more wear-resistant and less reliable during its life cycle, its programming speed also changes. Therefore, the programming speed of the NAND Flash memory chip can be used as the basis for chip reliability evaluation.

NAND Flash芯片随着擦除及编程次数的增加，芯片编程速度逐渐降低。对于一片磨损程度未知的NAND Flash芯片，只需要对测试芯片进行一次擦除及编程操作，记录编程时间，将该时间带入由该芯片建立的模型中，就可以得到擦除及编程次数，即测试芯片的磨损程度，从而评估其可靠性。图2为MLC型芯片块编程时间随擦除及编程次数变化曲线。With the increase of erasing and programming times of NAND Flash chips, the chip programming speed gradually decreases. For a NAND Flash chip with an unknown degree of wear, it is only necessary to perform an erasing and programming operation on the test chip, record the programming time, and bring the time into the model established by the chip to obtain the erasing and programming times, that is, Test the chip for wear to assess its reliability. Figure 2 is a curve showing the change of programming time of MLC chip blocks with erasing and programming times.

具体实施方式二：本实施方式是对具体实施方式一所述的一种NAND Flash存储可靠性评估方法作进一步说明，本实施方式中，步骤一中，建立新的NAND Flash芯片的编程时间随擦除及编程次数的变化模型的具体过程为：Embodiment 2: This embodiment further describes a method for evaluating the reliability of NAND Flash storage described in Embodiment 1. In this embodiment, in step 1, the programming time for establishing a new NAND Flash chip varies with erasure. The specific process of the change model of division and programming times is as follows:

从新的NAND Flash芯片中选取一定数量的数据块，对各个数据块进行不同次数的擦除及编程操作，相当于对芯片进行不同程度的人为磨损后，再对各数据块进行一次擦除及编程操作，并记录每个数据块的编程时间，从而绘制编程时间随擦除及编程次数的变化曲线，对曲线进行拟合，建立NAND Flash芯片的编程时间随擦除及编程次数的变化模型。Select a certain number of data blocks from the new NAND Flash chip, and perform different times of erasing and programming operations on each data block, which is equivalent to different degrees of artificial wear on the chip, and then erase and program each data block once. operation, and record the programming time of each data block, so as to draw the change curve of programming time with erasing and programming times, fit the curve, and establish the change model of NAND Flash chip programming time with erasing and programming times.

本实施方式中，在芯片磨损的基础上，不同磨损程度的块编程所用的时间不同，测量数据块的编程时间才有意义。所以，对芯片进行不同程度的人为磨损后，再对各数据块进行一次擦除及编程操作，记录编程操作所用的编程时间。In this embodiment, on the basis of chip wear, it is meaningful to measure the programming time of the data blocks because the programming time of blocks with different degrees of wear is different. Therefore, after different degrees of artificial wear on the chip, each data block is erased and programmed once, and the programming time used for the programming operation is recorded.

具体实施方式三：本实施方式是对具体实施方式一所述的一种NAND Flash存储可靠性评估方法作进一步说明，本实施方式中，测试芯片与建模所用的新芯片的工作温度和工作电压均相同。Embodiment 3: This embodiment further describes a method for evaluating the reliability of NAND Flash storage described in Embodiment 1. In this embodiment, the operating temperature and operating voltage of the test chip and the new chip used for modeling are the same.

Claims (2)

1. A NAND Flash storage reliability evaluation method is characterized by comprising the following steps:
step one, selecting a new NAND Flash chip, and establishing a model of the programming time of the chip changing along with the erasing and programming times;
the specific process of establishing a new model of the change of the programming time of the NAND Flash chip along with the erasing and programming times is as follows:
selecting a certain number of data blocks from a new NAND Flash chip, performing erasing and programming operations on each data block for different times, namely performing artificial abrasion on the chip to different degrees, performing one erasing and programming operation on each data block, recording the programming time of each data block, drawing a change curve of the programming time along with the erasing and programming times, fitting the curve, and establishing a change model of the programming time of the NAND Flash chip along with the erasing and programming times;
step two, selecting a test chip with the same model as that of the step one, selecting a data block to be tested from the chip, erasing and programming the data block, and recording the programming time of the data block;
and step three, substituting the programming time obtained in the step two into the model in the step one to obtain the erasing and programming times of the test chip, comparing the obtained erasing and programming times with the programming and erasing times allowed by the chip in a chip manual, and if the erasing and programming times of the test chip are greater than the erasing and programming times allowed by the chip, indicating that the reliability of the data stored in the test chip is reduced.
2. The method for evaluating the storage reliability of the NAND Flash according to claim 1, wherein the working temperature and the working voltage of the test chip are the same as those of a new chip used for modeling.
CN201711175059.4A 2017-11-22 2017-11-22 NAND Flash storage reliability evaluation method Active CN107817954B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711175059.4A CN107817954B (en) 2017-11-22 2017-11-22 NAND Flash storage reliability evaluation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711175059.4A CN107817954B (en) 2017-11-22 2017-11-22 NAND Flash storage reliability evaluation method

Publications (2)

Publication Number Publication Date
CN107817954A CN107817954A (en) 2018-03-20
CN107817954B true CN107817954B (en) 2020-07-24

Family

ID=61609646

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711175059.4A Active CN107817954B (en) 2017-11-22 2017-11-22 NAND Flash storage reliability evaluation method

Country Status (1)

Country Link
CN (1) CN107817954B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831517B (en) * 2018-05-23 2021-04-27 武汉忆数存储技术有限公司 Method and test device for judging reliability of flash memory chip based on operation time or current
CN109582224A (en) * 2018-11-12 2019-04-05 哈尔滨工业大学 A kind of NAND Flash memory reliability optimization method based on self- recoverage effect
CN110033818B (en) * 2019-03-20 2021-01-22 上海华虹宏力半导体制造有限公司 SONOS flash memory chip programming voltage screening method
CN111341375B (en) * 2020-02-19 2020-12-01 哈尔滨工业大学 A threshold voltage acquisition method for TLC-type NAND Flash
CN111950675B (en) * 2020-08-12 2022-01-07 深圳安捷丽新技术有限公司 System and method for evaluating memory media

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826367A (en) * 2009-06-02 2010-09-08 深圳市朗科科技股份有限公司 Method and device for monitoring reliability of semiconductor storage device
CN102520879A (en) * 2011-11-30 2012-06-27 广东威创视讯科技股份有限公司 Priority-based file information storage method, device and system
CN104766629A (en) * 2014-01-07 2015-07-08 北京兆易创新科技股份有限公司 Method for enhancing reliability of NAND type FLASH

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8737141B2 (en) * 2010-07-07 2014-05-27 Stec, Inc. Apparatus and method for determining an operating condition of a memory cell based on cycle information

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826367A (en) * 2009-06-02 2010-09-08 深圳市朗科科技股份有限公司 Method and device for monitoring reliability of semiconductor storage device
CN102520879A (en) * 2011-11-30 2012-06-27 广东威创视讯科技股份有限公司 Priority-based file information storage method, device and system
CN104766629A (en) * 2014-01-07 2015-07-08 北京兆易创新科技股份有限公司 Method for enhancing reliability of NAND type FLASH

Also Published As

Publication number Publication date
CN107817954A (en) 2018-03-20

Similar Documents

Publication Publication Date Title
CN107817954B (en) NAND Flash storage reliability evaluation method
US8806106B2 (en) Estimating wear of non-volatile, solid state memory
US11763908B2 (en) Memory system tester using test pad real time monitoring
CN110851079A (en) Adaptive storage device loss balancing method and system
US9734919B2 (en) Recovery of interfacial defects in memory cells
CN106909318B (en) Solid state disk using method and device
KR101905266B1 (en) Data retention charge loss sensor
Wu et al. Characterizing 3D charge trap NAND flash: Observations, analyses and applications
JP4819951B2 (en) Nonvolatile memory and method for linear estimation of initial programming voltage
KR101190742B1 (en) Controller for memory and storage system includint the same, method for measuring life span of memory
US9535611B2 (en) Cache memory for hybrid disk drives
Peleato et al. BER-based wear leveling and bad block management for NAND flash
CN105427886B (en) Data substep emphasis method during NAND Flash storage system saves
TWI606336B (en) Memory device and control unit thereof, and data storage method for memory device
CN106856102B (en) Programming method for Nand Flash
CN105405462B (en) NAND Flash storage system high eroded area data pre-emphasis method
CN112466387B (en) Quick test method for NAND FLASH chip read-write life
US11914490B2 (en) Reactive read based on metrics to screen defect prone memory blocks
CN110837477A (en) A storage system wear leveling method and device based on life prediction
US9442842B2 (en) Memory system performance configuration
CN107680632B (en) Method and device for testing service life of solid state disk
TWI455140B (en) Flash memory usage period assessment method
CN110580932B (en) A storage unit quality measurement method applied to wear leveling
US20240242768A1 (en) Controlling erase-to-program delay for improving data retention
CN110660446B (en) A device for evaluating data residues in non-volatile memory in a single-chip microcomputer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant