CN107817954B - NAND Flash storage reliability evaluation method - Google Patents
NAND Flash storage reliability evaluation method Download PDFInfo
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- CN107817954B CN107817954B CN201711175059.4A CN201711175059A CN107817954B CN 107817954 B CN107817954 B CN 107817954B CN 201711175059 A CN201711175059 A CN 201711175059A CN 107817954 B CN107817954 B CN 107817954B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0632—Configuration or reconfiguration of storage systems by initialisation or re-initialisation of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
A NAND Flash storage reliability assessment method relates to the field of solid state storage. The invention aims to solve the problem that a method for testing the reliability of a NAND Flash chip is lacked at present. Selecting a new NAND Flash chip, and establishing a model of the programming time of the chip changing along with the erasing and programming times; selecting a test chip with the same model as the first step, selecting a data block to be tested from the chip, erasing and programming the data block, and recording the programming time of each data block; and substituting the programming time obtained in the step two into the model in the step one to obtain the erasing and programming times of the test chip, comparing the obtained erasing and programming times with the programming and erasing times allowed by the chip in a chip manual, and if the erasing and programming times of the test chip are more than the erasing and programming times allowed by the chip, indicating that the reliability of the data stored in the test chip is reduced. For testing chip reliability.
Description
Technical Field
The invention relates to a NAND Flash storage reliability evaluation method. Belongs to the field of solid state storage.
Background
In order to improve the storage capacity of the SSDs and reduce the unit storage cost of the SSDs, NANDFlash is gradually developed from a Single-layer unit (Single L ev Cell, S L C) to a Multi-layer unit (Multi-level Cell, M L C). under the same volume, the threshold voltage interval of an M L C/T L C adjacent State is obviously reduced.
The P/E (erasing and writing) frequency of an S L C type chip is 10000 times, and the P/E frequency of an M L C type chip is 5000 times.
Disclosure of Invention
The invention aims to solve the problem that a method for testing the reliability of a NAND Flash chip is lacked at present. A NAND Flash storage reliability evaluation method is provided.
A NAND Flash storage reliability evaluation method comprises the following steps:
step one, selecting a new NAND Flash chip, and establishing a model of the programming time of the chip changing along with the erasing and programming times;
step two, selecting a test chip with the same model as that of the step one, selecting a data block to be tested from the chip, erasing and programming the data block, and recording the programming time of each data block;
and step three, substituting the programming time obtained in the step two into the model in the step one to obtain the erasing and programming times of the test chip, comparing the obtained erasing and programming times with the programming and erasing times allowed by the chip in a chip manual, and if the erasing and programming times of the test chip are more than the erasing and programming times allowed by the chip, indicating that the reliability of the data stored in the test chip is reduced.
Preferably, in the step one, the specific process of establishing a model of the change of the programming time of the new NAND Flash chip along with the erasing and programming times is as follows:
selecting a certain number of data blocks from a new NAND Flash chip, carrying out erasing and programming operations on each data block for different times, namely carrying out artificial abrasion on the chip in different degrees, carrying out one erasing and programming operation on each data block, recording the programming time of each data block, drawing a change curve of the programming time along with the erasing and programming times, fitting the curve, and establishing a change model of the programming time of the NAND Flash chip along with the erasing and programming times.
The invention has the beneficial effects that:
according to the method, aiming at the relation between the programming time of the chip and the erasing and programming times, the erasing and programming times are more, the abrasion degree of the chip is higher, the reliability is worse, and the programming time is shorter, a new NAND Flash chip is selected by utilizing the relation, and a model of the programming time of the chip changing along with the erasing and programming times is established. For a test chip to be evaluated for reliability, only one erasing and programming operation is needed to be carried out on the test chip, programming time is recorded, and the time is brought into a model established by a new chip of the type, so that the erasing and programming times of the test chip can be obtained. As the number of times of erasing and programming increases, the programming speed of the chip gradually decreases, and the wear degree of the test chip gradually increases, so that the reliability of the stored data of the test chip is worse. The method and the device can conveniently and quickly evaluate the chip reliability.
1. The NAND Flash reliability evaluation method has a simple modeling process, and a model between chip programming time and reliability can be established only by using a small number of data blocks;
2. the reliability evaluation method does not need to pre-store the erasing and programming times of the chip, only needs to perform one-time erasing and programming operation on the chip to be tested, records the programming time, and can evaluate the erasing and programming times of the chip, namely the abrasion degree of the chip, so that the reliability of the chip can be evaluated.
3. The reliability evaluation method can be used for identifying the abrasion degree of the second-hand NAND Flash or the renovated NAND Flash.
Drawings
FIG. 1 is a flowchart illustrating a method for evaluating storage reliability of NAND Flash according to a first embodiment;
FIG. 2 is a graph of programming time versus erase and program times for a M L C chip data block, wherein reference numeral 1 represents the fitted curve, and reference numeral 2 represents the programming time versus erase and program times plotted from experimental data.
Detailed Description
The first embodiment is as follows: specifically describing the present embodiment with reference to fig. 1, the method for evaluating nand flash storage reliability in the present embodiment includes the following steps:
step one, selecting a new NAND Flash chip, and establishing a model of the programming time of the chip changing along with the erasing and programming times;
step two, selecting a test chip with the same model as that of the step one, selecting a data block to be tested from the chip, erasing and programming the data block, and recording the programming time of the data block;
and step three, substituting the programming time obtained in the step two into the model in the step one to obtain the erasing and programming times of the test chip, comparing the obtained erasing and programming times with the programming and erasing times allowed by the chip in a chip manual, and if the erasing and programming times of the test chip are more than the erasing and programming times allowed by the chip, indicating that the reliability of the data stored in the test chip is reduced.
In this embodiment, the current solid-state storage is mainly an M L C NAND Flash memory chip, and the storage reliability thereof is closely related to parameters such as chip programming (P) and erasing (Erase, E) times, erasing frequency, operating temperature, operating voltage, operating duration, etc. the reliability of the chip is continuously reduced along with the continuous enhancement of the wear degree in the life cycle, and the programming speed thereof is also changed, so the programming speed of the NAND Flash memory chip can be used as the basis for chip reliability evaluation.
For a NAND Flash chip with unknown wear degree, only one erasing and programming operation is needed to be carried out on a test chip, programming time is recorded, the time is substituted into a model established by the chip, the erasing and programming times, namely the wear degree of the test chip, can be obtained, and therefore the reliability of the test chip is evaluated, and FIG. 2 is a curve of the programming time of M L C type chip blocks along with the change of the erasing and programming times.
The second embodiment is as follows: in this embodiment, in the first step, the specific process of establishing a new model of the change of the programming time of the NAND Flash chip along with the erase and programming times is as follows:
selecting a certain number of data blocks from a new NAND Flash chip, carrying out erasing and programming operations on each data block for different times, namely carrying out artificial abrasion on the chip in different degrees, carrying out one erasing and programming operation on each data block, recording the programming time of each data block, drawing a change curve of the programming time along with the erasing and programming times, fitting the curve, and establishing a change model of the programming time of the NAND Flash chip along with the erasing and programming times.
In this embodiment, it is significant to measure the programming time of a data block only if the time taken for programming blocks of different wear levels is different based on the wear of the chip. Therefore, after the chip is worn out artificially in different degrees, each data block is erased and programmed once, and the programming time used by the programming operation is recorded.
The third concrete implementation mode: in this embodiment, the working temperature and the working voltage of the test chip and the new chip used for modeling are the same.
Claims (2)
1. A NAND Flash storage reliability evaluation method is characterized by comprising the following steps:
step one, selecting a new NAND Flash chip, and establishing a model of the programming time of the chip changing along with the erasing and programming times;
the specific process of establishing a new model of the change of the programming time of the NAND Flash chip along with the erasing and programming times is as follows:
selecting a certain number of data blocks from a new NAND Flash chip, performing erasing and programming operations on each data block for different times, namely performing artificial abrasion on the chip to different degrees, performing one erasing and programming operation on each data block, recording the programming time of each data block, drawing a change curve of the programming time along with the erasing and programming times, fitting the curve, and establishing a change model of the programming time of the NAND Flash chip along with the erasing and programming times;
step two, selecting a test chip with the same model as that of the step one, selecting a data block to be tested from the chip, erasing and programming the data block, and recording the programming time of the data block;
and step three, substituting the programming time obtained in the step two into the model in the step one to obtain the erasing and programming times of the test chip, comparing the obtained erasing and programming times with the programming and erasing times allowed by the chip in a chip manual, and if the erasing and programming times of the test chip are greater than the erasing and programming times allowed by the chip, indicating that the reliability of the data stored in the test chip is reduced.
2. The method for evaluating the storage reliability of the NAND Flash according to claim 1, wherein the working temperature and the working voltage of the test chip are the same as those of a new chip used for modeling.
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| CN108831517B (en) * | 2018-05-23 | 2021-04-27 | 武汉忆数存储技术有限公司 | Method and test device for judging reliability of flash memory chip based on operation time or current |
| CN109582224A (en) * | 2018-11-12 | 2019-04-05 | 哈尔滨工业大学 | A kind of NAND Flash memory reliability optimization method based on self- recoverage effect |
| CN110033818B (en) * | 2019-03-20 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | SONOS flash memory chip programming voltage screening method |
| CN111341375B (en) * | 2020-02-19 | 2020-12-01 | 哈尔滨工业大学 | Threshold voltage obtaining method for TLC type NAND Flash |
| CN111950675B (en) * | 2020-08-12 | 2022-01-07 | 深圳安捷丽新技术有限公司 | System and method for evaluating memory media |
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| CN101826367A (en) * | 2009-06-02 | 2010-09-08 | 深圳市朗科科技股份有限公司 | Method and device for monitoring reliability of semiconductor storage device |
| CN102520879A (en) * | 2011-11-30 | 2012-06-27 | 广东威创视讯科技股份有限公司 | Priority-based file information storage method, device and system |
| CN104766629A (en) * | 2014-01-07 | 2015-07-08 | 北京兆易创新科技股份有限公司 | Method for enhancing reliability of NAND type FLASH |
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| US8737141B2 (en) * | 2010-07-07 | 2014-05-27 | Stec, Inc. | Apparatus and method for determining an operating condition of a memory cell based on cycle information |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101826367A (en) * | 2009-06-02 | 2010-09-08 | 深圳市朗科科技股份有限公司 | Method and device for monitoring reliability of semiconductor storage device |
| CN102520879A (en) * | 2011-11-30 | 2012-06-27 | 广东威创视讯科技股份有限公司 | Priority-based file information storage method, device and system |
| CN104766629A (en) * | 2014-01-07 | 2015-07-08 | 北京兆易创新科技股份有限公司 | Method for enhancing reliability of NAND type FLASH |
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