CN1077988C

CN1077988C - Setter of system resetting state

Info

Publication number: CN1077988C
Application number: CN95119891A
Authority: CN
Inventors: 余国成
Original assignee: Holtek Semiconductor Inc
Current assignee: Holtek Semiconductor Inc
Priority date: 1995-12-15
Filing date: 1995-12-15
Publication date: 2002-01-16
Anticipated expiration: 2015-12-15
Also published as: CN1152215A

Abstract

The present invention relates to a setter of a system resetting state for setting a system resetting state, which comprises a power supply stability detecting circuit, a delay circuit, an oscillator stability detecting circuit and a potential controller, wherein after the potential controller receives signals that a system power supply and an oscillation frequency are both in a stable state, the output terminal of the potential controller is down to a low potential from a high potential, and the system resetting state is completed. A system is ensured to work in the stable state and action errors caused by unstable system state parameters are avoided.

Description

The setting device of system reset state

The present invention relates to a kind of setting device of system state, refer to a kind of setting device of system reset state especially.

The stable end of distinguishing of General System relies on a reset signal, that is, when reset signal is in noble potential (High) state, expression system still end is stable, be in Reset Status, when reset signal when noble potential becomes electronegative potential (Low), the expression Reset Status finishes, system state is stable can to begin operate as normal.

By and large, whether system stability need consider following several factor:

1. the stability of supply voltage:

When system just started shooting, supply voltage is mostly non-to be a stationary value, but has the state of fluctuation, did not stablize this reset signal and promptly became Low by High if treat supply voltage, and system is started working, and then the fluctuation of supply voltage will cause the error of system acting.

2. initial value is set:

When system starts working, the setting of initial value must be done, because of system program when carrying out, beginning to rely on this initial value is that the numerical basis of system is carried out control action, reset signal does not promptly become Low from High if the setting of initial value is finished as yet, then system often obtains the initial value of a mistake, and influence various computings and control action thereafter.

3. the stability of system oscillator frequency:

Starting of oscillation when oscillator is just started shooting in system fails to reach double amplitude in the starting of oscillation initial stage more, that is, the frequency at starting of oscillation initial stage will be greater than normal system oscillation frequency, if in frequency stable as yet in, Reset Status promptly finishes, then this too high frequency will influence the normal operating conditions of system.

4. the immunity of power supply clutter:

In the start initial stage, supply voltage is mingled with the part clutter unavoidably, if after Reset Status finishes, this clutter does not disappear yet, and then the duty of system can produce error.

The reset signal () that the setting system of the Reset Status of prior art directly produces single pulse gives system; when pulse signal becomes Low (" low ") by High (" height "); system promptly starts working; yet; because when the reset signal of prior art becomes Low by High; the stability that does not have the various parameters of first detection system is so when regular meeting had the various parameters of system not tend towards stability as yet, Reset Status promptly finished.Like this then influenced the correctness of system works.The influence that the setting of the reset signal of this kind prior art is produced when being applied in microprocessor is obvious especially, because of the action of microprocessor is that built-in program cooperates the hardware configuration of itself to form, promptly do not move if the parameter of hardware is stablized built-in program as yet, then influenced the correctness of its action widely.

Fundamental purpose of the present invention is to provide the setting device of a system reset state, and it makes the power supply of system and the Reset Status that oscillation frequency is in steady state (SS) rear ends with system, in case the error of locking system work.

The present invention is a kind of setting device of system reset state, and it is used to set the Reset Status of a system, comprising: a stability of power supply testing circuit, in order to the stability of the power supply that detects this system; One oscillator degree of stability testing circuit is in order to the stability of detection system oscillation frequency; One potentiometric controller, its input is connected in the output of the output of this stability of power supply testing circuit and this oscillator degree of stability testing circuit and receives a reset signal, be not in steady state (SS) or described oscillator degree of stability testing circuit and detect the system oscillation frequency when unstable when described stability of power supply testing circuit detects system, control the current potential that output that described potentiometric controller makes described potentiometric controller still is in Reset Status; When described stability of power supply testing circuit detects system and is in steady state (SS) or described oscillator degree of stability testing circuit and detects the system oscillation frequency stabilization, control the output that described potentiometric controller makes described potentiometric controller and be in the current potential of resetting and finishing.

The setting device of this system reset state further comprises: a delay circuit, be electrically connected on this potentiometric controller, the variation that detects power supply in this stability of power supply testing circuit is during less than certain value, be subjected to the startup of this stability of power supply testing circuit, and the set time that picks up counting, and when in this set time, no longer being started, confirm that this power supply is really stable, give this potentiometric controller and send a high potential signal.

This potentiometric controller comprises: one or the door, its input end receives the output of this reset signal and this stability of power supply testing circuit respectively; One with the door, its input end receives the output of this delay circuit and the output of this oscillator degree of stability testing circuit respectively; One R-S latch circuit, be electrically connected on this or door and should and door, the current potential of this reset signal is kept in its output, and when this was output as noble potential with door, the side changed the potential state of this output, made the system finishing Reset Status.

Certainly, the present invention also can make this oscillator degree of stability testing circuit be electrically connected on this delay circuit, make delay circuit confirm that this power supply is really stable after, the side triggers the stability of this oscillator degree of stability testing circuit detection system oscillation frequency

This oscillator degree of stability testing circuit comprises: a schmitt trigger, in order to the less amplitude signal in the filtering appts oscillator signal; One frequency eliminator is electrically connected on this schmitt trigger, in order to strengthen and to stablize the amplitude of this oscillation frequency.

The present invention makes and is understood in depth by following accompanying drawing and detailed description:

Fig. 1: be a preferred embodiment synoptic diagram of this device.

See also Fig. 1, apparatus of the present invention comprise: a stability of power supply testing circuit 1, a delay circuit 2, an oscillator degree of stability testing circuit 3, and a potentiometric controller 4; In present embodiment, this oscillator degree of stability testing circuit 3 can be made up of a schmitt trigger 31 and a frequency eliminator 32, and this potentiometric controller 4 comprises: one or door 41, one and 42, and a S-R latch unit 43.

The present invention moves as follows: when system is reset, have a reset signal R _IN1Produce, make or an input end S1 of door 41 is in " height " (High) state,, make the output R of potentiometric controller 4 again because the effect of S-R internal lock device 43 _IN2Also be in " high " state, that is system is in Reset Status, whether 1 detection system supply voltage of stability of power supply testing circuit is stable, if the variation of power supply surpasses certain value, then produces a pulse signal, makes S2 be in high potential state, then R _IN2Can still be maintained at " high " state, system be remained be in Reset Status; When stability of power supply testing circuit 1 generation pulse signal gives potential controlling apparatus 4, can start delay circuit 2 simultaneously, make delay circuit 2 produce the delay of a set time, if stability of power supply testing circuit 1 does not start delay circuit 2 once more in this set time, the expression power supply is stable, then delay circuit 2 will make its output R1 be in " high " state, if and stability of power supply testing circuit 1 still continues to start this delay circuit 2 in this time delay, represent that then system power supply degree of stability testing circuit 1 still continues to start this delay circuit 2, represent that then system is unstable as yet, then delay circuit will be in being subjected to when mobile the reclocking should time delay at every turn, and do not make output R1 be in " high " state; Oscillator degree of stability testing circuit 3 can be in order to the stability of detection system oscillation frequency, when it receives the oscillator signal of system, the oscillator signal of this system is filtered through a schmitt trigger 31, make the too small oscillator signal of amplitude earlier by filtering, make this system oscillation signal lag with a frequency eliminator 32 again, after amplitude of oscillation is tended towards stability, send its output of pulse enable signal R2 again and be " height "; And potentiometric controller 4 must be waited until when R1, R2 all are in " height ", and it exports R _IN2Just can transfer " low " (Low) state to, the Reset Status of system is finished; That is, in reset signal R _IN1After the input, need wait until that stability of power supply testing circuit 1 detects power supply and has been in steady state (SS), and the steady state (SS) of power supply also must be through delay circuit 2 affirmations, after oscillator degree of stability testing circuit 3 also makes oscillation frequency stable simultaneously, the output R of potentiometric controller 4 _IN2Just can transfer " low " to, Reset Status is finished by " height ".

Subsidiary one carry be, when system stable and after Reset Status is finished, if stability of power supply testing circuit 1 detects power supply again in duty unsettled situation is arranged, then it is also by the potential state that changes S2, make the output of potentiometric controller 4 transfer noble potential to, and reset system once more, till power supply is stable.

In addition, among the embodiment of above-mentioned Fig. 1, oscillator degree of stability testing circuit 3 there is no with delay circuit 2 and connects, and this has represented that the stable detection of detection that power supply is stable and oscillation frequency can independently carry out.But, the present invention also can make this oscillator degree of stability testing circuit 3 be electrically connected on this delay circuit 2, make delay circuit 2 confirm that these power supplys are really stable after, trigger the stability of these oscillator degree of stability testing circuit 3 detection system oscillation frequency again.

So, when the present invention produces in reset signal, the degree of stability of while detection system power supply and oscillation frequency, after treating that each parameter is all stable, just make reset signal reduce to " low " and end Reset Status, make anti-locking system because of the power supply instability, system's error that power supply clutter or oscillation frequency instability are promptly started working and caused.

Though the present invention can make various modifications by the personnel that are familiar with this skill, do not break away from the protection of asking as attached claim.

Claims

1. the setting device of a system reset state, it comprises in order to set the Reset Status of a system:

One stability of power supply testing circuit is in order to the stability of the power supply that detects this system;

One oscillator degree of stability testing circuit is in order to the stability of detection system oscillation frequency;

One potentiometric controller, its input is connected in the output of the output of this stability of power supply testing circuit and this oscillator degree of stability testing circuit and receives a reset signal, be not in steady state (SS) or described oscillator degree of stability testing circuit and detect the system oscillation frequency when unstable when described stability of power supply testing circuit detects system, control the current potential that output that described potentiometric controller makes described potentiometric controller still is in Reset Status; When described stability of power supply testing circuit detects system and is in steady state (SS) or described oscillator degree of stability testing circuit and detects the system oscillation frequency stabilization, control the output that described potentiometric controller makes described potentiometric controller and be in the current potential of resetting and finishing.

2. the setting device of the system as claimed in claim 1 Reset Status, the setting device of this system reset state further comprises:

One delay circuit, be electrically connected on this potentiometric controller, the variation that detects power supply in this stability of power supply testing circuit is during less than certain value, be subjected to the startup of this stability of power supply testing circuit, and the set time that picks up counting, and when in this set time, no longer being started, confirm that this power supply is really stable, give this potentiometric controller and send a high potential signal.

3. the setting device of system reset state as claimed in claim 2, this potentiometric controller comprises:

One or the door, its input end receives the output of this reset signal and this stability of power supply testing circuit respectively;

One with the door, its input end receives the output of this delay circuit and the output of this oscillator degree of stability testing circuit respectively;

One R-S latch circuit, be electrically connected on this or door and should and door, the current potential of this reset signal is kept in its output, and in this during with the output noble potential of door, the side changes the potential state of this output, makes the system finishing Reset Status.

4. the setting device of system reset state as claimed in claim 3, wherein this oscillator degree of stability testing circuit is for being electrically connected on this delay circuit, after making delay circuit confirm that this power supply is really stable, the side triggers the stability of this oscillator degree of stability testing circuit detection system oscillation frequency.

5. the setting device of system reset state as claimed in claim 3, this oscillator degree of stability testing circuit comprises:

One schmitt trigger is in order to the less amplitude signal in the filtering appts oscillation frequency signal;

One frequency eliminator is electrically connected on this schmitt trigger, in order to strengthen and to stablize the amplitude of this oscillation frequency.